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DPC-7
CIRCUIT DESCRIPTION
288
C212
(clocks)
are
included
in a frame,
and
the
number of times of operation of the RAM in it is 197 times at
maximum.
In the system control block, against request 1, the timing of
its occurrence
is reserved
in advance.
Requests
2, 3 are
generated simultaneously, priority is given to request 2, and if
a@ request is generated
during execution
of either request,
priority is given to the job in execution:
(6) Jitter margin
The
EFM
demodulation
data
is synchronized
with
data's
playback system (PLL) as described earlier. Accordingly, it in-
cludes disturbance (wow, flutter, etc.) of disc rotation servo,
etc. It is loaded to the external RAM. As the data taken out of
the RAM
is synchronized
with the clock of X'tal system, this
RAM is subjected to time axis correction.
However, the limit of time axis correction is determined by the
capacity of the RAM.
In this system, other data is destroyed
when readiwrite frames are spaced apart by +5 frames. In
such
a
status
how
the
playback
sound
is cannot
be
guaranteed. The base counter monitor is provided in order to
avoid it.
In other
words,
when
the difference
between
read
base
counter and write base counter exceeds +4 frames, the write
base counter is set in the value of the read base counter.
AS a result, there is no case where data without error correc-
tion is output to the D/A.
The RAOV signal is of ''H'' for one frame (WFCK)
section
when
the difference between
base counters exceeded
+4
frames.
5. Error correction
(1)
The error correction block makes correction up to double
errors with each of C1 correction and C2 correction.
(2)
This system adopts a unique pointer erasure method in
order to minimize erroneous correction. Accordingly, the
external 16K RAM stores these pointer data in addition to
audio data.
(3)
The
pointer
generated
in C1
correction
is called
C1
pointer and the pointer generated in C2 correction is call-
ed C2 pointer.
(4)
When the data of C1 system is judged as reliable, a C1
pointer is set in this system.
(5)
During C2 correction, whether correction is to be made
or not to be made and whether the data is reliable or
unreliable
are judged
from
the error location,
locations
and number of C1 pointers obtained through computa-
tion.
A C2
pointer is set against an
unreliable
word
(16-bit).
(6)
The word in which a C2 pointer was set is subjected to
previous value hold or mean value interpolation when it is
output out of this LSI.
(7)
Terminal
C2FL
becomes
''H'' when
one
or more
C1
pointers are set in the data included in the C2 system at
the time
of C2 correction.
C2FL
is reset to ''L''
in
minimum
472ns
(see
Note)
after deactivation
of pin
RFCK. C2FL is the AND of C2F1 and C2F2.
Note: 472ns: One period of 2.1168 MHz
(8)
The flow of data with the external RAM is as follows.
A data request is made from the correction block to the
RAM interface block.
The RAM interface block accepts the request with the
operating situation of the entire system observed. The
address of the requested data is generated to the exter-
nal RAM.
Read/Write
of the correction
block and RAM
data are
enabled.
(9)
When
PSSL is set at ''L'', a signal that is capable of
monitoring error correction is output.
C1F1, C1F2, C2F1
and C2F2 output to DAO1
- DAO4
are these monitor signals. These signals are reset to ''L''
when
a period of minimum
472ns
has elapsed since
deactivation of RFCK.
The levels and meanings of these signals at the time of
deactivation of RFCK are as follows.
7
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