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DPC-77
CIRCUIT DESCRIPTION
(2)
Detection,
protection and interpolation of frame syn-
chronizing signals
There are cases during recording where the same pattern is
detected in the data due to the influence of drop-out and jitter,
even if a pattern that is same as the synchronizing signal will
not appear.
On the other hand, there also are cases where original frame
synchronizing
signal is not detected.
Therefore,
protection
and interpolation are required besides detection.
The edge portion only of EFM
signal (EFMO)
latched with
PLCK is converted to ''1'' and the rest to '0°', and then input
is to a 23-bit shift register and a frame synchronizing signal is
detected.
In order to protect a frame synchronizing signal, a window is
provided
and the same
patterns outside
of this window
are
removed. This width can be selected with WSEL.
If no frame synchronizing signal is located in this window, in-
terpolation
is made
with
a signal
produced
by 588-mal
counter (4.3218 MHz/588 = 7.35 kHz)
A 4-bit counter for counting the number of these frames to be
interpolated is provided, and when its count reaches the level
selected with GSEL, GSEM,
the window
is ignored and the
4-bit counter
is reset
with
the next
frame
synchronizing
signal. The GTOP pin is of ''H'' while this operation is per-
formed.
Further, GSF pin is of ''H'' when
the frame syn-
chronizing signal generated by the 588-mal counter for mak-
ing interpolation is synchronized with the frame synchronizing
signal from the disc.
The frame synchronizing signal before passage through the
window or the window is output out of UGFS (DAOS5 pin at
the time when PSSL=L).
WSEL | Window width
+3 clock
+7 clock
Number of frame to
be interpolated
UGFS (PSSL=L)
2 frames
Window
4 frames
Window
8 frames
Frame synchroniz-
ing signal before
passage through
window.
+—
13 frames
Window
The timing for write request signal (WREQ).
Write Frame
Clock (WECK), etc. is generated based on the protected and
interpolated frame synchronizing signal.
(3) EFM demodulation
14-bit data is taken out of the 23-bit shift register and is
demodulated
to 8-bit data through 14 =—~8 conversion circuit
composed
of array logics.
Then
a write
request
(WREQ)
signal is output to the RAM
interface block, and the data is
then output to the data bus (DBO8 - DBO1 pins) of the RAM in
accordance with the OENB signal transmitted from said block.
3.
Sub code demodulation
(1) Sub code demodulation
Synchronizing signals SO and S1 of 14-bit sub codes are
detected out of the 23-bit shift register, and sampling is made
in the timing that is synchronized with WFCK.
After delay of SO by one frame,
SO+S1
is output out of
SCOR pin and SO - S1 is output out of SBSO pin (only when
SCOR =H).
Data (P - W) of sub codes only is input to the register in the
timing synchronized with WFCK after EFM demodulation; and
sub code Q is output out of SUBQ pin, and at the same time, it
is loaded in the 8-bit shift register and is output out of SBSO
pin in correspondence to a clock from EXCK pin.
The
details
of this timing
will be shown
in '1, CPU
interface''. (Page 28)
(2) Sub code Q error detection
The CRC result of sub code Q is output from the CRCF pin in
synchronism with the SCOR pin.
It goes ''L'' when an error is detected. If the CRCQ flag is '17'
at this time, the CRCF flag is output from the SUBQ pin during
the time from the rising edge of the SCOR pin to the trailing
edge of the SUBQ pin. This timing is detailed in ''1. CPU in-
terface'.
37
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