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CIRCUIT DESCRIPTION
Explanation of functions
1. CPU interface
(1)
Data input
Each register may be set by input of 4-bit address, and 4-bit
data from LSB in the timing that is shown in Fig. 1 to three
pins, XLT, CLK and DATA. The address and data of each pin
}+—_—_——-
Data
SS
Address
4
Fig. 1 Timing chart for data input
(2) Registers
Register
9 —
New function control
Controls the new functions address to the CX23035.
DO: CRCQ
= Switches ON/OFF the function which outputs
the CRCF data to the SUBQ pin from the rising
edge of SCOR to the trailing edge of SOCK. De-
tails are described in ''1-(5). Subcode output'.
(Page 34)
Switches between the old CLV-P servo and the
new CLV-P servo by comparison with newly ad-
ded base counter. Details are described in ''6.
CLV servo control''. (Page 40)
One of the defect countermeasures. Switches
ON/OFF the function which makes the PDO pin
a high impedance (Z) for a maximum of 0.55
ms from the trailing edge of GFS. Details are
described
in
''10.
Countermeasures
to
defects''.
(Page 47)
Switches the zero cross mute function ON/OFF.
Details are described in ''7. Interpolation and
mute, attenuate'.
(Page 45)
D1: NCLV
D2 : HZPD
D3 : ZCMT
Register
A — Sync. protection, attenuator control
DO: ATTM
— Used for attenuating audio signals by 12 dB.
D1: WSEL
_ Provided for switching frame sync. protection
D2 : GSEL
characteristics in correspondence to the time
D3: GSEM __ of playback and time of access. Details will be
described
in the
paragraph
of
''2.
EFM
demodulation'.
(Page 36)
Registers
B and
C — Counter set, more significant 4-bit
(register C) and less significant 4-bit (register B)
These registers are used for setting the tracking counter value.
The data of registers B and C are preset in the counter through
the 4-bit buffer register assigned by address.
Accordingly, when data of either register B or C is input, the
contents of both registers are preset in the counter simultane-
ously as 8-bit data (either buffer register is of ''OLD"' data).
Register D-CLV control
DO : GAIN
Used for setting the gain of MDP pin output in
the CLV-S
and CLV-H
modes.
It is —12 dB
{time of 3/4 out of the period of RFCK/2 is of
high impedance) when DO=0 or is 0 dB when
DO=1.
Used for setting the period of peak hold in the
CLV-S mode. Peak hold is made in the period
of RFCK/4
when
D1=0
or in the period of
RFCK/2 when D1 =1.
Used for determining the period of bottom hold
in the CLV-S and CLV-H modes. Bottom hold
is made in the period of RFCK/32 when D2 =0
or in the period of RFCK/16 when D2=1.,
Used for setting the frequency dividing ratio of
RFCK,
WFCK
in the
CLV-P
mode.
When
D3=0,
phase
comparison
of RFCK/4
and
WFCK/4 is made, and output is made out of
MDP pin in each case.
D1: Te
D2: Ts
D3 : DIV
31
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