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SECTION 7
ECG Signal Control
The output of the ECG digital-to-analog converter, entering at
J1 (pin 24) is fed to inverter US (pin 1). The QRS Polarity
switch, S11, selects the inverted or non-inverted ECG signal.
The signal at this point has a peak amplitude of 3.5 V. The
resistive divider feeding the ECG QRS Amplitude switch, S9,
is arranged so that each 1 kQ of resistance between U5 (pin
12) and ground yields 10 mV of peak signal at US (pin 12).
After buffering by US (pin 14), the signal is fed to two 1000:1
dividers. Thus each 1 mV of signal at US (pin 7)
corresponds to | pV sensed by the maternal/fetal monitor.
The divider consisting of R62, R64, and R72 provides ECG
LA, RA, and RL signals. The signals pass through the ECG
Rate/CMA switch (S8), which connects the ECG signals to
the maternal/fetal monitor when it is in the left (RATE)
position, or the sine wave for the CMR test when it is in the
tight (CMR) position.
Ultrasound and Fetal Movement Detection
The carriers for the ultrasound and fetal movement signals
are generated from the division of two 4 MHz crystal
oscillators (X1 and X2) set to specific offsets from the
ultrasound operating frequency of the maternal/fetal monitor
(200 Hz for the heart rate signal and 25 Hz for the fetal
movement detection signal). These offsets produce detected
signals that fall within the monitor's operational passband for
both of these modes.
The ultrasound heart rate signal is gated on and off by a
comparator (U6) to produce a countable heart rate in the
maternal/fetal monitor. This comparator is triggered by an
analog waveform generated by a digital-to-analog converter
on the Power Supply and CPU Board (No. 7093). This
waveform is a representation of the fetal heart rate signal.
The amplitude variations in this signal are filtered out by an
RC lowpass filter (R37 and C7), and the peak amplitude of
the filtered waveform is limited to 5 V by a zener diode (D4).
Signal Level switch S10 sets the output level (HIGH, MED,
LOW) of the ultrasound signal. This switch controls the
number of NAND gates which are enabled to drive the output
stage. A single gate, U10 (pin 11), drives the output stage in
the low position; two gates, U10 (pins 6 and 8), are used in
the MED position; and four gates, ULO (pins 3, 6, 8, and 11),
are used in the HIGH position. These drive gates connect to a
tapped inductor parallel resonate tuned circuit through 1 КО
resistors (R16-R 19) and a 0.1 pF capacitor (C13). The
resistors connect to the low impedance tap on the tuned
circuit, The more gates active, the more current is applied to
the tuned circuit, and the larger the output at the high
impedance point. This tuned circuit serves as both a
summing node for the gate drivers and a filter to the output,
converting the square wave output from the gates to sine
waves. The signal present at the high impedance tap on the
tuned circuit is divided down in amplitude with a two-stage
attenuation network (R20, R21 and R22, R24). The output of
the network connects to the ultrasound transducer input of the
maternal/fetal monitor.
The fetal movement output is generated in much the same
way as the ultrasound signal. Jt uses the same NAND gate
drive to a tapped tuned circuit; however, when this mode is
activated by switching the US Mode switch (S4) to the
US/FMD position, a single drive gate, U11 (pin 8), is turned
on simultaneously. This is required to provide a background
signal level to the monitor's fetal movement detection
circuitry. Three other drive gates, U11 (pins 3, 6, and 11), are
turned on and off by a control signal generated by decoding
the outputs from the divisions of the fetal movement 4 MHz
oscillator. This produces the simulated fetal movement event.
The control signal turns the remaining drive gates on for
about one second and off for about eight seconds. This
produces a fetal movement detection mark on the monitor's
strip chart paper every eight seconds. The high impedance
output from the fetal movement tuned circuit is attenuated by
a 10 kQQ series resistor (R49) which connects to the second
stage of the ultrasound attenuation network. This serves as
the summing point for the two ultrasound signals.
Pressure Circuitry
The output of the UA digital-to-analog converter at J1 (pin
26) provides 3.125 V (4 V x 200/256) for a reading of 100
mmHg or relative units. This is divided down to 2 mV by
R78 and R84, then fed to the UA+ input of the monitor when
the UA Level/CMR switch (S12) is in the left (LEVEL)
position. When the switch is in the right (CMR) position,
both the UA+ and UA- inputs are connected to 0.1 V which is
derived from the +4 V UA reference voltage.
When the simulator is in the TOCO mode, the TOCO*OUT line
at JI (pin 22) is low. This turns on transistor Ql, grounding
the TOCO* line to the monitor at J4 (pin 4). It also turns off
Q3, bringing its collector to approximately 3.2 V. This allows
R82 to be adjusted to provide a negative offset to the UA
signal. When the simulator is in the IUP mode, the
TOCO*OUT line is high. This turns on O2 allowing the IUP*
line to be pulled up in the monitor. It also turns on O3,
effectively eliminating the negative UA offset. Turning on
O3 also loads the +4 V reference with R87; when the monitor
senses the current drawn by R87, it enters IUP mode. An IUP
enable line is provided for those maternal/fetal monitors
which do not have the current sensing capabilities.
7-4 + Theory of Operation
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