Watchdog Timer; Clock Signals; Digital-To-Analog Converter Output Circuits; Analog Switch Board (No. 14118) - GE 325 Product Manual

Watchdog Timer
Approximately every millisecond, on each pass through the
main software routine, a positive-going pulse is output on the
SOD line of processor U2. This pulse is applied to the trigger
input of watchdog timer U11. As long as pulses occur at least
every 30 ms, the output of this timer connected to the RST IN*
input of the processor, will remain high. If the pulses stop
(i.e, the processor has accessed an invalid memory location),
the timer produces a negative-going pulse to reset the
processor. The timer also makes a similar negative-going
pulse on power-up.
Clock Signals
Processor U2 operates on a 6.144 MHz clock, which is
divided by two and sent to the clock output. This 3.072 MHz
clock signal is fed to the input of the timer on U6, which is
programmed to divide it by 1536, resulting in a 2 kHz pulse
train on the timer output. This signal is fed to the RST7.5
interrupt line on the processor. This interrupt causes the
processor to update the input to the digital-to-analog
converters every 500 ps.
Digital-to-Analog Converter Output Circuits
Reference dicde D3 provides a 5.00 V reference, buffered by
U9 (pin 8), to drive the analog input of both digital-to-analog
converters in U11. One stage of op amp U8 (pins ! and 7)
converts the current outputs of the converters to voltages
ranging from 0 V to -5 V. Another stage of U8 (pins 8 and
14) scales and offsets these voltages to a—S V and +5 V
range. The analog input for digital-to-analog converter U10
is taken from the +4 V output of the monitor under test. One
stage of U9 (pins I and 7) converts the current output of the
converter to voltage and inverts it to a 0 to +4 V range.
LED and Mode Enable
Port C5 of U6 is used both to provide the TOCO OUT* enable
signal and to drive the test LED through buffer transistor O2.
This LED illuminates when the test routine is entered by
shorting TP! to ground. It goes out after a failed test; it
flashes after a successful test until the jumper is removed.
Nand gates in U7 (pins 3 and 6) provide the ECG* enable
signal, which is low when the simulator is either in the FECG
or MECG mode.
SECTION 7
ANALOG SWITCH BOARD (NO. 14118)
Rate and Level Switch Decoding
The ECG Rate switch (S1) shorts one of the nine inputs to UI
to ground or, in the lowest position, leaves all nine inputs
pulled up to +5 V. The four output pins of U1 provide a BCD
code ranging from 0, when the switch is in the lowest
Position, to 9, when it is the highest position. The US Rate
switch (S2) works similarly, except that the code 9 is
produced by U2 when the US Mode switch (S4) is in the
lowest (OFF) position—regardless of the position of 52.
Switch $2 may never be placed in the highest position
because the slot in the panel is not large enough for the slider
to reach this position. The UA Level switch (S5) also works
similarly except that U3 has only three output pins which
produces codes ranging from 0 to 5.
ECG Mode Switching
The ECG Mode switch, S3, may never be placed in the lowest
Position because the slot in the panel is not large enough for
the slider to reach this position. The next position (OFF)
leaves both FECG*IN and MECG*IN lines pulled up to +5 V.
The next two positions (FECG and MECG) ground the
FECG*IN and MECG*IN lines, respectively.
Line Frequency Signal Generator
The output of the secondary windings, entering at J1 (pin 28),
is divided by R53 and R54 to keep it within the common-
mode input range of U4. The first stage of U4 (pin 8) is used
as a comparator with positive feedback for hysteresis. The
output at U4 (pin 8) is a square wave at line frequency with an
amplitude determined by the output saturation voltage of U4,
regardless of changes in line voltage. Potentiometer R57 is
used to adjust the amplitude of the line frequency signal. The
signal is then fed through the remaining three stages of U4,
which are configured as a six-pole, 0.5 dB Chebyshev, low-
pass filter with a cutoff frequency of 67 Hz. The signal at U4
(pin 7) is a line-frequency sine wave with a peak-to-peak
amplitude of 20 V.
Theory of Operation + 7-3