Connection Of Remote I/O; Signal Outputs On Remote I/O - Extech Instruments 7470 Operation Manual

High withstand voltage tester
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8. Connection of Remote I/O

Two 9-pin "D" type connectors are mounted on the rear panel that provide
REMOTE-INPUT-OUTPUT control and information. These connectors mate with
standard 9 pin D-sub-miniature connector provided by the user. The output mates to
a male (plug) connector while the input mates to a female (receptacle) connector. For
best performance, a shielded cable should be used. To avoid ground loops the shield
should not be grounded at both ends of the cable. Suggested AMP part numbers for
interconnecting to the Remote I/O are shown below:
SIGNAL OUTPUT
FAIL
5
9
RESET
OUT

8.1. Signal Outputs on Remote I/O

The rear panel connector provides three output signals to remotely monitor PASS, FAIL,
and PROCESSING conditions. The monitoring signals are provided by three normally
open internal relays that toggle on and off to indicate the condition of the tester. These
are normally open free contacts and will not provide any voltage or current. The
ratings of the contacts are 1 AAC / 125 VAC (0.5 ADC / 30 VDC). The signal outputs
are provided on the 9-pin female D connector. Below is a listing that indicates what
conditions activate each pin. When a terminal becomes active, the relay closes
thereby allowing the external voltage to operate an external device.
Pins 1 and 2 provide the PASS signal.
Pins 3 and 4 provide the FAIL signal.
Pins 5 and 6 provide the PROCESSING signal.
Pins 7 and 8 provide the RESET OUT signal.
The following describes how the relays operate for each test condition:
PROCESSING – The relay contact closes the connection between pin (5) and pin (6)
while the instrument is performing a test. The connection is opened at the end of the
test. The process contact is closed all the way through to the end of the discharge
cycle in DC units.
PASS – The relay contact closes the connection between pin (1) and pin (2) after
Remote Interface Rear Panel:
PASS
1
6
PROCESSING
SIGNAL INPUT
RESET
TEST
INTERLOCK
1
5
6
9
MEMORY 1
MEMORY 2
MEMORY 3
53

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