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2.2.2.1 DLP660TEEVM Test Points
Reference Designator
(*) - These signals are not internally connected in the DMD
2.2.2.2 DLP660TEEVM Connectors
Reference Designator
J4
J500
DLPU126 – DECEMBER 2023
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TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
Note
FMC Connector
Copyright © 2023 Texas Instruments Incorporated
Description
I2C
DLP
®
Display ≥0.47-in Array 4K UHD Evaluation Module
Hardware
Description
DMD_P3P3V
GND
VOFFSET
EN_OFFSET
VRESET
VBIAS
PG_OFFSET
GND
GND
MBRST0*
MBRST1*
MBRST2*
MBRST3*
MBRST4*
MBRST5*
MBRST6*
MBRST7*
MBRST8*
MBRST9*
MBRST10*
MBRST11*
MBRST12*
MBRST13*
MBRST15*
MVRST14*
N/A
N/A
N/A
N/A
GND
GND
DMD_P1P8V
Physical Connection Type
Cable
Cable
11
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