Ina; Input Transfer To Accumulator - Honeywell H112 Instruction Manual

INA
-
Input
Transfer
to
Accumulator
After
address
decoding, the
skip condition
is
gated
in the
sanne
manner
as
in
the
OTA
instruction.
If
the test line
(KTSTL-)
is
grounded,
the
CPU
performs
the
following operations:
it
clears
the
accumulator and
takes
in
data;
issues
the
strobe signal
KSTRB-, and
skips the
next instruction.
If
KTSTL-
is
not
grounded, the
CPU
clears
the
accumulator and goes
to
the next instruction.
Data
is
not
taken
into the
accumulator and
the
strobe signal
is
not
generated.
Figure 2-11 shows
a skip gate
being
implemented with a
decoded address, an INA
signal,
and skip criteria
from
the
ready
flip-flop.
+
6V
+ 6V
KINAL-
ADDRESS
~
DECODE
KTSTL-
READY
FLIP-FLOP
A6248
Figure 2-11.
INA
Gating
Because
the
data
is
transferred
into the
accumulator
before the
strobe pulse occurs,
the data
must
be gated onto
the
data bus
when
the
address decode and
INA+
are
true.
See Figure 2-12.
NOTE
Even
though a data transfer
is
not
to
take place, the
address decode and
INA+
may
be true during transient
conditions.
This causes data
to
gate onto the bus.
The
same
is
also true for the
KTSTL-
test line.
These con-
ditions
do not create a
problem, however, because they
will
not
occur
while the lines
are
stable
during the actual
input time. Generally,
in
machines
that
place
many
spurious pulses
on
the bus,
error-free data transfers
are insured by
gating critical lines.
This
is
performed
by the controller
mainframe.
The
leading or
trailing
edge
of the
strobe
signal,
generated by
the
CPU
and gated with
the
address decode and INA+,
may
be
used
to
reset the
ready
flip-flop.
When
the flip-flop
is
reset, data
may
also be
rennoved
from
the data bus.
It
is
not
necessary
to
remove
data,
however,
until
the device
address or
INA
goes
false.
2-15