Honeywell H112 Instruction Manual page 22

If
the
address decode
indicates
that the least significant half of the W-register has
a
bit
configuration which
is
an instruction
to
be
mechanized
in the interface, the output
is
gated
with the
received
KOCPL-
line
as an assertion
level
and
the
KSTRB-
as
an assertion
level.
Figure 2-7
shows
OCP
gating.
The
output
from
this
gate
is
used
to initiate
the action
assigned
to the
OCP
command.
ADDRESS
+ 6V
DECODE-f
KOCPL-
KSTR8-
A62SI
Figure
2-7.
OCP
Gating
OTA
-
Output Transfer from Accumulator
Implementing
an
OTA
requires
gating
all
the bits
of
the
address bus
together as
in
the
OCP
case.
When
the least significant half of the address bus (W-register) has
a
device
address assigned
to the interface, a +6
volt output
is
produced.
If
the
OTA
is
contingent
upon
a
ready
flip-flop being
set,
the
decoded address
signal
is
gated with
a positive
OTA
signal
and
the skip criteria
(set
side
of the
ready
flip-flop).
If,
however,
the interface
is
always ready
for the
OTA,
the
READY+
term
is
omitted.
Figure 2-8 shows
OTA
gating
with skip
criteria,
-I-6V
KOTAL-
READY FLIP-FLOP
A6252
Figure
2-8.
OTA
Gating with Skip Criteria
2-13