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INTERFACING THE
PROGRAMMED
l/O
BUS
The
following section gives
examples
of the
hardware
which
must
be
added
in the
interface for
each
instruction
used
in the
HI
12
programmed
l/O.
For
discussion purposes,
hardware
which can
be
time-shared
in the
interface
will
be
presented
as
independent
components
When
interfacing
the
programmed
l/O
bus,
three steps
must
precede
actual
hardware
design.
The reconnmended
steps
are
as follows:
a.
Determine
the functional
or
subsystem
design.
b.
Define
the instructions
needed
to
execute
the
above
design.
c.
Develop an
interface
to
the
external device.
Determining
the functional
or
subsystem
design
involves
defining, in
general terms,
how
the
CPU
and external device
will interact.
Points
to
consider
are:
the
paths
for
blocks
of
data;
inherent synchronization pro
biennis
;
and
control
over
the
direction
of
data transfers.
In
defining the instructions, the
designer and
programmer must
agree
on
the following;
which
commands
cause
data transfer;
what
events
cause
interrupts;
what
resets interrupts;
what
conditions
will
cause
OTAs
and
INAs
to
skip or not
skip;
and what
SKS
instructions are
required.
Developing an
interface with the external
device involves
a
consideration
of
its
signals,
voltage
levels, logic levels,
and timing requirements.
After executing these
steps, the actual
design
of
the interface
begins.
To
facilitate
this
task,
an explanation
of the
design
used
to
interface
standard
options
is
helpful.
These
are
the
recommended
naethods.
Other
designs can be
used and
function properly;
however,
care
must
be taken
to
avoid interfering with devices using standard
methods.
All signals
fre:im
the
programmed
l/O bus
to
the interface
and
from
the
interface
to
the
bus
must
go
through
the
recommended
driver and receiver
circuits.
The
design
of
these
circuits
guarantees proper termination and
loading
of the
wires.
Other
circuits
may
cause spurious
signals
and
faulty
timing.
PACs
containing these circuits are available
from
Honeywell
CCD.
Descriptions
of
these
circuits
are presented
in the
appendix.
See
Appendix
B
for allocation of
H112
device
address assignments.
LOGIC DESIGN
TO
COMPLETE
INSTRUCTIONS
OCP
-
Output Control Pulse
Upon
execution
of this
instruction, a
command
pulse
is
to
be delivered
to
the
device
(or
device
function) specified
by
the
address
field.
The
execution
of this
comnnand
is
not
con-
tingent
upon
a
device
ready response and
will
never
skip.
Address
field
00 and
01
are
not
available for
OCP
instructions.
To implement
an
OCP
command,
the
address bus
is
terminated
in line
receivers and
the
outputs
generated
are then
fully
decoded
with
the
equivalent
of
a 6-input gate.
2-12
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