Ramsey Electronics FX-440 Manual page 107

The minimum "N" number is 1. The maximum can be stated in a variety
of ways, some more exact than others. We could just say "64K less 1" or
2 to an n-th power less one. We could say the maximum is what you get
when you install diodes in all 16 positions of the parallel programming
matrix. We could express it as "2 x 32768 - 1" or just say that it is
65,535! '
The details of N divider programming will be covered in the next section.
We' II even see that the roles of the offset matrix and the binary adders
(U7-U10) are clear, brief and simple to explain.
Unlike simpler PLL IC's, U6's phase detector has TWO outputs at pins 7
and 8. These outputs go through very simple low pass filters (R44-C68,
R53-C91) to cut back the 12.5 KHz whine sound of U6 at work. Op amp
US:A sums together the phase detector outputs and the output of US:·A is
passed through a network of 2.2 uf electrolytic capacitors (C67, 70,90,92)
to smooth out the phase detector pulses to clean DC for controlling the
vco.
R48 and C85 form yet another low pass filter to ensure that any 12.5 KHz
"whine" will not get into the VCO. Because the DC charge developed in
C85 (.1 uf) would slow down the PLL during major frequency swings,
such as just going from transmit to receive, D8 and D1 O are set up
back-to-back across voltage dropping R48.
Whenever there is a major frequency shift (which means a significant
YCO control voltage change), one way or the other, one diode or the
other is switched on to short out R48 and discharge C85. This lets the
PLL re-lock instantly; C85 recharges and the diodes become no factor in
the circuit. The "lock detect" output (pin 28) of this Motorola PLL IC is a
fine feature that could be used many different ways in this circuit. We
could have set it up to tell an LED just to alert you that you are "UL"
(unlucky, unlocked??) Instead, we decided to protect your investment in
the transmitter RF section of your transceiver and keep our FCC smiling.
The lock detector gives a strong series of pulses when the PLL is
unlocked. When the PLL is locked, only a tiny sawtooth wave appears at
pin 28. The "lock detect" voltage is watched by US:B. If "unlock" pulses
appear, they are integrated through R90 and C96 as a fairly clean DC
voltage charge built up in C96. If this charge causes USS to swing low,
bias is removed from Transmit Buffer 010. No damage is done, and no
offending signals can be emitted.
We've toured "The Loop.• Now, let's build it and enjoy what it can do!
STAGE G:
PLL SYNTHESIZER CIRCUIT ASSEMBLY
Since our most immediate goal is a functioning, programmable receiver,
it is useful to know that the receiver portion could work fine WITHOUT
the four binary _adder IC's (U7-U10) or the secondary diode programming
FX-440 Assm. 47