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Processor 5/9
5
D
Modify port,9/27 Tim
24
SMB_CLK_N
24
SMB_DATA_N
21
CNVI_W GR_CLK_DP
1.8VA
21
CNVI_W GR_CLK_DN
Modify,12/28 Max
21
CNVI_W GR_D0P
R930
*20K_04
21
CNVI_W GR_D0N
SOC_GPIO192
R929
21
CNVI_W GR_D1P
20K_04
SOC_GPIO193
21
CNVI_W GR_D1N
C
R928
*20K_04
SOC_GPIO194
21
CNVI_W T_CLK_DP
21
CNVI_W T_CLK_DN
R925
75K_04
CNVI_RF_RST#
21
CNVI_W T_D0P
21
CNVI_W T_D0N
21
CNVI_W T_D1P
Add,9/25 Max
21
CNVI_W T_D1N
Add,9/21 Max
FCM1005KF-121T03
L27
1
21
CLKIN_XTAL_LCP
R124
21
XTAL_CLKREQ
R110
21
CNVI_BRI_DT
R118
21
CNVI_BRI_RSP
R109
21
CNVI_RGI_DT
R368
21
CNVI_RGI_RSP
21
CNVI_RF_RST#
GPIO_195
R129 150_1%_04
T4
Add,9/21 Max
Hardware Straps (4)
B
PLACE
CLOSE TO SOC
CLKIN_XTAL_LCP_R
GPIO_79,80,85,86,87,89,192,194,196
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation.
R439
C431
SOC_GPIO79
Internal PD 20K CMOS
10K_04
5p_50V_NPO_04
Internal PD 20K CMOS
SOC_GPIO80
Internal PD 20K CMOS
SOC_GPIO85
Internal PD 20K CMOS
SOC_GPIO86
Internal PD 20K CMOS
SOC_GPIO87
SOC_GPIO89
Internal PD 20K CMOS
Internal PD 20K CMOS
SOC_GPIO192
SOC_GPIO194
Internal PD 20K CMOS
Internal PD 20K CMOS
SOC_GPIO196
GPIO_81,193
Ensure that this strap is pulled HIGH when
RSM_RST_N de-asserts for normal platform operation.
Internal PU 20K CMOS
SOC_GPIO81
A
Internal PU 20K CMOS
SOC_GPIO193
GPIO_62
This pin must be 0 or not externally driven at time
of RSM_RST_N.
Internal PD 20K CMOS
SOC_GPIO62
5
4
3
U26F
U49
SIO_I2C0_SCL
U51
SIO_I2C0_SDA
U46
LPSS_I2C
SIO_I2C1_SCL
U48
SIO_I2C1_SDA
AA39
SIO_I2C2_SCL
AA41
SIO_I2C2_SDA
I2C3_SCL
R44
SIO_I2C3_SCL
I2C3_SDA
R43
SIO_I2C3_SDA
R49
SIO_I2C4_SCL
R51
SIO_I2C4_SDA
C50
SIO_I2C5_SCL
A50
SIO_I2C5_SDA
C48
SIO_I2C6_SCL
C47
SIO_I2C6_SDA
B47
SIO_I2C7_SCL
Modify,9/26 Max
C46
SIO_I2C7_SDA
R389 *1K_04
A26
3.3VA
SMB_ALERT
B27
SMB_CLK
C27
LPSS SMBus
SMB_DATA
R425
0_04
H29
CNV_WGR_CLK_P
R426
0_04
H31
CNV_WGR_CLK
R414
0_04
M31
CNV_WGR_D0_P
R415
0_04
P31
CNV_WGR_D0
D29
R416
0_04
CNV_WGR_D1_P
R412
0_04
F29
CNV_WGR_D1
R443
0_04
F35
CNV_WT_CLK_P
R444
0_04
D35
CNV_WT_CLK
R445
0_04
J35
CNV_WT_D0_P
H35
R446
0_04
CNV_WT_D0
R447
0_04
L31
CNV_WT_D1_P
R448
0_04
J31
CNV_WT_D1
2
CLKIN_XTAL_LCP_R
J29
CLKIN_XTAL_LCP
SOC_GPIO196
0_04
F19
XTAL_CLKREQ
Modify,10/24 Max
33_04
SOC_GPIO191
H17
CNV_BRI_DT
33_04
SOC_GPIO192
J17
CNV_BRI_RSP
SOC_GPIO193
33_04
D19
CNV_RGI_DT
33_04
SOC_GPIO194
D17
CNV_RGI_RSP
F17
CNV_RF_RESET
CNVI_W T_RCOMP
F33
CNV_WT_RCOMP
Add net,7/12 Max
Modify,9/23 Max
Enable TXE ROM Bypass
1=enable bypass
0=disable bypass (default)
Internal PD 20K CMOS
UART0_TXD
Force DNX FW Load
1=Force
0=Do not force (default)
Internal PD 20K CMOS
UART2_TXD
LPC boot BIOS strap
1=boot from LPC
0=do not boot from LPC (default)
Internal PD 20K CMOS
SOC_GPIO66
1.8VA
LPC 1.8V/3.3V mode select
1=buffers set to 1.8V mode
0=buffers set to 3.3V mode (default)
SOC_GPIO83
Internal PD 20K CMOS
R120
10K_04
Allow SPI as a boot source
1=disable
0=enable (default)
Internal PU 20K CMOS
SOC_GPIO84
R137
4.7K_1%_04
eSPI Flash Sharing Mode
1=slave attached flash sharing (SAFS);
0=master attached flash sharing (MAFS;default)
SOC_GPIO191
Internal PD 20K CMOS
Modify,9/23 Max
4
3
2
M39
SIO_SPI_0_CLK
LPSS_SPI
J37
SIO_SPI_0_TXD
L39
SIO_SPI_0_RXD
L37
SIO_SPI_0_FS0
J39
SIO_SPI_0_FS1
M37
SIO_SPI_2_CLK
M33
SIO_SPI_2_TXD
P35
SIO_SPI_2_RXD
P33
SIO_SPI_2_FS0
P37
SIO_SPI_2_FS1
L35
SIO_SPI_2_FS2
N54
SIO_UART0_TXD
P53
SIO_UART0_RXD
N53
SIO_UART0_RTS
M55
SIO_UART0_CTS
L54
SIO_UART2_TXD
M53
SIO_UART2_RXD
K53
SIO_UART2_RTS
L53
SIO_UART2_CTS
LPSS_UART
CNVI
6 OF 13
1.8VA
3.3VA
AMI Debug Use
Modify,7/10 Max
R431
R430
R432
R437
*2.2K_04
*2.2K_04
*10K_04
*10K_04
UART0_TXD
1
6
UART_TXD_Q
R420
*0_04
UART2_TXD
R423
*0_04
*MTDK3S6R
Q32A
UART0_RXD
R418
*0_04
4
3
UART_RXD_Q
UART2_RXD
R424
*0_04
*MTDK3S6R
Q32B
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[06] GKL SOC_5/9_CNVi,LPSS
[06] GKL SOC_5/9_CNVi,LPSS
[06] GKL SOC_5/9_CNVi,LPSS
Size
Size
Size
Document Number
Document Number
Document Number
6-71-N24G0-D02
6-71-N24G0-D02
6-71-N24G0-D02
A3
A3
A3
Date:
Date:
Date:
Monday, January 22, 2018
Monday, January 22, 2018
Monday, January 22, 2018
2
Schematic Diagrams
1
SOC_GPIO79
SOC_GPIO83
SOC_GPIO80
SOC_GPIO81
SOC_GPIO84
SOC_GPIO89
D
SOC_GPIO85
SOC_GPIO86
SOC_GPIO87
UART0_TXD
UART0_RXD
SOC_GPIO62
Modify,7/10 Max
UART2_TXD
UART2_RXD
SOC_GPIO66
Sheet 6 of 40
Processor 5/9
C
B
A
Rev
Rev
Rev
2.0
2.0
2.0
Sheet
Sheet
Sheet
6
6
6
of
of
of
41
41
41
1
Processor 5/9 B - 7
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