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Processor 3/9
5
follow RVP,7/10 Max
R132
56_1%_04
20
CLK_PCIE0_LAN
CARD DREADER(100MHz)
20
CLK_PCIE0_LAN#
21
CLK_PCIE2_MINI
WLAN(100MHz)
21
CLK_PCIE2_MINI#
D
Modify Name,7/31 Max
C333
0.1u_10V_X7R_04
20
PCIE_TXP0_LAN
C332
0.1u_10V_X7R_04
20
PCIE_TXN0_LAN
LAN/CARD
READER
20
PCIE_RXP0_LAN
20
PCIE_RXN0_LAN
Modify Name,7/31 Max
21
PCIE_TXP2_W LAN
21
PCIE_TXN2_W LAN
WLAN
21
PCIE_RXP2_W LAN
21
PCIE_RXN2_W LAN
R144
*10K_04
25
LAN_CLKREQ#_R
Modify,9/20 Max
25
W LAN_CLKREQ#_R
C
R145
*10K_04
25
PCIE_W AKE0#_R
25
PCIE_W AKE2#_R
Modify,9/27 Tim
18
SATATXP0
18
SATATXN0
SATA HDD
18
SATARXP0
18
SATARXN0
CLKREQ0#
LAN
1.8VA
Modify,9/20 Max
CLKREQ1#
WLAN
R127 10K_04
PCIECLKRQ1#
R128 10K_04
PCIECLKRQ3#
B
A
5
4
3
U26D
PCIECLK_RCOMP
L10
PCIE_REF_CLK_RCOMP
R12
PCIE_CLKOUT0P
R10
SATA/USB3
PCIE_CLKOUT0N
N7
PCIE_CLKOUT1P
N5
PCIE_CLKOUT1N
PCIe
R7
PCIE_CLKOUT2P
R5
PCIE_CLKOUT2N
N8
PCIE_CLKOUT3P
N10
PCIE_CLKOUT3N
USB3
PCIE_TXP0_C
E2
PCIE_P0_TXP
PCIE_TXN0_C
F2
PCIE_P0_TXN
G7
PCIE_P0_RXP
H6
PCIE_P0_RXN
A7
PCIE_P1_TXP
PCIe/USB3
C7
PCIE_P1_TXN
D4
PCIE_P1_RXP
E5
PCIE_P1_RXN
C9
PCIE_P2_TXP
B9
PCIE_P2_TXN
E7
PCIE_P2_RXP
F6
PCIE_P2_RXN
LAN_CLKREQ#_R
A46
PCIE_CLKREQ0
PCIECLKRQ1#
C45
PCIE_CLKREQ1
W LAN_CLKREQ#_R
B45
PCIE_CLKREQ2
PCIECLKRQ3#
C44
PCIE_CLKREQ3
F47
PCIE_WAKE0
D47
PCIE_WAKE1
F45
PCIE_WAKE2
D50
PCIE_WAKE3
SSIC
SATA
J3
SATA_P0_TXP
J2
SATA_P0_TXN
J7
SATA_P0_RXP
J5
SATA_P0_RXN
USB2
4 OF 13
Hardware Straps (2)
Top swap override
1=Enable
0=Disable (default)
Internal PD 20K CMOS
GPIO_44
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation.
Internal PD 20K CMOS
4
3
2
H1
SATA_P1_USB3_P5_TXP
SATA_TXP1 21
H2
SATA_TXN1 21
SATA_P1_USB3_P5_TXN
(3G+mSATA)(B KEY)
H4
SATA_RXP1 21
SATA_P1_USB3_P5_RXP
G5
SATA_P1_USB3_P5_RXN
SATA_RXN1 21
B15
USB3_TX0_P 23
USB3_P0_TXP
C15
M/B
USB
USB3_P0_TXN
USB3_TX0_N 23
port0(2.0+3.0)
F15
USB3_RX0_P 23
USB3_P0_RXP
TYPE-C
D15
USB3_RX0_N 23
USB3_P0_RXN
C14
USB3_P1_TXP
USB3_TX1_P 19
A14
M/B
USB
USB3_TX1_N 19
USB3_P1_TXN
port1(2.0+3.0)
J11
USB3_RX1_P 19
USB3_P1_RXP
TYPE-A
H11
USB3_P1_RXN
USB3_RX1_N 19
C10
PCIE_P3_USB3_P4_TXP
A10
PCIE_P3_USB3_P4_TXN
H9
PCIE_P3_USB3_P4_RXP
F9
PCIE_P3_USB3_P4_RXN
C11
USB3_TX3_P 21
PCIE_P4_USB3_P3_TXP
B11
PCIE_P4_USB3_P3_TXN
USB3_TX3_N 21
3G / LTE
D11
USB3_RX3_P 21
PCIE_P4_USB3_P3_RXP
F11
USB3_RX3_N 21
PCIE_P4_USB3_P3_RXN
Add,7/14 Max
B13
PCIE_P5_USB3_P2_TXP
USB3_TX2_P 23
C13
M/B
USB
USB3_TX2_N 23
PCIE_P5_USB3_P2_TXN
port0(2.0+3.0)
F13
USB3_RX2_P 23
PCIE_P5_USB3_P2_RXP
TYPE-C
D13
PCIE_P5_USB3_P2_RXN
USB3_RX2_N 23
PCIE_USB3_OBS0
C5
R369
100_1%_04
PCIE2_USB3_SATA3_RCOMP
C6
PCIE_USB3_OBS1
PCIE2_USB3_SATA3_RCOMP_P
AA10
NC1
AA8
NC2
W13
NC5
W12
NC4
U15
NC3
U7
M/B USB port0(2.0+3.0)
USB_PP0 23
USB2_DP0
U5
USB_PN0
23
TYPE-C
USB2_DN0
N2
M/B USB port1(2.0+3.0)
USB2_DP1
USB_PP1 19
N3
USB_PN1
19
TYPE-A
USB2_DN1
L2
USB_PP2 20
USB2_DP2
L3
U/B USB port2 (2.0)
USB2_DN2
USB_PN2
20
R13
USB_PP3 21
USB2_DP3
R15
M/B 3G/LTE port3
USB_PN3
21
USB2_DN3
M1
USB2_DP4
USB_PP4 20
M3
U/B USB port4 (2.0)
USB_PN4
20
USB2_DN4
R2
USB2_DP5
R3
USB2_DN5
P1
USB_PP6 20
USB2_DP6
P3
CCD port 6
USB_PN6
20
USB2_DN6
U8
USB2_DP7
USB_PP7 21
U10
BT port 7
USB_PN7
21
USB2_DN7
U12
USB_RCOMP
R139
113_1%_04
USB2_RCOMP
V1
USB_OTG_ID
USB2_DUALROLE
USB_VBUSSNS
V3
R133
*20mil_short_04
USB2_VBUS_SNS
U54
USB_OC#0
USB2_OC0
U53
USB_OC#01
USB2_OC1
USB_OC#01
Modify,9/23 Max
USB_OC#0
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[04] GKL SOC_3/9_PCIE,SATA,USB
[04] GKL SOC_3/9_PCIE,SATA,USB
[04] GKL SOC_3/9_PCIE,SATA,USB
Size
Size
Size
Document Number
Document Number
Document Number
6-71-N24G0-D02
6-71-N24G0-D02
6-71-N24G0-D02
A3
A3
A3
Date:
Date:
Date:
Monday, January 22, 2018
Monday, January 22, 2018
Monday, January 22, 2018
2
Schematic Diagrams
1
D
Sheet 4 of 40
C
Processor 3/9
B
When the platform does not use the
USB2_OTG_ID and USB2_VBUS_SNS pins,
USB2_OTG_ID pin should be unconnected on
the platform (terminated with internal
pull ups] and USB2_VBUS_SNS should be
connected to ground.
A
Rev
Rev
Rev
2.0
2.0
2.0
Sheet
Sheet
Sheet
4
4
4
of
of
of
41
41
41
1
Processor 3/9 B - 5
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