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QB-RL78G1C In-Circuit Emulator
- PLL clock
If there is mismatch on the High-speed system clock frequency (f
(DSCCTL) setting, QB-RL78G1C generates 1MHz as PLL oscillation frequency (f
Refer to the device user's manual regarding a High-speed system clock frequency for USB clock and register
setting of PLL.
- D+/D- pull-up operation when using USB function module
D+/D- pull-up operation on QB-RL78G1C differs from the target device.
Target device:
- D+ pull-up is enabled when bit 4 of the system configuration control register is "1" (DPRPU = "1")
- D- pull-up is enabled when bit 3 of the system configuration control register is "1" (DMRPU = "1")
QB-RL78G1C:
Either bit 4 (DPRPU) or bit 3 (DMRPU) of the system configuration control register is made "1", D- or
D+ is pulled up as follows.
- D+ pull-up is enabled when using the full-speed operation.
- D- pull-up is enabled when using the low-speed operation.
- Operating voltage of USB battery charging detection
Operation voltage of USB battery charging detection on QB-RL78G1C differs from the target device.
Target device:
Operation voltage is proportional to UVBUS voltage levels because it is generated by the supply
voltage of UVBUS pin.
QB-RL78G1C:
Operation voltage is 5V because it is generated by QB-RL78G1C internal power supply (5V).
- UVDD pin voltage levels when supplying power from the internal power supply for the USB to
USB function module
UVDD pin voltage level on QB-RL78G1C differs from the target device when supplying power from the internal
power supply for USB to the USB function module.
. Target device : 3.3V (TYP)
QB-RL78G1C : 0V
R20UT2079EJ0100 Rev.1.00
2013.07.12
CHAPTER 4 CAUTIONS
) setting and the PLL operation register
MX
).
PLL
Page 40 of 45
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