Renesas QB-RL78G1C User Manual page 22

QB-RL78G1C In-Circuit Emulator
(2) High-speed system clock when using PLL
The clock settings are listed below.
QB-RL78G1C generates 48MHz clock as PLL oscillation frequency (f
reference clock divider setting and the DSCM bit used as PLL multiplication setting. If a setting other than the
below table is set on debugger, QB-RL78G1C generates 1MHz clock as PLL oscillation frequency (f
High-Speed
System Clock
Frequency
16MHz (a) When the clock generated within the emulator is used
12MHz (a) When the clock generated within the emulator is used
8MHz (a) When the clock generated within the emulator is used
(b) When the clock (a square wave) is supplied from the target system
(c) When the oscillator (OSC1) mounted onto the emulator is used
6MHz (a) When the clock generated within the emulator is used
(b) When the clock (a square wave) is supplied from the target systemNote
(c) When the oscillator (OSC1) mounted onto the emulator is used
Note This setting is not possible when TARGET LED is not lit.
Remarks 1. Settings other than the above are prohibited.
2. Selection of (a) or (b) is possible regardless of whether the oscillator is not mounted in the
OSC1socket.
(a) When the clock generated within the emulator is used
This method uses the clock generated by the emulator.
The oscillation frequency used must be set in the debugger.
Select the 8MHz in the debugger when using 16MHz or 8MHz as High-speed system clock.
Select the 6MHz in the debugger when using 12MHz or 6MHz as High-speed system clock.
Refer to the user's manual of the debugger used for setting method of the oscillation frequency.
(b) When the clock (a square wave) is supplied from the target system
The clock input from the target system is then used.
To input a clock from the target system, input to the clock pin (X2) the square-wave signal with the same
voltage potential as that of the target device supply voltage (VDD). Inputting the inverted signal to X1 is not
necessary.
The selectable frequencies are same as those of the target device.
For debugger settings, check the user's manual for the debugger that will be used. Oscillation by a resonator
in the target system is not supported.
R20UT2079EJ0100 Rev.1.00
2013.07.12
Table 2-3. Settings for High-Speed System Clock when using PLL
Type of Clock to Be Used
CHAPTER 2 SETUP PROCEDURE
) by setting the DSFRDIV bit used as PLL
PLL
OSC1
–
–
–
Note
–
Oscillator
mounted
–
–
Oscillator
mounted
Page 22 of 45
).
PLL
Clock frequency
setting of
debugger
8MHz
6MHz
8MHz
–
6MHz
–
–