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User's Guide
TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1
PMIC User Guide for J721S2, PDN-0A
This user's guide can be used as a guide for integrating the TPS6594-Q1 and LP8764-Q1 power management
integrated circuits (PMICs) into a system powering the Automotive Jacinto 7 J721S2, TDA4VE, TDA4VL or
TDA4AL processor.
1
Introduction.............................................................................................................................................................................2
2 Device Versions......................................................................................................................................................................
Connections..........................................................................................................................................................4
3.1 Power Mapping..................................................................................................................................................................
Mapping.................................................................................................................................................................7
4 Supporting Functional Safety Systems..............................................................................................................................
Settings..............................................................................................................................................................14
5.2 Device Identification Settings...........................................................................................................................................
5.3 BUCK Settings.................................................................................................................................................................
Settings....................................................................................................................................................................19
5.5 VCCA Settings.................................................................................................................................................................
5.6 GPIO Settings..................................................................................................................................................................
5.7 Finite State Machine (FSM) Settings...............................................................................................................................
Settings..............................................................................................................................................................23
Settings...................................................................................................................................................28
5.10 Miscellaneous Settings..................................................................................................................................................
Settings............................................................................................................................................................30
5.12 Multi-Device Settings.....................................................................................................................................................
5.13 Watchdog Settings.........................................................................................................................................................
6 Pre-Configurable Finite State Machine (PFSM) Settings..................................................................................................
6.1 Configured States............................................................................................................................................................
6.2 PFSM Triggers.................................................................................................................................................................
6.3 Power Sequences............................................................................................................................................................
7 Application Examples..........................................................................................................................................................
Standby...........................................................................................................................................51
7.3 Entering and Exiting LP_STANDBY.................................................................................................................................
7.4 Runtime Customization....................................................................................................................................................
8 References............................................................................................................................................................................
Trademarks
Jacinto
™
is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
SLVUCJ9 - FEBRUARY 2023
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ABSTRACT
Table of Contents
Requirements.........................................................................................................................12
Requirements................................................................................................................12
Settings........................................................................................................................14
RETENTION........................................................................................................50
TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
Copyright © 2023 Texas Instruments Incorporated
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for J721S2, PDN-0A
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Related Manuals for Texas Instruments TPS65941120-Q1
Summary of Contents for Texas Instruments TPS65941120-Q1
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Page 1: Table Of Contents
Jacinto ™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... -
Page 2: Introduction
The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1. TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback... - Page 3 TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
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Page 4: Processor Connections
3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused feedback pin, FB_B3, of the TPS65941120-Q1 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_MCUIO_3V3_LS power rail. - Page 5 * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V. • ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 6 SE_1V8 'R' is required and 'O' is optional. LDO1 and LDO2 of the TPS65941120-Q1 and LDO1 and LDO2 of the TPS65941421-Q1 remain on when TRIGGER_I2C_7, in FSM_I2C_TRIGGERS register, is set. BUCK4 of the TPS65941421-Q1 and the TLV73318P-Q1 which is controlled by the TPS65941421-Q1 GPIO3 remain active while TRIGGER_I2C_5, in FSM_I2C_TRIGGERS, is set.
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Page 7: Control Mapping
MCU Safety Island' and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... - Page 8 1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023...
- Page 9 For details on how functional safety related connections help achieve functional safety system-level goals, see Section SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 10 SCLK_SP GPIO_5 PMICB_SCLK SDATA_S GPIO_6 PMICB_SDATA GPIO_7 Unused GPIO_8 Unused GPIO_9 EN_EFUSE_LDO GPIO_10 WKUP2 WK_MCU_ONLYn GPIO_11 EN_3V3IO TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
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Page 11: Supporting Functional Safety Systems
ASIL-D rating. See the Safety Manual for Jacinto ™ 7 Processors for a complete list of functional safety system assumptions. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... -
Page 12: Achieving Asil-B System Requirements
C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65941120-Q1, FB_B3, is assigned to monitor the MCU IO supply voltage, VDD_MCUIO_3V3. For monitoring other supplies, the unused feedback pins of the LP876411B5- Q1 (FB_B3 or FB_B4) are assigned to monitor the DDR supply voltage, VDD1_DDR_1V8 and the SoC IO supply voltage, VDD_IO_3V3. - Page 13 PMIC-A - OV & PMIC-A -CM PMIC-A -RVM LDO4 VDA_MCU_1V8 PMIC-A - OV & PMIC-A -CM PMIC-A -RVM SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
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Page 14: Static Nvm Settings
None TLV73318P-Q1 LDO-D VDD_EFUSE_1V8 None Rail Group settings for the TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 are found in Table 5-7. Power rails VDDSHV5, VPP_CORE, VPP_MCU, VDDA_3P3_USB, and VDD1_LPDDR4_1V8 are not safety critical. Power rails VDD_IO_1V8/3V3 are typically not safety critical since other means are available (for example, black-channel checkers) to provide diagnostic coverage to detect faults in SoC signaling interfaces (for example, CAN, UART, and SPI). - Page 15 470 nH BUCK3 2.2MHz Single-Phase and Multi-Phase Configuration 470 nH BUCK4 2.2MHz Single-Phase and Multi-Phase Configuration 470 nH SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
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Page 16: Device Identification Settings
BUCKx_EN is set for the BUCK1 in the LP876411B5-Q1. The BUCKx_VMON_EN bit is set for BUCK1, BUCK3 and BUCK5 in the TPS65941120-Q1. The BUCKx_VMON_EN bit is set for BUCK1, BUCK3, BUCK4 and BUCK5 in the TPS65941421-Q1. The BUCKx_VMON_EN bit is set for BUCK1, BUCK3 and BUCK4 in the LP876411B5-Q1. - Page 17 0.800 V 0x73 1.10 V 0x37 0.800 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V 0xb2 1.80 V 0.3 V SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 18 +5% / +50 mV +5% / +50 mV BUCK5_UV_THR 0x3 -5% / -50 mV -5% / -50 mV TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
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Page 19: Ldo Settings
+5% / +50 mV +5% / +50 mV LDO3_UV_THR -5% / -50 mV -5% / -50 mV SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... -
Page 20: Vcca Settings
GPIO2_DEGLITC No deglitch, only 8 us deglitch time. 8 us deglitch time. H_EN synchronization. TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... - Page 21 GPIO7_DEGLITC 8 us deglitch time. 8 us deglitch time. 8 us deglitch time. H_EN SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 22 NPWRON. NPWRON. ENABLE_POL Active high Active high Active high NRSTOUT_OD Open-drain output Open-drain output TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
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Page 23: Finite State Machine (Fsm) Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed though I C after startup. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... - Page 24 Masked GPIO11_FSM_M Low; Masking sets Low; Masking sets ASK_POL signal value to '0' signal value to '0' TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 25 Interrupt not Interrupt not generated. generated. generated. VCCA_UV_MAS Interrupt not Interrupt not Interrupt not generated. generated. generated. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 26 Interrupt not Interrupt not Interrupt not generated. generated. generated. SOFT_REBOOT_ Interrupt generated Interrupt generated Interrupt generated MASK TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 27 Interrupt not Interrupt not _MASK generated. generated. ESM_MCU_FAIL Interrupt generated Interrupt not Interrupt not _MASK generated. generated. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
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Page 28: Powergood Settings
Field Name Value Description Value Description Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz 1.1 MHz 1.1 MHz TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... - Page 29 FSM_STEP_SIZ PFSM_DELAY_S 102.4μs (typ) 102.4μs (typ) 102.4μs (typ) LDO_RV_TIMEO LDO1_RV_TIME 16ms 16ms UT_ REG_1 LDO2_RV_TIME 16ms 16ms SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
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Page 30: Interface Settings
CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 0x4c 0x4C 0x58 0x58 I2C2_ID_REG I2C2_ID 0x12 0x12 0x13 0x13 0x14 0x14 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 31: Multi-Device Settings
This section describes the default PFSM settings of the TPS6594-Q1 devices. These settings cannot be changed after device startup. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... -
Page 32: Configured States
The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6594-Q1 and LP8764-Q1 data sheets, see Section TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright ©... - Page 33 When the PMICs transition from the FSM to the PFSM, several initialization instructions are performed to disable the residual voltage checks on both the BUCK and LDO regulators. Additionally, the FIRST_STARTUP_DONE SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A...
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Page 34: Pfsm Triggers
PWR_SOC_ERR Error I2C_1 bit is No State Execute RUNTIME False True ACTIVE, MCU ONLY high Change BIST TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... - Page 35 Refer to the data sheet for more details. If the LP_STANDBY_SEL bit is set in the TPS65941120-Q1 (see RTC_CTRL_2, in Table 5-10), then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY.
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Page 36: Power Sequences
EN_MCU3V3_VIO (Leo B) LP876411B5-Q1 BUCK1234 0 us VDD_DDR_1V1 (Hera C) Figure 6-2. TO_SAFE_SEVERE and TO_SAFE Power Sequences TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... - Page 37 Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and FORCE_EN_DRV_LOW in the TPS65941120 while only the SPMI_LP_EN is set in the TPS65941421 and LP876411B5. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 38 // Reset all BUCK regulators REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0 //LP876411B5 //Reset all BUCK regulators REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x0F MASK=0xF0 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 39 At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 40 The regulator transitions do not represent enabling of the regulators but the time at which the voltages are restored to their default values. Since this sequence originates from the ACTIVE state all of the regulators are on. TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright ©...
- Page 41 TPS65941421-Q1 GPIO11 3500 us EN_3V3_VIO (Leo B) Figure 6-6. PWR_SOC_ERROR with I2C Triggers High in both PMICs SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 42 NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023...
- Page 43 REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3 // Clear SPMI_LP_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF // LP876411B5 // Set CLKMON_EN // Clear LPM_EN SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 44 TPS65941120-Q1 nRSTOUT 16200 us H_MCU_PORz (Leo A) Figure 6-9. TO_MCU with I2C Triggers high in both PMICs TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 45 REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE Note After the TO_MCU sequence the MCU is responsible for managing the EN_DRV. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 46 H_SOC_PORz (Leo A) Figure 6-11. TO_ACTIVE Sequence At the end of the TO_ACTIVE sequence the 'FORCE_EN_DRV_LOW' bit is cleared. TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 47 // Set SPMI_LP_EN and FORCE_EN_DRV_LOW REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7 // TPS65941421 LP876411B5 // Set SPMI_LP_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated...
- Page 48 GPIO9 3500 us EN_MCU3V3_VIO (Leo A) Figure 6-12. TO_RETENTION when I2C triggers are low in both PMICs TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
- Page 49 The TPS65941120 device also performs an additional 16 ms delay based upon the contents of the register (PFSM_DELAY_REG_2) to ensure that the TPS65941120 sequence finishes last. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A...
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Page 50: Application Examples
// Set NSLEEP1 and NSLEEP2 in TPS65951213 Write 0x48:0x66:0x01:0xFE // Clear BIST_PASS_INT Write 0x48:0x65:0x26:0xD9 // Clear all potential sources of the On Request TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated... -
Page 51: Entering And Exiting Standby
// set I2C_0 trigger, trigger TO_STANDBY sequence After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A Copyright © 2023 Texas Instruments Incorporated... -
Page 52: Entering And Exiting Lp_Standby
In this example BUCK4 is used to monitor a 0.8V supply. The wait statement ensures that the built in self-test of the monitors is completed before the OV and UV monitors are unmasked. Refer to the TPS6594-Q1Power TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide SLVUCJ9 – FEBRUARY 2023 for J721S2, PDN-0A Submit Document Feedback Copyright ©... - Page 53 NVM settings. For both the GPIO and BUCK monitor customizations, these customizations are not preserved and must be re-applied with every power cycle and transition through the hardware states. SLVUCJ9 – FEBRUARY 2023 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide Submit Document Feedback for J721S2, PDN-0A...
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Page 54: References
• Texas Instruments, Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for J721E, PDN-0C (Rev. A) • Texas Instruments, TPS6594-Q1 Safety Manual (request through mySecure) • Texas Instruments, LP8764-Q1 Safety Manual (request through mySecure) • Texas Instruments, TPS6594-Q1 Schematic PCB Checklist application note •... - Page 55 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
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