Linear Technology DC1763A Demo Manual page 3

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Notes:
1. The DC1371 does not support 1- or 4-lane operation.
2. Optional jumper should be left open to ensure proper
serial configuration.
3. In the first revision of this demo board the jumpers
were mislabeled. For boards labeled with a Rev 1 use
the following jumper positions:
a. JP8: Term: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default: 3.5mA)
b. JP14/JP5: ILVDS/LANE: Two bits that select between
one, two and four lanes.
JP14 – ILVDS
3.5mA
3.5mA
1.75mA
1.75mA
Applying Power and Signals to the DC1763A
Demonstration Circuit
If a DC1371 is used to acquire data from the DC1763A, the
DC1371 must FIRST be connected to a powered USB port
and have 5V applied BEFORE applying 3.0V to 6V across
the pins marked V
requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1763A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1763A should not be removed, or connected to
the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2195 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
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JP5 LANE NUMBER OF LANES
2
1
2
1 Not Used
+
and GND on the DC1763A. DC1763A
DEMO MANUAL DC1763A
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a gallium arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
2
Apply the analog input signal of interest to the SMA con-
1
nectors on the DC1763A demonstration circuit board
4
marked J3 AIN1 and J4 AIN2. These inputs correspond
with channels one and two of the ADC respectively. These
inputs are capacitively coupled to balun transformers
ETC1-1-13 (lead free part number MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1763A demonstration circuit board marked J12
+
CLK . As a default the DC1763A is populated to have a
single-ended input.
For the best noise performance, the encode clock must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2195. Using band pass filters on the clock and
the analog input will improve the noise performance by
reducing the wideband noise power of the signals. In
the case of the DC1763A a band pass filter used for the
clock should be used prior to the DC1075. Data sheet FFT
plots are taken with 10-pole LC filters made by TTE (Los
Angeles, CA) to suppress signal generator harmonics,
non-harmonically related spurs and broadband noise.
Low phase noise Agilent 8644B generators are used for
both the clock input and the analog input.
or 13dBm. When
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