DESCRIPTION
Demonstration circuit 1760A supports a family of 14-
/12-bit 25Msps to 150Msps ADCs and an LTC
noise amplifier. Each assembly features a device from the
LTC2261-14 family of high dynamic range 1.8V ADCs and
a LTC6409 low noise amplifier.
Demonstration circuit 1760A supports the LTC2261-14
family full rate CMOS and DDR CMOS output mode. The
PERFORMANCE SUMMARY
PARAMETER
Supply Voltage—ADC
Supply Voltage—Amplifier
Analog Input Range
Logic Input Voltages
Logic Output Voltages (OV
= 1.8V)
DD
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
Convert Clock Level
Resolution
Input Frequency Range
SFDR
SNR
DEMO MANUAL DC1760A
12-/14-Bit, 25Msps to 150Msps
circuitry on the analog inputs is optimized for analog input
®
6409 low
frequencies from DC to 100MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
(T
= 25°C)
A
CONDITION
Depending on Sampling Rate and the A/D
Converter Provided, This Supply Must Provide Up
to 150mA
Depending on Supply Voltage Used, This Supply
Must Provide Up to 25mA
Depending On Sense Pin Voltage
Minimum Logic High
Maximum Logic Low
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
Depending on ADC This Can Vary Between
20Msps and 125Msps
Single-Ended Encode Mode (ENC
–
Differential Encode Mode (ENC
Not Tied to GND) 0.2V to 3.6V
14 Bits
DC-100MHz
See Applicable Data Sheet
See Applicable Data Sheet
LTC2261-14 and LTC6409
ADC Combo Board
VALUE
Optimized for 3.3V [3.0V ⇔ 3.5V Min/Max]
Optimized for 3.0V [2.7V ⇔ 5.0V Min/Max]
1V
to 2V
P-P
P-P
1.3V
0.6V
1.750V (1.790V Typical)
0.050V (0.010V Typical)
LTC2261-14 = 125Msps
–
Tied To Gnd)
0V to 3.6V
dc1760af
1
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