3.3.
SRC capacity
Any combination of inputs and/or outputs can be assigned to either clock domain,
and channels routed between different clock domains are routed through the SRC
until its the maximum capacity is reached. The available SRC channels will be split
between directions A>B and B>A according to the following table:
Automatically optimized for A>B and B>A (in blocks of 16 channels) until 128
channels total are reached, when both sides run at x1 (44.1 / 48 kHz)
Up to 64x64 when either side is running at x2 speed (88.2 / 96 kHz)
Up to 32x32 when either side is running at x4 speed (176.4 / 192 kHz)
Channels routed within the same clock domain (A>A or B>B) are not routed
through the SRC and therefore require no SRC channel capacity.
Channels routed between different clock domains (A>B or B>A) which have
multiple destinations occupy only one channel on the SRC.
1 Requires SRC-64 firmware 2.0 and MVR-64 firmware 5.0. On older, the config is fixed 64x64ch
SRC-64
1
13
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