Nuvoton ISD91500 Technical Reference Manual

Multi-algorithm voice processor with headphone driver

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ISD91500 Technical Reference Manual

ISD91500

Technical Reference Manual

Multi-Algorithm Voice Processor

With Headphone Driver

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of ISD91500 series microcontroller

based system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Feb. 21, 2023

Page 1 of 500

Rev 2.3

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Summary of Contents for Nuvoton ISD91500

Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of ISD91500 series microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2: Table Of Contents
ISD91500 Technical Reference Manual Table of Contents GENERAL DESCRIPTION ................11 FEATURES ..................... 11 PART INFORMATION AND PIN CONFIGURATION ........15 LQFP 64-Pin Diagram ..................15 3.1.1 I91535ADI ......................15 3.1.2 I91535H02DI ....................16 QFN 48-Pin Diagram ..................17 3.2.1 I91535AQI .......................
Page 3 ISD91500 Technical Reference Manual 5.5.4 Functional Description ................... 174 5.5.5 Register Map ....................176 5.5.6 Register Description ..................178 PWM Generator and Capture Timer (PWM) ..........186 5.6.1 Overview ......................186 5.6.2 Features ......................186 5.6.3 Block Diagram ....................187 5.6.4...
Page 4 ISD91500 Technical Reference Manual 5.11.3 Functional Description ................... 280 5.11.4 Register Map ....................294 5.11.5 Register Description ..................295 5.12 12-bit Analog-to-Digital Converter (SARADC) ..........303 5.12.1 Overview ......................303 5.12.2 Features ......................303 5.12.3 Block Diagram ....................303 5.12.4 Functional Description ................... 305 5.12.5 Register Map ....................
Page 5 ISD91500 Technical Reference Manual 5.16.6 Register Map ....................393 5.16.7 Register Description ..................396 5.17 Companding (CPD) ..................423 5.17.1 Overview ......................423 5.17.2 Features ......................423 5.17.3 Functional Description ................... 423 5.17.4 Register Map ....................425 5.17.5 Register Description ..................426 5.18...
Page 6 ISD91500 Technical Reference Manual List of Tables Table 3.4-1 Alternate function table of GPIO ................. 31 Table 5.2-1 Address Space Assignments for On-Chip Modules ........... 36 Table 5.2-2 Exception Model ......................89 Table 5.2-3 System Interrupt Map ....................90 Table 5.2-4 Vector Table Format ....................91 Table 5.3-1 The symbol definition of PLL Output Frequency formula .........
Page 7 ISD91500 Technical Reference Manual List of Figures Figure 3.1-1 I91535ADI Pin Diagram ..................... 15 Figure 3.1-2 LQFP64 Type2 Pin Diagram ..................16 Figure 3.2-1 QFN48 Type1 Pin Diagram ..................17 Figure 3.2-2 QFN48 Type2 Pin Diagram ..................18 Figure 4-1 Functional Block Diagram 1 ..................33 Figure 4-2 Functional Block Diagram 2 ..................
Page 8 ISD91500 Technical Reference Manual Figure 5.7-15 SPI Timing in Slave Mode ..................220 Figure 5.7-16 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ........221 Figure 5.8-1 I2S Block Diagram ....................241 Figure 5.8-2 I S Clock Control Diagram ..................242 Figure 5.8-3 Master mode Interface Block Diagram ..............
Page 9 ISD91500 Technical Reference Manual Figure 5.11-13 GC Mode ......................290 Figure 5.11-14 I2C Data Shift Direction ..................292 Figure 5.11-15 I2C Time-out Count Block Diagram ..............293 Figure 5.12-1 ADC Controller Block Diagram ................304 Figure 5.12-2 SARADC Clock Source ..................306 Figure 5.12-3 Continuous Scan on Selected Channels ...............
Page 10 ISD91500 Technical Reference Manual Figure 5.19-3 SDADC Sample Rate Diagram ................461 Figure 5.19-4 Audio SDADC FIFO Contents ................464 Figure 5.19-5 SDADC controller interrupt ..................466 Figure 5.20-1 VMIDH/L Reference Generation ................484 Figure 5.20-2 MICBIAS Block Diagram ..................485 Figure 5.20-3 MICBIAS Application Diagram ................
Page 11: General Description
GPIO, SDADC, SARADC, DAC and Low Voltage Detector. ISD91500 series supports a rich set of power saving modes including Deep Power Down (DPD) mode drawing less than 2uA. A micro-power 10KHz oscillator enables the device to periodically wake up from deep power down to check other events.
Page 12 ISD91500 Technical Reference Manual – Clock Doubler(XCLK) minimum input frequency 512KHz – Clock failure detection for high speed external crystal oscillator  GPIO – Up to 50 GPIOs individually configurable as three I/O modes Input with pull-up option  Push-Pull output ...
Page 13 ISD91500 Technical Reference Manual  – Up to two I2C controllers – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus –...
Page 14 ISD91500 Technical Reference Manual – I2S protocols: Philips standard, MSB-justified, and LSB-justified data format – PCM protocols: PCM standard, MSB-justified, and LSB-justified data format – Interrupt requests generated when buffer levels cross a programmable boundary – Support two 16-level FIFO data buffers, one for transmitting and the other for receiving –...
Page 15: Part Information And Pin Configuration
ISD91500 Technical Reference Manual PART INFORMATION AND PIN CONFIGURATION LQFP 64-Pin Diagram 3.1.1 I91535ADI PA.6 nRESET PA.5 PC.2 PA.4 PC.3 PA.3 PC.4 PA.2 PC.5 PA.1 PC.6 PA.0 PC.7 MICBIAS PC.8 I91535ADI VMIDH PC.9 MICN PC.10 MICP PC.11 VMIDL PC.1 VCCA PC.0...
Page 16: I91535H02Di
ISD91500 Technical Reference Manual 3.1.2 I91535H02DI PA.6 USB_VBUS PA.5 nRESET PA.4 PC.2 PA.3 PC.3 PC.4 PA.2 PA.1 PC.5 PA.0 PC.6 MICBIAS PC.7 I91535H02DI VMIDH PC.9 MICN PC.10 MICP PC.11 VMIDL PC.1 VCCA PC.0 HPOR PC.12 HPOL PC.13 VSSA PC.14 Figure 3.1-2 LQFP64 Type2 Pin Diagram Feb.
Page 17: Qfn 48-Pin Diagram
ISD91500 Technical Reference Manual QFN 48-Pin Diagram 3.2.1 I91535AQI PA.4 USB_CAP PA.3 USB_D+ Top transparent view PA.2 USB_D- PA.1 USB_VBUS PA.0 nRESET MICBIAS PC.2 VMIDH PC.3 I91535AQI MICN PC.4 MICP PC.5 VMIDL PC.6 VCCA PC.7 HPOR VSSA PC.10 HPOL PC.11 VSSA PC.1...
Page 18: I91535H02Qi
ISD91500 Technical Reference Manual 3.2.2 I91535H02QI PA.9 USB_CAP PA.4 USB_D+ Top transparent view PA.3 USB_D- PA.2 USB_VBUS PA.1 nRESET PA.0 PC.2 MICBIAS PC.3 I91535H02QI VMIDH PC.4 MICN PC.5 MICP PC.6 VMIDL PC.7 VSSA VCCA PC.10 HPOR PC.11 HPOL PC.1 Figure 3.2-2 QFN48 Type2 Pin Diagram Feb.
Page 19: Pin/Pad Description
ISD91500 Technical Reference Manual Pin/Pad Description 3.3.1 LQFP64 I91535A I91535H 02DI Name Type Description Pin No. Pin No. PD.15 General purpose input/output pin; port D, bit15 I2C0_SDA I2C0 data input/output pin SPI1_MOSI1 SPI1 Master Out Slave In 1 PD.14 General purpose input/output pin; port D, bit14...
Page 20 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PD.8 General purpose input/output pin, port D, bit8 PWM1_ch0 PWM1 channel 0 output SPI0_SS0 SPI0 Slave Select 0 UART0_TX UART0 Transmitter Serial Out PD.7 General purpose input/output pin, port D, bit7...
Page 21 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PD.0 General purpose input/output pin, port D, bit0 UART1_nCTS UART1 Clear To Send Input PWM0_ch0 PWM0 channel 0 output I2S0_MCLK I2S0 Master Clock Output pin PC.14...
Page 22 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PC.9 General purpose input/output pin, port C, bit9 SPI0_MISO1 SPI0 Master In Slave Out 1 PWM1_ch3 PWM1 channel 3 output PWM1_ch2 PWM1 channel 2 output PC.8...
Page 23 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PC.2 General purpose input/output pin, port C, bit2 UART0_nCTS UART0 Clear To Send Input I2S0_LRCK I2S0 left right channel clock pin PWM0_ch0 PWM0 channel 0 output...
Page 24 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PA.10 General purpose input/output pin, port A, bit10 SPI0_MISO1 SPI0 Master In Slave Out 1 MCLKI External Clock Input UART0_TX UART0 Transmitter Serial Out PA.9 General purpose input/output pin, port A, bit9...
Page 25 ISD91500 Technical Reference Manual I91535A I91535H 02DI Name Type Description Pin No. Pin No. PA.2 General purpose input/output pin, port A, bit2 I2S0_BCLK I2S0 Bit Clock pin I2C0_SDA I2C0 data input/output pin SPI1_MOSI0 SPI1 Master Out Slave In 0 PA.1...
Page 26: Qfn48
ISD91500 Technical Reference Manual 3.3.2 QFN48 I91535A I91535H 02QI Name Type Description Pin No. Pin No. PD.13 General purpose input/output pin; port D, bit13 I2C1_SDA I2C1 data input/output pin SPI0_MISO1 SPI0 Master In Slave Out 1 ICE_DAT SWD Interface, Serial Data PD.12...
Page 27 ISD91500 Technical Reference Manual I91535A I91535H 02QI Name Type Description Pin No. Pin No. PC.13 General purpose input/output pin, port C, bit13 SPI0_MISO0 SPI0 Master In Slave Out 0 I2S0_DO I2S0 Data output pin UART1_TX UART1 Transmitter Serial Out PC.12...
Page 28 ISD91500 Technical Reference Manual I91535A I91535H 02QI Name Type Description Pin No. Pin No. PC.5 General purpose input/output pin, port C, bit5 UART0_RX UART0 Receiver Serial In I2S0_DI I2S0 Data input pin PWM0_ch3 PWM0 channel 3 output PC.4 General purpose input/output pin, port C, bit4...
Page 29 ISD91500 Technical Reference Manual I91535A I91535H 02QI Name Type Description Pin No. Pin No. PA.12 General purpose input/output pin, port A, bit12 SPI0_MOSI0 SPI0 Master Out Slave In 0 I2C1_SDA I2C1 data input/output pin UART0_nCTS UART0 Clear To Send Input...
Page 30 ISD91500 Technical Reference Manual I91535A I91535H 02QI Name Type Description Pin No. Pin No. PA.2 General purpose input/output pin, port A, bit2 I2S0_BCLK I2S0 Bit Clock pin I2C0_SDA I2C0 data input/output pin SPI1_MOSI0 SPI1 Master Out Slave In 0 PA.1...
Page 31: Pin Alternate Function
ISD91500 Technical Reference Manual Pin Alternate Function Table 3.4-1 Alternate function table of GPIO Special GPIO Power ALT =1 I/O of ALT = 1 ALT =2 I/O of ALT = 2 ALT =3 I/O of ALT = 3 Modes GPA0*...
Page 32 ISD91500 Technical Reference Manual Special GPIO Power ALT =1 I/O of ALT = 1 ALT =2 I/O of ALT = 2 ALT =3 I/O of ALT = 3 Modes GPC11* VCCPST SPI0_MOSI0 I2S0_LRCK UART1_nCTS GPC12* VCCPST SPI0_CLK I2S0_BCLK UART1_nRTS GPC13* VCCPST SPI0_MISO0...
Page 33: Block Diagram
ISD91500 Technical Reference Manual BLOCK DIAGRAM Power control Timer / PWM Analog Interface Memory 12-bit SARADC APROM POR / LVR Timer x3 12-ch 64KB Cortex SRAM 20KB WDT x1 24-bit DAC x2 CPU core LDO 50MHz (with Class AB HP 1.5V...
Page 34: Functional Description
ISD91500 Technical Reference Manual FUNCTIONAL DESCRIPTION ® ® Cortex -M0 core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB- Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor.
Page 35 ISD91500 Technical Reference Manual – Support for both level-sensitive and pulse-sensitive interrupt lines – Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.  Debug support – Four hardware breakpoints. – Two watchpoints. – Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
Page 36: System Manager
Combined peripheral interrupt source identify 5.2.2 System Memory Map ISD91500 provides a 4G-byte address space for programmers. The memory locations assigned to each on-chip modules are shown in Table 5.2-1 Table 5.2-1 is Address Space Assignments for On-Chip Modules. The detailed register and memory addressing and programming will be described in the following sections for individual on-chip modules.
Page 37 ISD91500 Technical Reference Manual 0x4005_0000 – 0x4005_0FFF PWM1_BA PWM1 Control Registers 0x4006_0000 – 0x4006_0FFF UART0_BA UART0 Control Registers 0x4006_1000 – 0x4006_1FFF UART1_BA UART1 Control Registers 0x4007_0000 – 0x4007_0FFF DAC_BA DAC Control Registers 0x4008_0000 – 0x4008_3FFF ANA_BA Analog Block Control Registers 0x4009_0000 –...
Page 38: System Manager Control Registers
ISD91500 Technical Reference Manual 5.2.3 System Manager Control Registers Register Offset R/W Description Reset Value SYS Base Address: SYS_BA = 0x5000_0000 SYS_PDID SYS_BA+0x00 Product Identifier Register 0xXXXX_XXXX SYS_RSTSTS SYS_BA+0x04 R/W System Reset Source Register 0x0000_0XXX SYS_IPRST0 SYS_BA+0x08 R/W IP Reset Control Resister0...
Page 39 ISD91500 Technical Reference Manual SYS_OSC10K SYS_BA+0x114 R/W 10KHz Oscillator and Bias trim register 0xXXXX_XXXX SYS_OSC_TRIMn SYS_BA+0x118+0x04*n R/W Oscillator Frequency Adjustment control register 0xXXXX_XXXX n=0,1,2 SYS_IRCTCTL SYS_BA+0x130 R/W HIRC Trim Control Register 0x0000_0000 SYS_IRCTIEN SYS_BA+0x134 R/W HIRC Trim Interrupt Enable Register...
Page 40 ISD91500 Technical Reference Manual Product Identifier Register (SYS_PDID) [1] Every part number has a unique default reset value. Register Offset Description Reset Value SYS_PDID SYS_BA+0x00 Product Identifier Register 0xXXXX_XXXX IMG2 IMG2 IMG2 IMG2 Bits Description Product Device Identification [31:0] IMG2 This register reflects device part number code.
Page 41 ISD91500 Technical Reference Manual System Reset Source Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Source Register 0x0000_0XXX Reserved Reserved Reserved...
Page 42 ISD91500 Technical Reference Manual Reset Source From PMU The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source. PMURSTF 0= No reset from PMU. 1= The PMU has issued the reset signal to reset the system.
Page 43 ISD91500 Technical Reference Manual IP Reset Control Register0 (SYS_IPRST0) Register Offset Description Reset Value SYS_IPRST0 SYS_BA+0x08 IP Reset Control Resister0 0x0000_0000 Reserved Reserved Reserved Reserved CPURST CHIPRST Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 44 ISD91500 Technical Reference Manual IP Reset Control Register1 (SYS_IPRST1) Setting these bits “1” will generate an asynchronous reset signal to the corresponding peripheral block. The user needs to set bit to “0” to release block from the reset state. Register...
Page 45 ISD91500 Technical Reference Manual PWM0 Controller Reset [20] PWM0RST 0 = Normal Operation. 1 = Reset. [19] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. BIQ Controller Reset [18] BIQRST 0 = Normal Operation.
Page 46 ISD91500 Technical Reference Manual Timer2 Controller Reset TMR2RST 0 = Normal operation. 1 = Reset. Timer1 Controller Reset TMR1RST 0 = Normal Operation. 1 = Reset. Timer0 Controller Reset TMR0RST 0 = Normal Operation. 1 = Reset. GPIO Controller Reset GPIORST 0 = Normal operation.
Page 47 ISD91500 Technical Reference Manual Brown-Out Detector Control Register (SYS_BODCTL) Register Offset Description Reset Value SYS_BODCTL SYS_BA+0x18 Brown-Out Detector Control Register 0x000X_00XX Partial of the SYS_BODCTL control registers values are initiated by the Flash configuration and partial bits are write-protected bit.
Page 48 ISD91500 Technical Reference Manual Brown-Out Detector Threshold Voltage Selection (Write Protected) The default value is set by flash controller user configuration CBOV bit (CONFIG0[25:22]). 0000 = Brown-out Detector threshold voltage is 1.8V. 0001 = Brown-out Detector threshold voltage is 1.9V.
Page 49 ISD91500 Technical Reference Manual GPIO PA Multiple Alternate Function and Input Type Control Register (SYS_GPA_MFP) Register Offset Description Reset Value GPIO PA Multiple Alternate Functions and Input Type Control SYS_GPA_MFP SYS_BA+0x20 0x0000_0000 Register PA15MFP PA14MFP PA13MFP PA12MFP PA11MFP PA10MFP PA9MFP...
Page 50 ISD91500 Technical Reference Manual PA.11 Multi-function Pin Selection 00 = PA.11. [23:22] PA11MFP 01 = SPI0_MOSI1. 10 = I2C1_SCL. 11 = UART0_RX. PA.10 Multi-function Pin Selection 00 = PA.10. [21:20] PA10MFP 01 = SPI0_MISO1. 10 = MCLKI. 11 = UART0_TX.
Page 51 ISD91500 Technical Reference Manual PA.4 Multi-function Pin Selection 00 = PA.4. [9:8] PA4MFP 01 = I2S0_DI. 10 = UART1_RX. 11 = SPI1_MISO0. PA.3 Multi-function Pin Selection 00 = PA.3. [7:6] PA3MFP 01 = I2S0_DO. 10 = UART1_TX. 11 = SPI1_CLK.
Page 52 ISD91500 Technical Reference Manual GPIO PB Multiple Alternate Function and Input Type Control Register (SYS_GPB_MFP) Register Offset Description Reset Value GPIO PB Multiple Alternate Functions and Input Type Control SYS_GPB_MFP SYS_BA+0x24 0x0000_0000 Register Reserved Reserved Reserved Reserved PB1MFP PB0MFP Bits...
Page 53 ISD91500 Technical Reference Manual GPIO PC Multiple Alternate Function and Input Type Control Register (SYS_GPC_MFP) Register Offset Description Reset Value GPIO PC Multiple Alternate Functions and Input Type Control SYS_GPC_MFP SYS_BA+0x28 0x0000_0000 Register PC15MFP PC14MFP PC13MFP PC12MFP PC11MFP PC10MFP PC9MFP...
Page 54 ISD91500 Technical Reference Manual PC.10 Multi-function Pin Selection 00 = PC.10. [21:20] PC10MFP 01 = SPI0_MOSI1. 10 = I2S0_MCLK. 11 = MCLKI. PC.9 Multi-function Pin Selection 00 = PC.9. [19:18] PC9MFP 01 = SPI0_MISO1. 10 = Reserved. 11 = PWM13.
Page 55 ISD91500 Technical Reference Manual PC.2 Multi-function Pin Selection 00 = PC.2. [5:4] PC2MFP 01 = UART0_nCTS. 10 = I2S0_LRCK. 11 = PWM00. PC.1 Multi-function Pin Selection 00 = PC.1. [3:2] PC1MFP 01 = XT1_IN. 10 = Reserved. 11 = I2C0_SDA.
Page 56 ISD91500 Technical Reference Manual GPIO PD Multiple Alternate Function and Input Type Control Register (SYS_GPD_MFP) Register Offset Description Reset Value GPIO PD Multiple Alternate Functions and Input Type Control SYS_GPD_MFP SYS_BA+0x2C 0x0F00_0000 Register PD15MFP PD14MFP PD13MFP PD12MFP PD11MFP PD10MFP PD9MFP...
Page 57 ISD91500 Technical Reference Manual PD.11 Multi-function Pin Selection 00 = PD.11. [23:22] PD11MFP 01 = PWM13. 10 = SPI0_MOSI0. 11 = I2C1_SDA. PD.10 Multi-function Pin Selection 00 = PD.10. [21:20] PD10MFP 01 = PWM12. 10 = SPI0_CLK. 11 = I2C1_SCL.
Page 58 ISD91500 Technical Reference Manual PC.4 Multi-function Pin Selection 00 = PD.4. [9:8] PD4MFP 01 = PWM00. 10 = CAP0. 11 = I2S0_DI. PC.3 Multi-function Pin Selection 00 = PD.3. [7:6] PD3MFP 01 = UART1_RX. 10 = PWM03. 11 = I2S0_DO.
Page 59 ISD91500 Technical Reference Manual GPIO Input type control (SYS_GPIO_INTP) Register Offset Description Reset Value SYS_GPIO_INTP SYS_BA+0x40 GPIO input type and slew rate Control 0xFFFF_03FF GPD[15:12]HS GPD[15:12]SS GPD[11:8]HS GPD[11:8]SS GPD[7:4]HS GPD[7:4]SS GPD[3:0]HS GPD[3:0]SS GPC[15:12]HS GPC[15:12]SS GPC[11:8]HS GPC[11:8]SS GPC[7:4]HS GPC[7:4]SS GPC[3:0]HS GPC[3:0]SS...
Page 60 ISD91500 Technical Reference Manual PA.15~PA.0 Pull Resistance Control Register (SYS_GPA_PULL) Register Offset Description Reset Value SYS_GPA_PULL SYS_BA+0x44 PA.15 ~ PA.0 Pull Resistance Control Register 0x0000_0000 Reserved Reserved PUEN PUEN Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 61 ISD91500 Technical Reference Manual PA.15~PA.0 Pull Resistance Select Control Register (SYS_GPA_HR) Register Offset Description Reset Value SYS_GPA_HR SYS_BA+0x48 PA.15 ~ PA.0 Pull Resistance Select Control Register 0x0000_FFFF Reserved Reserved PUHR PUHR Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 62 ISD91500 Technical Reference Manual PA.15~PA.0 Digital Buffer Control Register (SYS_GPA_IEN) Register Offset Description Reset Value PA.15 ~ PA.0 Digital and Analog Input Buffer Control SYS_GPA_IEN SYS_BA+0x4C 0x0000_0000 Register Reserved Reserved Bits Description Reserved. Any values read should be ignored. When writing to this field always write with reset...
Page 63 ISD91500 Technical Reference Manual PB.1~PB.0 Pull Resistance Control Register (SYS_GPB_PULL) Register Offset Description Reset Value SYS_GPB_PULL SYS_BA+0x54 PB.1 ~ PB.0 Pull Resistance Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PUEN Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 64 ISD91500 Technical Reference Manual PB.1~PB.0 Pull Resistance Select Control Register (SYS_GPB_HR) Register Offset Description Reset Value SYS_GPB_HR SYS_BA+0x58 PB.1 ~ PB.0 Pull Resistance Select Control Register 0x0000_0003 Reserved Reserved Reserved Reserved PUHR Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 65 ISD91500 Technical Reference Manual PB.1~PB.0 Digital Input Buffer Control Register (SYS_GPB_IEN) Register Offset Description Reset Value SYS_GPB_IEN SYS_BA+0x5C PB.1 ~ PB.0 Digital Input Buffer Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 66 ISD91500 Technical Reference Manual PC.15~PC.0 Pull Resistance Control Register (SYS_GPC_PULL) Register Offset Description Reset Value SYS_GPC_PULL SYS_BA+0x64 PC.15 ~ PC.0 Pull Resistance Control Register 0x0000_0000 Reserved Reserved PUEN PUEN Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 67 ISD91500 Technical Reference Manual PC.15~PC.0 Pull Resistance Select Control Register (SYS_GPC_HR) Register Offset Description Reset Value SYS_GPC_HR SYS_BA+0x68 PC.15 ~ PC.0 Pull Resistance Select Control Register 0x0000_FFFF Reserved Reserved PUHR PUHR Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 68 ISD91500 Technical Reference Manual PC.15~PC.0 Digital Buffer Control Register (SYS_GPC_IEN) Register Offset Description Reset Value SYS_GPC_IEN SYS_BA+0x6C PC.15 ~ PC.0 Digital Input Buffer Control Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 69 ISD91500 Technical Reference Manual PD.15~PD.0 Pull Resistance Control Register (SYS_GPD_PULL) Register Offset Description Reset Value SYS_GPD_PULL SYS_BA+0x74 PD.15 ~ PD.0 Pull Resistance Control Register 0x0000_0000 Reserved Reserved PUEN PUEN Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 70 ISD91500 Technical Reference Manual PD.15~PD.0 Pull Resistance Select Control Register (SYS_GPD_HR) Register Offset Description Reset Value SYS_GPD_HR SYS_BA+0x78 PD.15 ~ PD.0 Pull Resistance Select Control Register 0x0000_FFFF Reserved Reserved PUHR PUHR Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 71 ISD91500 Technical Reference Manual PD.15~PD.0 Digital Buffer Control Register (SYS_GPD_IEN) Register Offset Description Reset Value SYS_GPD_IEN SYS_BA+0x7C PD.15 ~ PD.0 Digital Input Buffer Control Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 72 ISD91500 Technical Reference Manual Register Lock Control Register (SYS_REGLCTL) Certain critical system control registers are protected against inadvertent write operations which may disturb chip operation. These system control registers are locked after power on reset until the user specifically issues an unlock sequence to disable register protection.
Page 73 ISD91500 Technical Reference Manual Oscillator Trim Control Register (SYS_OSCTRIM) The master oscillator of the deivce has an adjustable frequency and is controlled by the OSCTRIM and OSC_TRIM[n] registers. There are three factory trimmed settings available for the oscillator, the active one being selected by the OSCFSEL bits of CLKSEL0.
Page 74 ISD91500 Technical Reference Manual 10kHz Oscillator Trim Control Register (SYS_OSC10K) Register Offset R/W Description Reset Value SYS_OSC10K SYS_BA+0x114 R/W 10KHz Oscillator and Bias trim register 0xXXXX_XXXX TRM_CLK Reserved Reserved OSC10K_TRIM OSC10K_TRIM OSC10K_TRIM Bits Description OSC10K Trim Value Update Bit [31]...
Page 75 ISD91500 Technical Reference Manual Oscillator Trim Control Register (SYS_OSC_TRIM[n]) Register Offset Description Reset Value SYS_OSC_TRIMn SYS_BA+0x118+0x04*n R/W Oscillator Frequency Adjustment control register 0xXXXX_XXXX n=0,1,2 EN2MHZ Reserved Reserved TRIM TRIM Bits Description HIRC Clock Frequency Selection (Write Protect) 1 = High frequency mode (20-50 MHz).
Page 76 ISD91500 Technical Reference Manual HIRC Trim Control Register (SYS_IRCTCTL) Register Offset Description Reset Value SYS_IRCTCTL SYS_BA+0x130 HIRC Trim Control Register 0x0000_0000 Reserved Reserved Reserved REFCKSEL Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:11] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 77 ISD91500 Technical Reference Manual Trim Calculation Loop Selection This field defines that trim value calculation is based on how many internal reference clocks. 00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
Page 78 ISD91500 Technical Reference Manual HIRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset Description Reset Value SYS_IRCTIEN SYS_BA+0x134 HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 79 ISD91500 Technical Reference Manual HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset Description Reset Value SYS_IRCTISTS SYS_BA+0x138 HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKERRIF TFAILIF FREQLOCK Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 80 ISD91500 Technical Reference Manual HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn’t trigger any interrupt FREQLOCK Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
Page 81 ISD91500 Technical Reference Manual HIRC Trim Clock Reference Frequency Register (SYS_IRCTCKRF) Register Offset Description Reset Value SYS_IRCTCKRF SYS_BA+0x13C HIRC Trim Clock Reference Frequency Register 0x0000_0020 Reserved Reserved Reserved HXTFREQ HXTFREQ Bits Description [31:15] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 82 ISD91500 Technical Reference Manual Bandgap Trim Control Register (SYS_BGAPTRIM) Register Offset R/W Description Reset Value SYS_BGAPTRIM SYS_BA+0x140 R/W Bandgap Trim Control Register 0x0000_000X Reserved Reserved Reserved Reserved TRIM Bits Description [31:4] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 83 ISD91500 Technical Reference Manual Uniq Customer ID Register (SYS_UCID[n]) Register Offset R/W Description Reset Value SYS_UCID[n] Specified ID register for library and customized feature SYS_BA+0x150+0x04*n R 0xXXXX_XXXX checking n=0,1,2,3 This register provides specific read-only information for software to check the UCID.
Page 84: System Timer (Syst)
ISD91500 Technical Reference Manual 5.2.4 System Timer (SYST) The Cortex-M0 includes an integrated system timer, SYST. SYST provides a simple, 24-bit,Clear-on- write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ...
Page 85 ISD91500 Technical Reference Manual 5.2.4.1 Register Map R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear Register Offset R/W Description Reset Value SYSTICK Base Address: SYSTICK_BA = 0xE000_E000 SYST_CSR SYSTICK_BA+0x10 R/W SYST Control and Status Register...
Page 86 ISD91500 Technical Reference Manual 5.2.4.2 Register Description SYST Control and Status（SYST_CSR） Register Offset Description Reset Value SYST_CSR SYSTICK_BA+0x10 SYST Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description [31:17] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 87 ISD91500 Technical Reference Manual SYST Reload Value Register（SYST_RVR） Register Offset Description Reset Value SYST_RVR SYSTICK_BA+0x14 SYST Reload Value Register 0xXXXX_XXXX Reserved RELOAD RELOAD RELOAD Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 88 ISD91500 Technical Reference Manual SYST Current Value Register（SYST_CVR） Register Offset Description Reset Value SYST_CVR SYSTICK_BA+0x18 SYST Current Value Register 0xXXXX_XXXX Reserved CURRENT CURRENT CURRENT Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 89: Nested Vectored Interrupt Controller (Nvic)
ISD91500 Technical Reference Manual 5.2.5 Nested Vectored Interrupt Controller (NVIC) Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides following features: ...
Page 90: Table 5.2-3 System Interrupt Map
ISD91500 Technical Reference Manual SVCall Configurable Reserved 12 ~ 13 PendSV Configurable SysTick Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 5.2-3 System Interrupt Map Interrupt Number Vector Interrupt Name Source IP Interrupt Description (Bit Interrupt Number Registers)
Page 91: Table 5.2-4 Vector Table Format
ISD91500 Technical Reference Manual IRCTRIM_INT IRCTRIM IRCTRIM intrrupt USB_INT USB interrupt CPD_INT Companding Companding interrupt XCLKF_INT XCLK Fail XCLK Fail interrupt SPI1_INT SPI1 Interrupt from SPI1 >43 >27 Reserved 5.2.5.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from the vector table in memory.
Page 92 ISD91500 Technical Reference Manual 5.2.5.4 NVIC Control Registers R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear Register Offset Description Reset Value SCS Base Address: SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ26 Set-Enable Control Register...
Page 93 ISD91500 Technical Reference Manual IRQ0 ~ IRQ26 Set-Enable Control Register （NVIC_ISER） Register Offset Description Reset Value NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ26 Set-Enable Control Register 0x0000_0000 If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
Page 94 ISD91500 Technical Reference Manual IRQ0 ~ IRQ26 Clear-Enable Control Register (NVIC_ICER） Register Offset Description Reset Value NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ26 Clear-Enable Control Register 0x0000_0000 Reserved CLRENA CLRENA CLRENA CLRENA Bits Description [31:26] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 95 ISD91500 Technical Reference Manual IRQ0 ~ IRQ26 Set-Pending Control Register （NVIC_ISPR） Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x200 IRQ0 ~ IRQ26 Set-Pending Control Register 0x0000_0000 Reserved SETPEND SETPEND SETPEND SETPEND Bits Description [31:26] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 96 ISD91500 Technical Reference Manual IRQ0 ~ IRQ26 Clear-Pending Control Register （NVIC_ICPR） Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x280 IRQ0 ~ IRQ26 Clear-Pending Control Register 0x0000_0000 Reserved CLRPEND CLRPEND CLRPEND CLRPEND Bits Description [31:26] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 97 ISD91500 Technical Reference Manual IRQ0 ~ IRQ3 Interrupt Priority Register （NVIC_IPR0） Register Offset Description Reset Value NVIC_IPR0 SCS_BA+0x400 IRQ0 ~ IRQ3 Priority Control Register 0x0000_0000 PRI_3 Reserved PRI_2 Reserved PRI_1 Reserved PRI_0 Reserved Bits Description Priority Of IRQ3 [31:30] PRI_3 “0”...
Page 98 ISD91500 Technical Reference Manual IRQ4 ~ IRQ7 Interrupt Priority Register （NVIC_IPR1） Register Offset Description Reset Value NVIC_IPR1 SCS_BA+0x404 IRQ4 ~ IRQ7 Priority Control Register 0x0000_0000 PRI_7 Reserved PRI_6 Reserved PRI_5 Reserved PRI_4 Reserved Bits Description Priority Of IRQ7 [31:30] PRI_7 “0”...
Page 99 ISD91500 Technical Reference Manual IRQ8 ~ IRQ11 Interrupt Priority Register （NVIC_IPR2） Register Offset Description Reset Value NVIC_IPR2 SCS_BA+0x408 IRQ8 ~ IRQ11 Priority Control Register 0x0000_0000 PRI_11 Reserved PRI_10 Reserved PRI_9 Reserved PRI_8 Reserved Bits Description Priority Of IRQ11 [31:30] PRI_11 “0”...
Page 100 ISD91500 Technical Reference Manual IRQ12 ~ IRQ15 Interrupt Priority Register （NVIC_IPR3） Register Offset Description Reset Value NVIC_IPR3 SCS_BA+0x40C IRQ12 ~ IRQ15 Priority Control Register 0x0000_0000 PRI_15 Reserved PRI_14 Reserved PRI_13 Reserved PRI_12 Reserved Bits Description Priority Of IRQ15 [31:30] PRI_15 “0”...
Page 101 ISD91500 Technical Reference Manual IRQ16 ~ IRQ19 Interrupt Priority Register （NVIC_IPR4） Register Offset Description Reset Value NVIC_IPR4 SCS_BA+0x410 IRQ16 ~ IRQ19 Priority Control Register 0x0000_0000 PRI_19 Reserved PRI_18 Reserved PRI_17 Reserved PRI_16 Reserved Bits Description Priority Of IRQ19 [31:30] PRI_19 “0”...
Page 102 ISD91500 Technical Reference Manual IRQ20 ~ IRQ23 Interrupt Priority Register （NVIC_IPR5） Register Offset Description Reset Value NVIC_IPR5 SCS_BA+0x414 IRQ20 ~ IRQ23 Priority Control Register 0x0000_0000 PRI_23 Reserved PRI_22 Reserved PRI_21 Reserved PRI_20 Reserved Bits Description Priority Of IRQ23 [31:30] PRI_23 “0”...
Page 103 ISD91500 Technical Reference Manual IRQ24 ~ IRQ26 Interrupt Priority Register （NVIC_IPR6） Register Offset Description Reset Value NVIC_IPR6 SCS_BA+0x418 IRQ24 ~ IRQ26 Priority Control Register 0x0000_0000 Reserved PRI_26 Reserved PRI_25 Reserved PRI_24 Reserved Bits Description Priority Of IRQ26 [23:22] PRI_26 “0” denotes the highest priority and “3” denotes lowest priority...
Page 104 ISD91500 Technical Reference Manual 5.2.5.5 Interrupt Source Control Registers Along with the interrupt control registers associated with the NVIC, This device also implements some specific control registers to facilitate the interrupt functions, including “interrupt source identify” and”NMI source selection”. They are described as below.
Page 105 ISD91500 Technical Reference Manual IRQ23_SRC INT_BA+0x5C IRQ23 (USB) Interrupt Source Identity Register 0xXXXX_XXXX IRQ24_SRC INT_BA+0x60 IRQ24 (CPD) Interrupt Source Identity Register 0xXXXX_XXXX IRQ25_SRC INT_BA+0x64 IRQ25 (XCLKF) Interrupt Source Identity Register 0xXXXX_XXXX IRQ26_SRC INT_BA+0x68 IRQ26 (SPI1) Interrupt Source Identity Register 0xXXXX_XXXX...
Page 106 ISD91500 Technical Reference Manual IRQ0 (WDT) Interrupt Source Identify Register (IRQ0_SRC) Register Offset Description Reset Value IRQ0_SRC INT_BA+0x00 IRQ0 (WDT) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 107 ISD91500 Technical Reference Manual IRQ1 (DAC) Interrupt Source Identify Register (IRQ1_SRC) Register Offset Description Reset Value IRQ1_SRC INT_BA+0x04 IRQ1 (DAC) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 108 ISD91500 Technical Reference Manual IRQ2 (SARADC) Interrupt Source Identify Register (IRQ2_SRC) Register Offset Description Reset Value IRQ2_SRC INT_BA+0x08 IRQ2 (SARADC) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 109 ISD91500 Technical Reference Manual IRQ3 (SDADC) Interrupt Source Identify Register (IRQ3_SRC) Register Offset Description Reset Value IRQ3_SRC INT_BA+0x0C IRQ3 (SDADC) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 110 ISD91500 Technical Reference Manual IRQ4 (I2S0) Interrupt Source Identify Register (IRQ4_SRC) Register Offset Description Reset Value IRQ4_SRC INT_BA+0x10 IRQ4 (I2S0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 111 ISD91500 Technical Reference Manual IRQ5 (Timer0) Interrupt Source Identify Register (IRQ5_SRC) Register Offset Description Reset Value IRQ5_SRC INT_BA+0x14 IRQ5 (Timer0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 112 ISD91500 Technical Reference Manual IRQ6 (Timer1) Interrupt Source Identify Register (IRQ6_SRC) Register Offset Description Reset Value IRQ6_SRC INT_BA+0x18 IRQ6 (Timer1) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 113 ISD91500 Technical Reference Manual IRQ7 (Timer2) Interrupt Source Identify Register (IRQ7_SRC) Register Offset Description Reset Value IRQ7_SRC INT_BA+0x1C IRQ7 (Timer2) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 114 ISD91500 Technical Reference Manual IRQ8 (GPA) Interrupt Source Identify Register (IRQ8_SRC) Register Offset Description Reset Value IRQ8_SRC INT_BA+0x20 IRQ8 (GPA) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 115 ISD91500 Technical Reference Manual IRQ9 (GPB) Interrupt Source Identify Register (IRQ9_SRC) Register Offset Description Reset Value IRQ9_SRC INT_BA+0x24 IRQ9 (GPB) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 116 ISD91500 Technical Reference Manual IRQ10 (GPC) Interrupt Source Identify Register (IRQ10_SRC) Register Offset Description Reset Value IRQ10_SRC INT_BA+0x28 IRQ10 (GPC) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 117 ISD91500 Technical Reference Manual IRQ11 (GPD) Interrupt Source Identify Register (IRQ11_SRC) Register Offset Description Reset Value IRQ11_SRC INT_BA+0x2C IRQ11 (GPD) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 118 ISD91500 Technical Reference Manual IRQ12 (SPI0) Interrupt Source Identify Register (IRQ12_SRC) Register Offset Description Reset Value IRQ12_SRC INT_BA+0x30 IRQ12 (SPI0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 119 ISD91500 Technical Reference Manual IRQ13 (PWM0) Interrupt Source Identify Register (IRQ13_SRC) Register Offset Description Reset Value IRQ13_SRC INT_BA+0x34 IRQ13 (PWM0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 120 ISD91500 Technical Reference Manual IRQ14 (PWM1) Interrupt Source Identify Register (IRQ14_SRC) Register Offset Description Reset Value IRQ14_SRC INT_BA+0x38 IRQ14 (PWM1) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 121 ISD91500 Technical Reference Manual IRQ15 (PDMA) Interrupt Source Identify Register (IRQ15_SRC) Register Offset Description Reset Value IRQ15_SRC INT_BA+0x3C IRQ15 (PDMA) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 122 ISD91500 Technical Reference Manual IRQ16 (I2C0) Interrupt Source Identify Register (IRQ16_SRC) Register Offset Description Reset Value IRQ16_SRC INT_BA+0x40 IRQ16 (I2C0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 123 ISD91500 Technical Reference Manual IRQ17 (I2C1) Interrupt Source Identify Register (IRQ17_SRC) Register Offset Description Reset Value IRQ17_SRC INT_BA+0x44 IRQ17 (I2C1) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 124 ISD91500 Technical Reference Manual IRQ18 (BOD) Interrupt Source Identify Register (IRQ18_SRC) Register Offset Description Reset Value IRQ18_SRC INT_BA+0x48 IRQ18 (BOD) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 125 ISD91500 Technical Reference Manual IRQ20 (UART0) Interrupt Source Identify Register (IRQ20_SRC) Register Offset Description Reset Value IRQ20_SRC INT_BA+0x50 IRQ20 (UART0) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 126 ISD91500 Technical Reference Manual IRQ21 (UART1) Interrupt Source Identify Register (IRQ21_SRC) Register Offset Description Reset Value IRQ21_SRC INT_BA+0x54 IRQ21 (UART1) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 127 ISD91500 Technical Reference Manual IRQ22 (IRCTRIM) Interrupt Source Identify Register (IRQ22_SRC) Register Offset Description Reset Value IRQ22_SRC INT_BA+0x58 IRQ22 (IRCTRIM) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 128 ISD91500 Technical Reference Manual IRQ23 (USB) Interrupt Source Identify Register (IRQ23_SRC) Register Offset Description Reset Value IRQ23_SRC INT_BA+0x5C IRQ23 (USB) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 129 ISD91500 Technical Reference Manual IRQ24 (CPD) Interrupt Source Identify Register (IRQ24_SRC) Register Offset Description Reset Value IRQ24_SRC INT_BA+0x60 IRQ24 (CPD) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 130 ISD91500 Technical Reference Manual IRQ25 (XCLKF) Interrupt Source Identify Register (IRQ25_SRC) Register Offset Description Reset Value IRQ25_SRC INT_BA+0x64 IRQ25 (XCLKF) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 131 ISD91500 Technical Reference Manual IRQ26 (SPI1) Interrupt Source Identify Register (IRQ26_SRC) Register Offset Description Reset Value IRQ26_SRC INT_BA+0x68 IRQ26 (SPI1) Interrupt Source Identity Register 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC[2:0] Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 132 ISD91500 Technical Reference Manual NMI Interrupt Source Select Control Register (NMI_SEL) Register Offset Description Reset Value NMI_SEL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_001F Reserved Reserved Reserved Reserved NMI_SEL Bits Description [31:5] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 133: System Control Registers
ISD91500 Technical Reference Manual 5.2.6 System Control Registers Key control and status features of Coterx-M0 are managed centrally in a System Control Block within the System Control Registers. For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical Reference Manual”...
Page 134 ISD91500 Technical Reference Manual CPUID Base Register (SYSINFO_CPUID) Register Offset R/W Description Reset Value SYSINFO_CPUID SYSINFO_BA+0x000 CPUID Base Register 0x410C_C200 IMPCODE Reserved PART PARTNO PARTNO REVISION Bits Description Implementer Code Assigned by ARM [31:24] IMPCODE ARM = 0x41. [23:20] Reserved Reserved.
Page 135 ISD91500 Technical Reference Manual Interrupt Control State Register (SYSINFO_ICSR) Register Offset Description Reset Value SYSINFO_ICSR SYSINFO_BA+0x004 Interrupt Control State Register 0x0000_0000 NMIPNSET Reserved PPSVISET PPSVICLR PSTKISET PSTKICLR Reserved ISRPREEM ISRPEND Reserved VTPNDING VTPEND Reserved VTACT VTACT Bits Description NMI Pending Set Control...
Page 136 ISD91500 Technical Reference Manual Reserved. Any values read should be ignored. When writing to this field always write with reset [11:9] Reserved value. Vector Active [8:0] VTACT 0: Thread mode Value > 1: the exception number for the current executing exception.
Page 137 ISD91500 Technical Reference Manual Application Interrupt and Reset Control Register (SYSINFO_AIRCTL) Register Offset Description Reset Value SYSINFO_AIRCTL SYSINFO_BA+0x00C Application Interrupt and Reset Control Register 0xFA05_0000 VTKEY VTKEY ENDIANES Reserved Reserved SRSTREQ CLRACTVT Reserved Bits Description Vector Key [31:16] VTKEY The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE.
Page 138 ISD91500 Technical Reference Manual System Control Register (SYSINFO_SCR) Register Offset R/W Description Reset Value SYSINFO_SCR SYSINFO_BA+0x010 R/W System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVNONPN Reserved SLPDEEP SLPONEXC Reserved Bits Description [31:5] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 139 ISD91500 Technical Reference Manual System Handler Priority Register2 (SYSINFO_SHPR2) Register Offset R/W Description Reset Value SYSINFO_SHPR2 SYSINFO_BA+0x01C R/W System Handler Priority Register 2 0x0000_0000 PRI11 Reserved Reserved Reserved Reserved Bits Description Priority of System Handler 11 – SVCall [31:30] PRI11 “0”...
Page 140 ISD91500 Technical Reference Manual System Handler Priority Register3 (SYSINFO_SHPR3) Register Offset R/W Description Reset Value SYSINFO_SHPR3 SYSINFO_BA+0x020 R/W System Handler Priority Register 3 0x0000_0000 PRI15 Reserved PRI14 Reserved Reserved Reserved Bits Description Priority of System Handler 15 – SYST [31:30] PRI15 “0”...
Page 141: Clock Controller
ISD91500 Technical Reference Manual Clock Controller 5.3.1 Overview The clock controller generates the clock sources for the whole chip. It includes all AMBA interface modules and all peripheral clocks, ADC, and so on. The controller also implements the power control function, include the individually clock on or off control register, clock source select and the divided number from clock source.
Page 142: Figure 5.3-1 Clock Tree
ISD91500 Technical Reference Manual HIRC LIRC HIRC PLLFOUT XCLK PLL FOUT PWM0 PWM1 I2C0/1 CLK_PLLCTL[20:19] PDMA SPI0 PCLK SRAM I2S_BCLK TMR0~2 Clock XCLK MCLKI Doubler SDADC CLK_CLKSEL2[4] SARADC HIRC LIRC HCLK 1/(HCLKDIV+1) PLLFOUT CLK_CLKSEL0[1:0] HCLK 1/(BIQDIV+1) HIRC HCLK HIRC SysTick...
Page 143: Clock Generator
ISD91500 Technical Reference Manual 5.3.2 Clock Generator The clock generator consists of 3 sources which are listed below:  One external 4~24MHz crystal (High speed external crystal, HXT).  One internal 10 KHz RC oscillator (Low speed internal Oscillator, LIRC).
Page 144: Peripheral Clock
ISD91500 Technical Reference Manual Need to notice that the system clock is provided to CPU and whole system, the clock source should be stable and never disconnected. When PLL source from XCLK, the system clock is not suggested to select PLLFOUT as its clock source.
Page 145 ISD91500 Technical Reference Manual To configure the device for DPD the user sets the following options: • SYSCLK->PWRCTL.SELWKTMR: Select OSC10K cycles in this register,it will trigger a wakeup event after a certain number of OSC10K clock cycles when WK10KEN = 0’b .
Page 146: Register Map
ISD91500 Technical Reference Manual 5.3.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value CLK Base Address: CLK_BA = 0x5000_0200 CLK_PWRCTL CLK_BA+0x00 R/W System Power Control Register 0x0803_X125 CLK_AHBCLK CLK_BA+0x04...
Page 147: Register Description
ISD91500 Technical Reference Manual 5.3.7 Register Description System Power Control Register (CLK_PWRCTL) Register Offset Description Reset Value CLK_PWRCTL CLK_BA+0x00 System Power Control Register 0x0803_X125 WKTMRSTS Reserved TMRWKF WKPINWKF Reserved SELWKTMR FLASHEN WK10KEN WKPINEN VSET LIRCEN Reserved DPDEN STOPEN Reserved IOFWK...
Page 148 ISD91500 Technical Reference Manual Determine whether FLASH memory enters deep power down. FLASHEN[0]= 1: flash enters deep power down upon DEEP_SLEEP FLASHEN[1]= 1: flash enters deep power down upon STOP mode. [19:18] FLASHEN If FLASHEN is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence.
Page 149 ISD91500 Technical Reference Manual HXT Gain Control Bit This is a protected register. Please refer to open lock sequence to program it. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Page 150 ISD91500 Technical Reference Manual AHB Device Clock Enable Control Register (CLK_AHBCLK) These register bits are used to enable/disable the clock source for AMBA, AHB (Advanced High- Performance Bus) blocks and peripherals. Register Offset Description Reset Value CLK_AHBCLK CLK_BA+0x04 AHB Device Clock Enable Control Register...
Page 151 ISD91500 Technical Reference Manual APB Device Clock Enable Control Register (CLK_APBCLK) These register bits are used to enable/disable clocks for APB (Advanced Peripheral Bus) peripherals. To enable the clocks write ‘1’ to the appropriate bit. To reduce power consumption and disable the peripheral, write ‘0’...
Page 152 ISD91500 Technical Reference Manual PWM1 Block Clock Enable Control [21] PWM1EN 0 = PWM1 clock Disabled. 1 = PWM1 clock Enabled. PWM0 Block Clock Enable Control [20] PWM0EN 0 = PWM0 clock Disabled. 1 = PWM0 clock Enabled. Biquad Filter(BIQ) Block Clock Enable Control...
Page 153 ISD91500 Technical Reference Manual Timer1 Clock Enable Control TMR1EN 0 = Timer1 clock Disabled. 1 = Timer1 clock Enabled. Timer0 Clock Enable Control TMR0EN 0 = Timer0 clock Disabled. 1 = Timer0 clock Enabled. Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 154 ISD91500 Technical Reference Manual DPD State Register and Flash Regulator Control (CLK_DPDFLR) Register Offset Description Reset Value CLK_DPDFLR CLK_BA+0x0C DPD State Register and Flash Regulator Control 0x0000_XXXX Reserved Reserved PD_STATE_RB PD_STATE Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 155 ISD91500 Technical Reference Manual Clock Source Select Control Register 0 (CLK_CLKSEL0) Register Offset Description Reset Value CLK_CLKSEL0 CLK_BA+0x10 Clock Source Select Control Register 0 0x0003_001B Reserved Reserved FCLK_MUX_STATE Reserved OSCFSEL Reserved STICKSEL Reserved HCLKSEL Bits Description Reserved. Any values read should be ignored. When writing to this field always write with reset...
Page 156 ISD91500 Technical Reference Manual SysTick Clock Source Selection (Write Protected) 00 = clock source from HXT 01 = clock source from HXT/2 10 = clock source from HCLK/2 11 = clock source from HIRC/2 [4:3] STICKSEL Note 1: When power on, HIRC is selected as HCLK clock source.
Page 157 ISD91500 Technical Reference Manual Clock Source Select Control Register 1 (CLK_CLKSEL1) Register Offset Description Reset Value CLK_CLKSEL1 CLK_BA+0x14 Clock Source Select Control Register 1 0xAF37_77A8 PWM1SEL PWM0SEL UART1SEL UART0SEL Reserved I2S0SEL Reserved TMR2SEL Reserved TMR1SEL Reserved TMR0SEL Reserved SARADCSEL Reserved...
Page 158 ISD91500 Technical Reference Manual I2S0 Clock Source Select 000 = Clock source from HXT. 001 = Clock source from PLLFOUT. 010 = Clock source from PCLK. [22:20] I2S0SEL 011 = Clock source from HIRC. 100 = Clock source from MCLKI.
Page 159 ISD91500 Technical Reference Manual Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. Watchdog Timer Clock Source Selection (Write Protect) 0 = Clock source from LIRC. WDTSEL 1 = Clock source from HCLK/2048.
Page 160 ISD91500 Technical Reference Manual Clock Divider Register0 (CLK_CLKDIV0) Register Offset Description Reset Value CLK_CLKDIV0 CLK_BA+0x18 Clock Divider Number Register 0 0x0018_0000 Reserved Reserved SARADCDIV USBDIV UART1DIV UART0DIV HCLKDIV Bits Description [31:23] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 161 ISD91500 Technical Reference Manual Clock Divider Register1 (CLK_CLKDIV1) Register Offset Description Reset Value CLK_CLKDIV1 CLK_BA+0x1C Clock Divider Number Register 1 0x0000_0000 Reserved SDADCDIV Reserved BIQDIV DACDIV Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 162 ISD91500 Technical Reference Manual Clock Status Monitor Register (CLK_STATUS) Register Offset Description Reset Value CLK_STATUS CLK_BA+0x20 Clock Status Monitor Register 0x0000_0000 Reserved Reserved Reserved Reserved XCLKSTB PLLSTB HIRCSTB LIRCSTB HXTSTB Bits Description [31:5] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 163 ISD91500 Technical Reference Manual Power Down Flag Register (CLK_PFLAG) Register Offset Description Reset Value CLK_PFLAG CLK_BA+0x24 Power down Flag Register 0x0000_000X Reserved Reserved Reserved Reserved STOPF Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 164 ISD91500 Technical Reference Manual Clock Source Select Control Register 2 (CLK_CLKSEL2) Register Offset Description Reset Value CLK_CLKSEL2 CLK_BA+0x28 Clock Source Select Control Register 2 0x0000_3300 Reserved Reserved Reserved SDADCSEL Reserved DACSEL Reserved XCLKSEL Reserved USBSEL Bits Description [31:15] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 165 ISD91500 Technical Reference Manual [3:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. USB Clock Source Select USBSEL 0 = Clock source from HIRC. 1 = Clock source from PLLFOUT.
Page 166 ISD91500 Technical Reference Manual Clock Doubler Control Register (CLK_XCLKCTL) Register Offset Description Reset Value CLK_XCLKCTL CLK_BA+0x2C Clock doubler Output Control Register 0x0000_0000 Reserved Reserved Reserved XCLKFIF XCLKFIEN XCLKFDEN Reserved Reserved RELOCK XCLKEN Reserved XCLKMUL Bits Description [31:15] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 167 ISD91500 Technical Reference Manual Clock doubler Output Frequency Multiplication 00 = Output frequency multiply by 1 (Bypass) [1:0] XCLKMUL 01 = Output frequency multiply by 2 10 = Output frequency multiply by 4 11 = Output frequency multiply by 8 Feb.
Page 168 ISD91500 Technical Reference Manual PLL Control Register (CLK_PLLCTL) Register Offset Description Reset Value CLK_PLLCTL CLK_BA+0x30 PLL Control Register 0x0005_8430 Reserved STBSEL FTREN Reserved PLLSRC OUTDIV Reserved INDIV Reserved Reserved FBDIV Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 169 ISD91500 Technical Reference Manual Note: This bit is write protected. Refer to the SYS_REGLCTL register. Power-down Mode (Write Protected) If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. [16] 0 = PLL is in normal mode.
Page 170: Table 5.3-1 The Symbol Definition Of Pll Output Frequency Formula
ISD91500 Technical Reference Manual Table 5.3-1 The symbol definition of PLL Output Frequency formula Symbol Description FOUT Output Clock Frequency Input (Reference) Clock Frequency Input Divider INDIV=0, NR =16 INDIV=1~16, NR =INDIV Feedback Divider FBDIV=0, NF =64 FBDIV=1~64, NF =FBDIV OUTDIV = “00”...
Page 171 ISD91500 Technical Reference Manual Internal LDO Control Register (CLK_ILDOCTL) Register Offset Description Reset Value CLK_ILDOCTL CLK_BA+0xF4 Ineternal LDO Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 172: Sram
ISD91500 Technical Reference Manual SRAM 5.4.1 Overview This device equips with 20KB SRAM for program code and data storage. It’s an AHB slave interface. It supports byte, half, and word read, and write access. 5.4.2 Block Diagram The block diagram of SRAM Controller with rotation engine is depicted as following:...
Page 173: General Purpose I/O (Gpio)
ISD91500 Technical Reference Manual General Purpose I/O (GPIO) 5.5.1 Overview There are 50 pins of General Purpose I/O shared with special feature functions. These pins are arranged in 4 groups, PA, PB, PC and PD. Each pin of the 50 pins is independent and has the corresponding register bits to control the pin mode function and data.
Page 174: Block Diagram
ISD91500 Technical Reference Manual 5.5.3 Block Diagram Control Registers PA[15:0] PB[1:0] PA[15:0] PC[15:0] Control Register PD[15:0] PB[1:0] Control Register PC[15:0] Control Register PD[15:0] Control Register Interrupt, Wake-up Event Detector GPIO_INT Figure 5.5-1 GPIO Controller Block Diagram 5.5.4 Functional Description 5.5.4.1 Input Mode For Px_MODEn = 00’b the GPIO Px[n] pin is in Input mode, and the pin will be in tri-state (high...
Page 175: Figure 5.5-2 Push-Pull Output
ISD91500 Technical Reference Manual Port Pin Port Pin Port Latch Data Port Latch Data Input Data Input Data Figure 5.5-2 Push-Pull Output 5.5.4.3 Open-Drain mode explanation For Px_MODEn = 10’b the GPIO Px[n] pin is in Open-Drain mode. If the bit value in the corresponding bit Px_DOUT[n] is “0”, the pin drive a “low” output on the pin.
Page 176: Register Map
ISD91500 Technical Reference Manual 5.5.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value GPIO Base Address: GPIO_BA = 0x5000_4000 PA_MODE GPIO_BA+0x000 R/W GPIO PA Pin I/O Mode Control 0x0000_0000...
Page 177 ISD91500 Technical Reference Manual PBn_PDIO GPIO_BA+0x840+(0x04*n) R/W GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1 PCn_PDIO GPIO_BA+0x880+(0x04*n) R/W GPIO PC.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 PDn_PDIO GPIO_BA+0x8C0+(0x04*n) R/W GPIO PD.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 Note: Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
Page 178: Register Description
ISD91500 Technical Reference Manual 5.5.6 Register Description GPIO Port [A/B/C/D] I/O Mode Control (Px_MODE) Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 GPIO PA Pin I/O Mode Control 0x0000_0000 PB_MODE GPIO_BA+0x040 GPIO PB Pin I/O Mode Control 0x0000_0000 PC_MODE GPIO_BA+0x080 GPIO PC Pin I/O Mode Control...
Page 179 ISD91500 Technical Reference Manual GPIO Port [A/B/C/D] Data Output Value (Px_DOUT)  Register Offset Description Reset Value PA_DOUT GPIO_BA+0x008 GPIO PA Data Output Value 0x0000_FFFF PB_DOUT GPIO_BA+0x048 GPIO PB Data Output Value 0x0000_0003 PC_DOUT GPIO_BA+0x088 GPIO PC Data Output Value...
Page 180 ISD91500 Technical Reference Manual GPIO Port [A/B/C/D] Pin Value (Px _PIN) Register Offset Description Reset Value PA_PIN GPIO_BA+0x010 GPIO PA Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 GPIO PB Pin Value 0x0000_00XX PC_PIN GPIO_BA+0x090 GPIO PC Pin Value 0x0000_XXXX PD_PIN GPIO_BA+0x0D0 GPIO PD Pin Value...
Page 181 ISD91500 Technical Reference Manual GPIO Port [A/B/C/D] Interrupt Mode Control (Px _INTTYPE) Register Offset Description Reset Value PA_INTTYPE GPIO_BA+0x018 GPIO PA Interrupt Trigger Type 0x0000_0000 PB_INTTYPE GPIO_BA+0x058 GPIO PB Interrupt Trigger Type 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 GPIO PC Interrupt Trigger Type...
Page 182 ISD91500 Technical Reference Manual GPIO Port [A/B/C/D] Interrupt Enable Control (Px _INTEN) Register Offset Description Reset Value PA_INTEN GPIO_BA+0x01C GPIO PA Interrupt Enable 0x0000_0000 PB_INTEN GPIO_BA+0x05C GPIO PB Interrupt Enable 0x0000_0000 PC_INTEN GPIO_BA+0x09C GPIO PC Interrupt Enable 0x0000_0000 PD_INTEN GPIO_BA+0x0DC...
Page 183 ISD91500 Technical Reference Manual Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set “1” also enables the pin wake-up function.
Page 184 ISD91500 Technical Reference Manual GPIO Port [A/B/C/D] Interrupt Source Flag(Px _INTSRC) Register Offset Description Reset Value PA_INTSRC GPIO_BA+0x020 GPIO PA Interrupt Source Flag 0x0000_0000 PB_INTSRC GPIO_BA+0x060 GPIO PB Interrupt Source Flag 0x0000_0000 PC_INTSRC GPIO_BA+0x0A0 GPIO PC Interrupt Source Flag 0x0000_0000...
Page 185 ISD91500 Technical Reference Manual GPIO Px.n Pin Data Input/Output Register (Pxn_PDIO) Register Offset Description Reset Value PAn_PDIO GPIO_BA+0x800+(0x04*n) GPIO PA.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 PBn_PDIO GPIO_BA+0x840+(0x04*n) GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1 PCn_PDIO GPIO_BA+0x880+(0x04*n) GPIO PC.n Pin Data Input/Output Register 0x0000_000X n=0,1..15...
Page 186: Pwm Generator And Capture Timer (Pwm)
ISD91500 Technical Reference Manual PWM Generator and Capture Timer (PWM) 5.6.1 Overview This device has 2 sets of PWM timers. Each PWM timer consists of 1 prescaler, 1 clock divider, 1 clock selector with 5 input sources, one 16-bit counter, and four 16-bit comparators.
Page 187: Block Diagram
ISD91500 Technical Reference Manual 5.6.3 Block Diagram The following figures illustrate the architecture of the PWM0/1 generator. CMP (PWM_CAPDAT0[15:0]) CLKDIV (PWM_CLKDIV[2:0]) PWM_CH0 16-bit Control Logic Counter 8-bit PWM_CLK DZEN0 Prescaler (PWM_CTL[4]) 1/16 Dead Zone Generator PWM_CH1 Control Logic DZI0 PWM_CLKPSC[23:16])
Page 188: Functional Description
ISD91500 Technical Reference Manual 5.6.4 Functional Description 5.6.4.1 PWM-Timer Operation Basic Timer operation Counter Timer output CMP : 1 CMP : 0 CNR : 3 CNR : 3 Auto reload : 1 Auto-load Auto-load Timer enable Figure 5.6-3 PWM Timer Operation Timing 5.6.4.2...
Page 189: Figure 5.6-4 Pwm Controller Output Duty Ratio
ISD91500 Technical Reference Manual Write Write CMR=50 Write CMR=0 CMR=100 1 PWM cycle = 151 1 PWM cycle = 151 1 PWM cycle = 151 Modulate PWM controller ouput duty ratio(CNR = 150) Figure 5.6-4 PWM Controller Output Duty Ratio.
Page 190 ISD91500 Technical Reference Manual Setup prescaler (PWM_CLKPSC) Setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and PWM timer off (PWM_CTL) Setup comparator registers (PWM_CMPDATn) to set PWM duty cycle. Setup PWM down-counter register (PWM_PERIOD) to set PWM period. Setup interrupt enable register (PWM_INTEN)
Page 191: Figure 5.6-6 Capture Operation Timing
ISD91500 Technical Reference Manual PWM Counter Reload Reload Reload (If CNRx = 8) Capture Input x CAPENx CFLRx CRLRx Clear by S/W Clear by S/W Clear by S/W CAPIFx Set by H/W Set by H/W Set by H/W Clear by S/W...
Page 192: Register Map
ISD91500 Technical Reference Manual 5.6.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value PWM Base Address: PWMx_BA = 0x4004_0000+0x1_0000*x x= 0, 1 PWM_CLKPSC...
Page 193: Register Description
ISD91500 Technical Reference Manual 5.6.6 Register Description PWM Pre-Scale Register (PWM_CLKPSC)  Register Offset Description Reset Value PWM_CLKPSC PWMx_BA+0x000 PWM Prescaler Register 0x0000_0000 DZI1 DZI0 Reserved CLKPSC Bits Description Dead Zone Interval Register 1 [31:24] DZI1 These 8 bits determine dead zone length.
Page 194 ISD91500 Technical Reference Manual PWM Clock Select Register (PWM_CLKDIV) Register Offset Description Reset Value PWM_CLKDIV PWMx_BA+0x004 PWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKDIV Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 195 ISD91500 Technical Reference Manual PWM Control Register (PWM_CTL) Register Offset Description Reset Value PWM_CTL PWMx_BA+0x008 PWM Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DTEN1 DTEN0 CNTMODE PINV Reserved CNTEN Bits Description [31:6] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 196 ISD91500 Technical Reference Manual PWM Period Register (PWM_PERIOD) Register Offset Description Reset Value PWM_PERIOD PWMx_BA+0x00C PWM Period Register 0x0000_0000 Reserved Reserved PERIOD PERIOD Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 197 ISD91500 Technical Reference Manual PWM Comparator Register 3-0 (PWM_CMPDAT3-0) Register Offset Description Reset Value PWM_CMPDAT0 PWMx_BA+0x010 PWM Comparator Register 0 0x0000_0000 PWM_CMPDAT1 PWMx_BA+0x01C PWM Comparator Register 1 0x0000_0000 PWM_CMPDAT2 PWMx_BA+0x028 PWM Comparator Register 2 0x0000_0000 PWM_CMPDAT3 PWMx_BA+0x034 PWM Comparator Register 3...
Page 198 ISD91500 Technical Reference Manual PWM Counter Register (PWM _CNT) Register Offset Description Reset Value PWM_CNT PWMx_BA+0x014 PWM Counter Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 199 ISD91500 Technical Reference Manual PWM Interrupt Enable Register (PWM _INTEN) Register Offset Description Reset Value PWM_INTEN PWMx_BA+0x040 PWM Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved PIEN Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 200 ISD91500 Technical Reference Manual PWM Interrupt Flag Register (PWM _INTSTS) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0x044 PWM Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 201 ISD91500 Technical Reference Manual Capture Control Register (PWM_CAPCTL) Register Offset R/W Description Reset Value PWM_CAPCTL PWMx_BA+0x050 R/W Capture Control Register 0x0000_0000 Reserved Reserved Reserved CFLIF CRLIF Reserved CAPIF CAPEN CFLIEN CRLIEN CAPINV Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 202 ISD91500 Technical Reference Manual Rising Latch Interrupt Enable ON/OFF 0 = Disable rising latch interrupt. CRLIEN 1 = Enable rising latch interrupt. When enabled, capture block generates an interrupt on rising edge of input. Inverter ON/OFF CAPINV 0 = Inverter OFF.
Page 203 ISD91500 Technical Reference Manual Capture Rising Latch Register (PWM _RCAPDAT) Register Offset R/W Description Reset Value PWM_RCAPDAT PWMx_BA+0x058 Capture Rising Latch Register 0x0000_0000 Reserved Reserved RCAPDAT RCAPDAT Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 204 ISD91500 Technical Reference Manual Capture Falling Latch Register (PWM _FCAPDAT) Register Offset R/W Description Reset Value PWM_FCAPDAT PWMx_BA+0x05C Capture Falling Latch Register 0x0000_0000 Reserved Reserved FCAPDAT FCAPDAT Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 205 ISD91500 Technical Reference Manual PWM Output and Capture Input Enable Register (PWM_PCEN) Register Offset R/W Description Reset Value PWM_PCEN PWMx_BA+0x07C R/W PWM Output and Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved CAPINEN Reserved POEN3 POEN2 POEN1 POEN0 Bits Description...
Page 206 ISD91500 Technical Reference Manual Feb. 21, 2023 Page 206 of 500 Rev 2.3...
Page 207: Serial Peripheral Interface (Spi)
ISD91500 Technical Reference Manual Serial Peripheral Interface (SPI) 5.7.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional interface. This device contains two SPI controller performing a serial-to-parallel conversion of data received from an external device, and a parallel-to-serial conversion of data transmitted to an external device.
Page 208: Block Diagram
ISD91500 Technical Reference Manual 5.7.3 Block Diagram Clock Generator SPI_SCLK SPI_SSB0 (32-bits) Status/Control Register SPI_SSB1 Core Logic SPI_MOSI0 SPI_MOSI1 TX FIFO/ TX Bufer/ Shifter PDMA Shifter Control SPI_MISO0 RX FIFO/ RX Bufer/ Shifter SPI_MISO1 Shifter Figure 5.7-1 SPI Block Diagram 5.7.4...
Page 209: Figure 5.7-2 Spi Master Mode Application Block Diagram
ISD91500 Technical Reference Manual SCLK SCLK MISO MISO Slave 0 SPI Controller MOSI MOSI Master SSB0 SSB1 SCLK MISO Slave 1 MOSI Figure 5.7-2 SPI Master Mode Application Block Diagram SCLK SCLK MISO MISO Master SPI Controller MOSI MOSI Slave...
Page 210 ISD91500 Technical Reference Manual automatically and output to SPI_SSB0 and SPI_SSB1 pins according to registers SPI_SSCTL.SS[0] and SPI_SSCTL.SS[1]. In this mode, SPI controller will assert SSB when transaction is triggered and de-assert when data transfer is finished. If the SPI_SSCTL.AUTOSS bit is cleared, the slave select output signals are asserted and de-asserted by manual setting and clearing the related bits in the SPI_SSCTL.SS[1:0] register.
Page 211: Figure 5.7-4 Word Sleep Suspend Mode
ISD91500 Technical Reference Manual 5.7.4.11 Word Suspend The four bit field SUSPITV (SPI_CTL[7:4]) provides a configurable suspend interval of 0.5 ~ 15.5 SPI clock periods, between two successive transaction words in Master mode. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
Page 212: Figure 5.7-6 Byte Order In Memory
ISD91500 Technical Reference Manual transmission out the SPI port. The CortexM0 stores data in a little endian format; that is the LSB of a multi-byte word or half-word are stored first in memory. Consider how the CortexM0 stores the following arrays in memory: 1.
Page 213: Figure 5.7-7 Byte Order In Memory
ISD91500 Technical Reference Manual unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; unsigned int *uiSPI_DATA = (unsigned int *)ucSPI_DATA[]; RAM Address RAM Contents Byte0 Byte1 Byte2 Byte3 0x20000014 Byte0 Byte1 Byte2 Byte3 0x20000010 0x08 0x07 0x06 0x05 0x2000000c...
Page 214 ISD91500 Technical Reference Manual In Slave mode, if the transmit/ receive bit count mismatch with the DWIDTH when the slave select line goes to inactive state, the Slave mode error 0, SLVBEIF, SPI_STATUS[6], will be set to 1. The SPI controller will issue an interrupt if the SLVBCEIEN, SPI_SSCTL[8], is set to 1.
Page 215: Figure 5.7-8 Bit Sequence Of Dual Output Mode
ISD91500 Technical Reference Manual three pins, SPICLK, SPI_MISO0, and SPI_MOSI0, are required to communicate with a SPI master. The SPI_SS pin can be configured as a GPIO. When the SLV3WIRE bit is set to 1, the SPI slave will be ready to transmit/receive data after the SPIEN bit is set to 1.
Page 216: Figure 5.7-9 Bit Sequence Of Dual Input Mode
ISD91500 Technical Reference Manual SPI_SS SPI_CLK SPI_MOSI 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 Master output Input Slave input SPI_MISO 7 5 3 1 7 5 3 1...
Page 217: Figure 5.7-11 Bit Sequence Of Quad Output Mode
ISD91500 Technical Reference Manual SPI_SS SPI_CLK DI (IO SPI_MOSI0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 Master output Output Slave input SPI_MISO0 5 1 5 1 5 1...
Page 218: Figure 5.7-12 Fifo Mode Block Diagram
ISD91500 Technical Reference Manual Write SPI_TX Buffer MOSI Pin in Master Mode Transmit Buffer 0 Transmit buffer 1 Transmit buffer 2 MISO Pin in Slave Mode Transmit buffer n MISO Pin in Master Mode Receive buffer n Receive buffer 2...
Page 219: Figure 5.7-13 Spi Timing In Master Mode
ISD91500 Technical Reference Manual When the Slave select is active and the value of SLVTOCNT is not 0, the Slave time-out counter in the SPI controller logic will start after the serial clock input. This counter will be clear after one transaction done or the SLVTOCNT is set to 0.
Page 220: Figure 5.7-14 Spi Timing In Master Mode (Alternate Phase Of Spiclk)
ISD91500 Technical Reference Manual SSLVL=1 SPI_SS SSLVL=0 CLKP=0 SPICLK CLKP=1 MOSI Tx0[1] Tx0[2] Tx0[3] Tx0[4] Tx0[5] Tx0[6] Tx0[0] Tx0[7] MISO Rx0[1] Rx0[2] Rx0[3] Rx0[4] Rx0[5] Rx0[6] Rx0[0] Rx0[7] Master Mode: SPI_CTL.SLVAE=0, SPI_CTL.LSB=1, SPI_CTL.TXCNT=0x0, SPI_CTL.DWIDTH=0x08 1. SPI_CTL.CLKP=0,SPI_CTL.TXNEG=0, SPI_CTL.RXNEG=1 or 2. SPI_CTL.CLKP=1, SPI_CTL.TXNEG=1, SPI_CTL.RXNEG=0 Figure 5.7-14 SPI Timing in Master Mode (Alternate Phase of SPICLK)
Page 221: Figure 5.7-16 Spi Timing In Slave Mode (Alternate Phase Of Spiclk)
ISD91500 Technical Reference Manual SSLVL=1 SPI_SS SSLVL=0 CLKP=0 SPICLK CLKP=1 MISO Tx0[1] Tx0[7] Tx1[0] Tx1[6] Tx0[0] Tx1[7] MOSI Rx0[1] Rx0[7] Rx1[0] Rx1[6] Rx0[0] Rx1[7] Master Mode: SPI_CTL.SLVAE=1, SPI_CTL.LSB=1, SPI_CTL.TXCNT=0x1, SPI_CTL.DWIDTH=0x08 1. SPI_CTL.CLKP=0,SPI_CTL.TXNEG=0, SPI_CTL.RXNEG=1 or 2. SPI_CTL.CLKP=1, SPI_CTL.TXNEG=1, SPI_CTL.RXNEG=0 Figure 5.7-16 SPI Timing in Slave Mode (Alternate Phase of SPICLK) Feb.
Page 222 ISD91500 Technical Reference Manual 5.7.4.19 SPI Configuration Examples  Example 1, SPI controller is set as a master to access an off-chip slave device with following specifications:  Data bit latched on positive edge of serial clock  Data bit driven on negative edge of serial clock ...
Page 223 ISD91500 Technical Reference Manual To configure the SPI interface to the above specifications perform the following steps: 1) Configure the SPI_SSCTL register. SPI_SSCTL.SSACTPOL=1 for active high slave select, SPI_SSCTL.SS_LTRIG=1 for level sensitive trigger. 2) Configure the SPI_CTL register. Set SPI_CTL.SLAVE=1 for slave mode, set SPI_CTL.CLKPOL=1 for SCLK polarity idle high, set SPI_CTL.TXNEG=1 so that data changes on falling edge of SCLK,...
Page 224: Register Map
ISD91500 Technical Reference Manual 5.7.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPIx_BA = 0x4003_0000 + (0x1000 * x) x=0,1 SPI_CTL SPIx_BA + 0x00 Control and Status Register...
Page 225: Register Description
ISD91500 Technical Reference Manual 5.7.6 Register Description SPI Control and Status Register (SPI_CTL) Register Offset Description Reset Value SPI_CTL SPIx_BA + 0x00 Control and Status Register 0x0000_0034 Reserved RXMODEEN RXTCNTEN QUADIOEN DUALIOEN QDIODIR REORDER SLAVE Reserved Reserved DWIDTH SUSPITV CLKP...
Page 226 ISD91500 Technical Reference Manual Byte Reorder Function Enable 0 = Byte reorder function Disabled. 1 = Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV.
Page 227 ISD91500 Technical Reference Manual Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3.
Page 228 ISD91500 Technical Reference Manual SPI Divider Register (SPI_CLKDIV) Register Offset Description Reset Value SPI_CLKDIV SPIx_BA + 0x04 Clock Divider Register (Master Only) 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 229 ISD91500 Technical Reference Manual SPI Slave Select Register (SPI_SSCTL) Register Offset Description Reset Value SPI_SSCTL SPIx_BA + 0x08 Slave Select Register 0x0000_0000 SLVTOCNT SLVTOCNT Reserved SSINAIEN SSACTIEN Reserved SLVUDRIEN SLVBCEIEN Reserved SLVTORST SLVTOIEN SLV3WIRE AUTOSS SSLVL Bits Description Slave Mode Time-out Period...
Page 230 ISD91500 Technical Reference Manual Slave Mode Time-out Interrupt Enable SLVTOIEN 0 = Slave mode time-out interrupt Disabled. 1 = Slave mode time-out interrupt Enabled. Slave 3-wire Mode Enable This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI.
Page 231 ISD91500 Technical Reference Manual SPI DMA Control Register (SPI_PDMACTL) Register Offset R/W Description Reset Value SPI_PDMACTL SPIx_BA + 0x0C R/W SPI PDMA Control Register 0x0000_0000 Reserved Reserved Reserved DIVIDER PDMARST RXPDMAEN TXPDMAEN Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 232 ISD91500 Technical Reference Manual SPI FIFO Control Register (SPI_FIFOCTL) Register Offset Description Reset Value SPI_FIFOCTL SPIx_BA + 0x10 FIFO Control/Status Register 0x4400_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXUDFIEN TXUDFPOL RXOVIEN RXTOIEN TXTHIEN RXTHIEN TXRST RXRST Bits Description [31] Reserved Reserved.
Page 233 ISD91500 Technical Reference Manual Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
Page 234 ISD91500 Technical Reference Manual Clear Transmit FIFO Buffer 0 = No effect. 1 = Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set TXRST to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1.
Page 235 ISD91500 Technical Reference Manual SPI Status Register (SPI_STATUS) Register Offset R/W Description Reset Value SPI_STATUS SPIx_BA + 0x14 R/W Status Register 0x0005_0110 TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL TXEMPTY SPIENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY SLVURIF SLVBEIF SLVTOIF...
Page 236 ISD91500 Technical Reference Manual Transmit FIFO Buffer Empty Indicator (Read Only) [16] TXEMPTY 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty. SPI Enable Bit Status (Read Only) 0 = Indicate the transmit control bit is disabled.
Page 237 ISD91500 Technical Reference Manual Slave Time-out Interrupt Status (Read Only) When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI_SSCTL.SLVTOCNT, during before one transaction done, the slave...
Page 238 ISD91500 Technical Reference Manual SPI Receive Transaction Count (SPI_RXTSNCNT) Register Offset Description Reset Value SPI_RXTSNCNT SPIx_BA + 0x18 Receive Transaction Count Register 0x0000_0000 Reserved Reserved RXTSNCNT RXTSNCNT Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 239 ISD91500 Technical Reference Manual SPI Data Transmit Register (SPI_TX) Register Offset Description Reset Value SPI_TX SPIx_BA + 0x20 FIFO Data Transmit Register 0x0000_0000 Bits Description Data Transmit Register A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number [31:0] of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
Page 240 ISD91500 Technical Reference Manual SPI Data Receive Register (SPI_RX) Register Offset Description Reset Value SPI_RX SPIx_BA + 0x30 FIFO Data Receive Register 0x0000_0000 Bits Description Data Receive Register [31:0] A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS.
Page 241: I 2 S Controller (I 2 S)
ISD91500 Technical Reference Manual S Controller (I 5.8.1 Overview The I2S controller consists of I2S protocol to interface with external audio CODEC. There is one set of I2S controller, with two 16-level depth FIFO for reading path and writing path respectively and is capable of handling 8/16/24/32 bits audio data sizes.
Page 242: Functional Description
ISD91500 Technical Reference Manual 5.8.4 Functional Description 5.8.4.1 S Clock The I2S controller has five clock sources selected by I2S0SEL (CLK_CLKSEL1[22:20]). The I2S clock rate must be slower than or equal to system clock rate. XCLK MCLKI HIRC PCLK PLLFOUT...
Page 243: Figure 5.8-4 Slave Mode Interface Block Diagram
ISD91500 Technical Reference Manual I2S_MCLK IS2_BCLK I2S_LRCLK Master Slave I2S_DO I2S_DI Figure 5.8-4 Slave mode Interface Block Diagram 5.8.4.3 S Operation The I2S controller supports MSB-justified, LSB-justified, and I2S Philips standard data format. The I2S_LRCLK signal indicates which audio channel is in transferring. The bit count of an audio channel is defined by CHWIDTH (I2S0_CTL0[29:28]), and the bit-width of data word in an audio channel is determined by DATWIDTH (I2S0_CTL0[5:4]).
Page 244: Figure 5.8-7 I 2 S Data Format Timing Diagram (Format = 0X0 ; Chwidth≦Datwidth)
ISD91500 Technical Reference Manual DATWIDTH) , transmitting data are read at rising edge of I2S_BCLK and sent out at falling edge of I2S_BCLK in I2S protocol. In I2S data format, the MSB is sent and latched at the next falling edge of I2S_BCLK cycle after the transition of I2S_LRCLK.
Page 245: Figure 5.8-10 Standard Pcm Audio Timing Diagram (Format = 0X4 ; Chwidth≦Datwidth)
ISD91500 Technical Reference Manual an audio sample (or audio frame) and it is always indicated by the rising edge of the pulse. Therefore, the I2S_LRCLK in PCM protocol may be also called “frame start” or “frame sync” signal. In master...
Page 246 ISD91500 Technical Reference Manual 5.8.4.4 Zero Crossing When playing the audio by I2S controller, the output transmitting data comes from the memory by PDMA or by CPU. However, there may be some pop noise which induces the uncomfortable hearing if the playing sound volume is changed greatly by user.
Page 247: Figure 5.8-13 I 2 S Interrupts
ISD91500 Technical Reference Manual CH0ZCIEN CH0ZCIF CH1ZCIEN CH1ZCIF TXTHIEN I2STXINT TXTHIF TXOVFIEN TXOVIF TXUDFIEN I2SINT TXUDIF RXTHIEN RXTHIF RXOVFIEN I2SRXINT RXOVIF RXUDFIEN RXUDIF Figure 5.8-13 I S Interrupts FIFO Operation 5.8.4.7 In 2-channel I2S or PCM protocol, the bit-width of audio data in a channel block can be 8, 16, 24, or 32 bits.
Page 248: Figure 5.8-14 Fifo Contents For Various 2-Channel Audio Modes
ISD91500 Technical Reference Manual Mono 8-bit data mode Stereo 8-bit data mode, ORDER (I2S_CTL0[7]) = 0 LEFT+1 RIGHT+1 LEFT RIGHT Stereo 8-bit data mode, ORDER (I2S_CTL0[7]) = 1 RIGHT+1 LEFT+1 RIGHT LEFT Mono 16-bit data mode Stereo 16-bit data mode, ORDER (I2S_CTL0[7]) = 0...
Page 249: Register Map
ISD91500 Technical Reference Manual 5.8.5 Register Map R: Read only, W: Write only, R/W: Both read and write Register Offset Description Reset Value I2S0 Base Address I2S0_BA = 0x4009_0000 I2S0_CTL0 I2S0_BA+0x00 S0 Control Register 0 0x0000_0000 I2S0_CTL1 I2S0_BA+0x20 S0 Control Register 1...
Page 250: Register Description
ISD91500 Technical Reference Manual 5.8.6 Register Description I2S0 Control Register 0 (I2S0_CTL0) Register Offset Description Reset Value I2S0_CTL0 I2S0_BA+0x00 S0 Control Register 0 0x0000_0000 Reserved CHWIDTH Reserved FORMAT RXLCH Reserved RXPDMAEN TXPDMAEN RXFBCLR TXFBCLR FLZCDEN FRZCDEN MCLKEN Reserved SLAVE ORDER...
Page 251 ISD91500 Technical Reference Manual Receive PDMA Enable Control [21] RXPDMAEN 0 = Receiver PDMA function Disabled. 1 = Receiver PDMA function Enabled. Transmit PDMA Enable Control [20] TXPDMAEN 0 = Transmit PDMA function Disabled. 1 = Transmit PDMA function Enabled.
Page 252 ISD91500 Technical Reference Manual Stereo Data Order in FIFO In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
Page 253 ISD91500 Technical Reference Manual I2S0 Control Register 1 (I2S0_CTL1) Register Offset Description Reset Value I2S0_CTL1 I2S0_BA+0x20 S0 Control Register 1 0x0000_0000 Reserved PB16ORD PBWIDTH Reserved RXTH Reserved TXTH Reserved CH1ZCEN CH0ZCEN Bits Description Reserved. Any values read should be ignored. When writing to this field always write with...
Page 254 ISD91500 Technical Reference Manual Receive FIFO Threshold Level 0000 = 1 data word in receive FIFO. 0001 = 2 data words in receive FIFO. 0010 = 3 data words in receive FIFO. [19:16] RXTH …. 1110 = 15 data words in receive FIFO.
Page 255 ISD91500 Technical Reference Manual I2S0 Clock Divider (I2S0_CLKDIV) Register Offset Description Reset Value I2S0_CLKDIV I2S0_BA+0x04 S0 Clock Divider Register 0x0000_0000 Reserved Reserved BCLKDIV BCLKDIV Reserved MCLKDIV Bits Description [31:18] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 256 ISD91500 Technical Reference Manual I2S0 Interrupt Enable Register (I2S0_IEN) Register Offset Description Reset Value I2S0_IEN I2S0_BA+0x08 S0 Interrupt Enable Register 0x0000_0000 Reserved Reserved CH1ZCIEN CH0ZCIEN Reserved TXTHIEN TXOVFIEN TXUDFIEN Reserved RXTHIEN RXOVFIEN RXUDFIEN Bits Description [31:18] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 257 ISD91500 Technical Reference Manual Transmit FIFO Underflow Interrupt Enable Control 0 = Interrupt Disabled. TXUDFIEN 1 = Interrupt Enabled. Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S0_STATUS0[16]) flag is set to 1. [7:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 258 ISD91500 Technical Reference Manual I2S0 Status Register 0 (I2S0_STATUS0) Register Offset Description Reset Value I2S0_STATUS0 I2S0_BA+0x0C R/W S0 Status Register 0 0x0014_1000 Reserved Reserved TXEMPTY TXFULL TXTHIF TXOVIF TXUDIF Reserved RXEMPTY RXFULL RXTHIF RXOVIF RXUDIF Reserved DATACH I2STXINT I2SRXINT I2SINT...
Page 259 ISD91500 Technical Reference Manual Transmit FIFO Underflow Interrupt Flag 0 = No underflow. 1 = Underflow. [16] TXUDIF Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
Page 260 ISD91500 Technical Reference Manual S Transmit Interrupt (Read Only) I2STXINT 0 = No transmit interrupt. 1 = Transmit interrupt. S Receive Interrupt (Read Only) I2SRXINT 0 = No receive interrupt. 1 = Receive interrupt. S Interrupt Flag (Read Only) 0 = No I S interrupt.
Page 261 ISD91500 Technical Reference Manual I2S0 Status Register 1 (I2S0_STATUS1) Register Offset Description Reset Value I2S0_STATUS1 I2S0_BA+0x24 R/W S0 Status Register 1 0x0000_0000 Reserved Reserved RXCNT Reserved TXCNT Reserved CH1ZCIF CH0ZCIF Bits Description [31:21] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 262 ISD91500 Technical Reference Manual Channel1 Zero-cross Interrupt Flag It indicates channel1 next sample data sign bit is changed or all data bits are zero. 0 = No zero-cross in channel1. CH1ZCIF 1 = Channel1 zero-cross is detected. Note 1: Write 1 to clear this bit to 0.
Page 263 ISD91500 Technical Reference Manual I2S0 Transmit FIFO (I2S0_TXFIFO) Register Offset Description Reset Value I2S0_TXFIFO I2S0_BA+0x10 S0 Transmit FIFO Register 0x0000_0000 TXFIFO TXFIFO TXFIFO TXFIFO Bits Description Transmit FIFO Bits [31:0] TXFIFO S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit.
Page 264 ISD91500 Technical Reference Manual I2S0 Receive FIFO (I2S0_RXFIFO) Register Offset Description Reset Value I2S0_RXFIFO I2S0_BA+0x14 S0 Receive FIFO Register 0x0000_0000 RXFIFO RXFIFO RXFIFO RXFIFO Bits Description Receive FIFO Bits [31:0] RXFIFO S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO.
Page 265: Timer Controller (Tmr)
ISD91500 Technical Reference Manual Timer Controller (TMR) 5.9.1 Overview The timer controller includes three timers, Timer0, Timer1 and Timer2 which allow user to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information.
Page 266: Functional Description
ISD91500 Technical Reference Manual TMRx_S TMRx_EN HIRC LIRC TMRx_CLK TMx(GPIO) PCLK Note: x means 0,1,2 Figure 5.9-2 Clock Source of Timer Controller 5.9.4 Functional Description Timer Interrupt Flag 5.9.4.1 In timer mode, Timer controller can generate the interrupt: Timer Interrupt: TIF (TIMERx_INTSTS[0]) bit will be set when timer counter value CNT (TIMERx_CNT[15:0]) matches the timer compared value CMPDAT (TIMERx_CMP[15:0]);...
Page 267: Figure 5.9-3 Continuous Counting Mode
ISD91500 Technical Reference Manual 5.9.4.5 Continuous Counting Mode Writing 0b11 into TIMERx_CTL[28:27] selects continuous counting mode. Under continuous counting mode, timer starts up counting once CNTEN (TIMERx_CTL[30]) is enabled. When CNT (TIMERx_CNT[15:0]) value reaches CMPDAT (TIMERx_CMP[15:0]) value, the TIF (TIMERx_INTSTS[0]) will be set to 1, hence a timer interrupt generated if enabled, and counting continues.
Page 268: Register Map
ISD91500 Technical Reference Manual 5.9.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TMR Base Address: TMR_BA=0x4001_0000 TIMER0_CTL TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER0_CMP TMR_BA+0x04 Timer0 Compare Register...
Page 269: Register Description
ISD91500 Technical Reference Manual 5.9.6 Register Description Timer Control Register (TIMERx_CTL) Register Offset Description Reset Value TIMER0_CTL TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER1_CTL TMR_BA+0x20 Timer1 Control and Status Register 0x0000_0005 TIMER2_CTL TMR_BA+0x40 Timer2 Control and Status Register 0x0000_0005...
Page 270 ISD91500 Technical Reference Manual Counter Reset Bit Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0. [26] RSTCNT 0 = No effect. 1 = Reset Timer’s pre-scale counter, internal 16-bit up-counter and CNTEN bit.
Page 271 ISD91500 Technical Reference Manual Timer Compare Register (TIMERx_CMP) Register Offset Description Reset Value TIMER0_CMP TMR_BA+0x04 Timer0 Compare Register 0x0000_0000 TIMER1_CMP TMR_BA+0x24 Timer1 Compare Register 0x0000_0000 TIMER2_CMP TMR_BA+0x44 Timer2 Compare Register 0x0000_0000 Reserved Reserved CMPDAT CMPDAT Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 272 ISD91500 Technical Reference Manual Timer Interrupt Status Register (TIMERx_INTSTS) Register Offset Description Reset Value TIMER0_INTSTS TMR_BA+0x08 Timer0 Interrupt Status Register 0x0000_0000 TIMER1_INTSTS TMR_BA+0x28 Timer1 Interrupt Status Register 0x0000_0000 TIMER2_INTSTS TMR_BA+0x48 Timer2 Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits...
Page 273 ISD91500 Technical Reference Manual Timer Data Register (TIMERx_CNT) Register Offset R/W Description Reset Value TIMER0_CNT TMR_BA+0x0C Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR_BA+0x2C Timer1 Data Register 0x0000_0000 TIMER2_CNT TMR_BA+0x4C Timer2 Data Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 274 ISD91500 Technical Reference Manual IR Carrier Output Control Register (IR_CTL) Register Offset Description Reset Value IR_CTL TMR_BA+0x34 IR Carrier Output Control Register 0x0000_0000 Reserved Reserved Reserved Reserved IRCEN NONCS Timer1 time-out signal is used to toggle IROUT output. Before IR carrier output is enabled, user needs to setup Timer1 according to output frequency of IR carrier.
Page 275: Watchdog Timer (Wdt)
ISD91500 Technical Reference Manual 5.10 Watchdog Timer (WDT) 5.10.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset if system runs into an unknown state. This prevents system from hanging for an indefinite period of time.
Page 276: Table 5.10-1 Watchdog Timeout Interval Selection
ISD91500 Technical Reference Manual INTEN(WDT_CTL [6]) is set, in the meantime, a specified delay time follows the time-out event. User must set RSTCNT (WDT_CTL [0]) (Watchdog timer reset) high to reset the 19-bit WDT counter to prevent Watchdog timer reset before the delay time expires. RSTCNT ( WDT_CTL [0]) bit is auto cleared by hardware after WDT counter is reset.
Page 277: Register Map
ISD91500 Technical Reference Manual 5.10.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4000_4000 WDT_CTL WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Note: Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
Page 278: Register Description
ISD91500 Technical Reference Manual 5.10.6 Register Description Watchdog Timer Control Register (WDT_CTL) Register Offset Description Reset Value WDT_CTL WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Reserved Reserved Reserved TOUTSEL WDTEN INTEN Reserved RSTF RSTEN RSTCNT Bits Description [31:11] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 279 ISD91500 Technical Reference Manual Watchdog Time-Out Interrupt Enable (Write Protected) 0 = Disable the WDT time-out interrupt. INTEN 1 = Enable the WDT time-out interrupt. Note: This bit is writing protected. Refer to the SYS_REGLCTL. [5:4] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 280: I 2 C Serial Interface Controller (I 2 C)
ISD91500 Technical Reference Manual 5.11 I C Serial Interface Controller (I 5.11.1 Overview This device supports two I2C controller – I2C0 and I2C1. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 281: Figure 5.11-1 I2C Bus Timing
ISD91500 Technical Reference Manual Repeated STOP START STOP START HIGH HD;STA SU;STA SU;STO HD;DAT SU;DAT Figure 5.11-1 I2C Bus Timing The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit I2CEN in I2C_CTL should be set to '1'.
Page 282: Figure 5.11-3 Master Transmits Data To Slave
ISD91500 Technical Reference Manual SLAVE ADDRESS DATA DATA data transfer (n bytes + acknowledge) '0'(write) from master to slave A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition from slave to master P = STOP condition Figure 5.11-3 Master Transmits Data to Slave...
Page 283: Figure 5.11-6 Bit Transfer On The I2C Bus
ISD91500 Technical Reference Manual This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle.
Page 284 ISD91500 Technical Reference Manual and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted.
Page 285: Figure 5.11-8 Legend For The Following Four Figures
ISD91500 Technical Reference Manual Software's access to I2DAT with respect to "Expected next action": Last state (1) Data byte will be transmitted: A START has been Last action is done Software should load the data byte (to be transmitted) transmitted.
Page 286: Figure 5.11-9 Master Transmitter Mode
ISD91500 Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+W will be transmitted; ACK bit will be received. From Master/Receiver (B) SLA+W will be transmitted; ACK bit will be received.
Page 287: Figure 5.11-10 Master Receiver Mode
ISD91500 Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+R will be transmitted; ACK bit will be received. From Master/Transmitter (A) SLA+R has been transmitted; SLA+R has been transmitted;...
Page 288: Figure 5.11-11 Slave Transmitter Mode
ISD91500 Technical Reference Manual Set AA Own SLA+R has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+R has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Last data byte will be transmitted; Data byte will be transmitted;...
Page 289: Figure 5.11-12 Slave Receiver Mode
ISD91500 Technical Reference Manual Set AA Own SLA+W has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+W has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Data byte will be received; Data byte will be received;...
Page 290: Figure 5.11-13 Gc Mode
ISD91500 Technical Reference Manual Set AA Reception of the general call address and one or more data bytes; ACK has been return. Arbitration lost SLA+R/W as master; and address as SLA by general call; ACK has been return. (STA,STO,SI,AA)=(X,0,1,0) (STA,STO,SI,AA)=(X,0,1,1) Data byte will be received;...
Page 291 ISD91500 Technical Reference Manual 5.11.3.4 I C Protocol Registers The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL (control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL (Time-out counter register).
Page 292: Figure 5.11-14 I2C Data Shift Direction
ISD91500 Technical Reference Manual I2C Data Register: DATA.7 DATA.6 DATA.5 DATA.4 DATA.3 DATA.2 DATA.1 DATA.0 shifting direction Figure 5.11-14 I2C Data Shift Direction Control Register (I2C_CTL) The CPU can read from and write to this 8-bit field of I2C_CTL[7:0]. Two bits are affected by hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is cleared when a STOP condition is present on the bus.
Page 293: Figure 5.11-15 I2C Time-Out Count Block Diagram
ISD91500 Technical Reference Manual Clock Divided Register (I2C_CLKDIV) The data baud rate of I2C is determined by I2C_CLKDIV[7:0] register when SIO is in a master mode. It is not important when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize with any clock frequency up to 1M Hz from master I2C device.
Page 294: Register Map
ISD91500 Technical Reference Manual 5.11.4 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value I2C Base Address: I2Cx_BA = 0x4002_0000 + (0x1000 * x) x=0,1 I2C_CTL I2Cx_BA+0x00 I2C Control Register 0x0000_0000...
Page 295: Register Description
ISD91500 Technical Reference Manual 5.11.5 Register Description I2C Ccontrol Register (I2C_CTL) Register Offset Description Reset Value I2C_CTL I2Cx_BA+0x00 I2C Control Register 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 296 ISD91500 Technical Reference Manual Assert Acknowledge Control Bit When AA=1 prior to address or data received, an acknowledge (ACK - low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:. 1. A slave is acknowledging the address sent from master, 2.
Page 297 ISD91500 Technical Reference Manual I2C Data Register (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2Cx_BA+0x08 I2C DATA Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 298 ISD91500 Technical Reference Manual I2C Status Register (I2C_STATUS ) Register Offset Description Reset Value I2C_STATUS I2Cx_BA+0x0C I2C Status Register 0x0000_00F8 Reserved Reserved Reserved STATUS Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 299 ISD91500 Technical Reference Manual I2C Clock Divided Register (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2Cx_BA+0x10 I2C clock divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 300 ISD91500 Technical Reference Manual I2C Time-Out Ccounter Register (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2Cx_BA+0x14 I2C Time out control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 301 ISD91500 Technical Reference Manual I2C Slave Address Register (I2CADDRn) Register Offset Description Reset Value I2C_ADDR0 I2Cx_BA+0x04 I2C Slave address Register0 0x0000_0000 I2C_ADDR1 I2Cx_BA+0x18 I2C Slave address Register1 0x0000_0000 I2C_ADDR2 I2Cx_BA+0x1C I2C Slave address Register2 0x0000_0000 I2C_ADDR3 I2Cx_BA+0x20 I2C Slave address Register3...
Page 302 ISD91500 Technical Reference Manual I2C Slave Address Mask Register (I2CADMn) Register Offset Description Reset Value I2C_ADDRMSK0 I2Cx_BA+0x24 I2C Slave address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cx_BA+0x28 I2C Slave address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cx_BA+0x2C I2C Slave address Mask Register2 0x0000_0000 I2C_ADDRMSK3 I2Cx_BA+0x30...
Page 303: 12-Bit Analog-To-Digital Converter (Saradc)
ISD91500 Technical Reference Manual 5.12 12-bit Analog-to-Digital Converter (SARADC) 5.12.1 Overview This device contains one 12-bit successive approximation analog-to-digital converters (SARADC). SARADC can be programmed operation independently. SARADC has 12-channel external single- ended inputs. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode.
Page 304: Figure 5.12-1 Adc Controller Block Diagram
ISD91500 Technical Reference Manual VALID & OVERRUN PDMA request Digital Control Logics ADC_INT & ADC Clock Generator RSLT[13:0] Successive Approximations Register 12-bit DAC ADC0 ADC1 Analog Control Logics Comparator ADC11 Sample and Hold Reserved Reserved Analog Macro Figure 5.12-1 ADC Controller Block Diagram Feb.
Page 305: Functional Description
ISD91500 Technical Reference Manual 5.12.4 Functional Description 5.12.4.1 SARADC Inputs SARADC Input Pin Name AIN0 PA.0 AIN1 PA.1 AIN2 PA.2 AIN3 PA.3 AIN4 PA.4 AIN5 PA.5 AIN6 PA.6 AIN7 PA.7 AIN8 PA.8 AIN9 PA.9 AIN10 PA.10 AIN11 PA.11 5.12.4.2 SARADC Operation Procedure The A/D converter operates by successive approximation with 12-bit resolution.
Page 306: Figure 5.12-2 Saradc Clock Source
ISD91500 Technical Reference Manual SARADCSEL HIRC SARADCEN PCLK SARADC_CLK 1/(SARADCDIV+1) PLLFOUT Figure 5.12-2 SARADC Clock Source 5.12.4.4 Single Mode In single mode, A/D conversion is to be performed only once on the specified channel. The operations are as follows: The channel defined in CHSEQ0 is the channel to be converted.
Page 307: Figure 5.12-3 Continuous Scan On Selected Channels
ISD91500 Technical Reference Manual CSEQ4=F CSEQ0=4 CSEQ1=3 CSEQ2=4 CSEQ3=2 CSEQ0=4 CSEQ1=3 Channel Channel Channel Channel Channel Channel Interrupt Figure 5.12-3 Continuous Scan on Selected Channels 5.12.4.6 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels that are defined by CHSEQx bits in SARADC_CHSEQ0/ SARADC_CHSEQ1 register (14 channels maximum for SARADC).
Page 308: Figure 5.12-4 Single-Cycle Scan On Selected Channels
ISD91500 Technical Reference Manual CSEQ4=F CSEQ0=2 CSEQ1=4 CSEQ2=3 CSEQ3=4 Channel sample Result ADCDR0 ADCDR1 ADCDR2 ADCDR3 Single scan on channel 2, 4, 3 and 4 Figure 5.12-4 Single-Cycle Scan on selected Channels 5.12.4.7 Conversion Result Monitor SARADC controller provides two compare registers ADC_CMP0/1 to monitor specified channel conversion result from A/D conversion module (see figure below).
Page 309: Figure 5.12-6 A/D Controller Interrupt
ISD91500 Technical Reference Manual 5.12.4.8 Interrupt Sources The A/D converter generates a conversion end ADIF in SARADC_STATUS0 register upon the end of A/D conversion. If ADCIE bit in SARADC_CTL is set then conversion end interrupt request ADINT is generated. If ADCMPIE bit is enabled, when A/D conversion result meets setting in SARADC_CMPn register, monitor interrupt is generated, ADINT will be set also.
Page 310: Register Map
ISD91500 Technical Reference Manual 5.12.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value SARADC Base Address: SARADC_BA = 0x400E_0000 SARADC_DAT0 SARADC_BA+0x00 R SARADC Data Register for the channel defined in CHSEQ0...
Page 311: Register Description
ISD91500 Technical Reference Manual 5.12.6 Register Description SARADC Data Registers (SARADC_DATn) Register Offset R/W Description Reset Value SARADC_DAT0 SARADC_BA+0x00 R SARADC Data Register for the channel defined in CHSEQ0 0x0000_0000 SARADC_DAT1 SARADC_BA+0x04 R SARADC Data Register for the channel defined in CHSEQ1...
Page 312 ISD91500 Technical Reference Manual Valid Flag 0 = Data in RESULT are not valid. [17] VALID 1 = Data in RESULT are valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
Page 313 ISD91500 Technical Reference Manual SARADC Control Register (SARADC_CTL) Register Offset Description Reset Value SARADC_CTL SARADC_BA+0x3C R/W SARADC Control Register 0x0000_0040 Reserved Reserved Reserved ADCFM SWTRG OVRIE Reserved MUXEN DLYTRIM MUXSW PDMAEN OPMODE ADCIE ADCEN Bits Description [31:13] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 314 ISD91500 Technical Reference Manual Trim bit for SARADC internal conversion time. When higher level will have longer conversion time. 00 = Level 0 [7:6] DLYTRIM 01 = Level 1 10 = Level 2 11 = Level 3 Note: Suggest to set Level 3 for best SARADC performance.
Page 315 ISD91500 Technical Reference Manual SARADC Channel Sequence Register0 (SARADC_CHSEQ0) Register Offset Description Reset Value SARADC_CHSEQ0 SARADC_BA+0x40 R/W SARADC Channel Sequence Register0 0xFFFF_FFFF CHSEQ7 CHSEQ6 CHSEQ5 CHSEQ4 CHSEQ3 CHSEQ2 CHSEQ1 CHSEQ0 Bits Description Select Channel N As The 8 Conversion In Scan Sequence...
Page 316 ISD91500 Technical Reference Manual Select Channel N As The 1 Conversion In Scan Sequence One of the following channel is selected according to CHSEQ0. 0000 = ADC Channel 0. 0001 = ADC Channel 1. 0010 = ADC Channel 2. 0011 = ADC Channel 3.
Page 317 ISD91500 Technical Reference Manual SARADC Channel Sequence Register1 (SARADC_CHSEQ1) Register Offset Description Reset Value SARADC_CHSEQ1 SARADC_BA+0x44 R/W SARADC Channel Sequence Register1 0xFFFF_FFFF Reserved CHSEQ13 CHSEQ12 CHSEQ11 CHSEQ10 CHSEQ9 CHSEQ8 Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 318 ISD91500 Technical Reference Manual SARADC Compare Register 0/1 (SARADC_CMPn) Register Offset Description Reset Value SARADC_CMP0 SARADC_BA+0x48 R/W SARADC Compare Register 0 0x0000_0000 SARADC_CMP1 SARADC_BA+0x4C R/W SARADC Compare Register 1 0x0000_0000 Reserved CMPDAT CMPDAT Reserved CMPMCNT CMPCH Reserved CMPCOND ADCMPIE ADCMPEN...
Page 319 ISD91500 Technical Reference Manual Compare Channel Selection 0000 = Channel 0 conversion result is selected to be compared. 0001 = Channel 1 conversion result is selected to be compared. 0010 = Channel 2 conversion result is selected to be compared.
Page 320 ISD91500 Technical Reference Manual SARADC Status Register0 (SARADC_STATUS0) Register Offset Description Reset Value SARADC_STATUS0 SARADC_BA+0x50 R/W SARADC Status Register0 0x0000_00F0 Reserved Reserved Reserved OVRF CHANNEL BUSY ADCMPF1 ADCMPF0 ADIF Bits Description [31:9] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 321 ISD91500 Technical Reference Manual Compare Flag0 When the selected channel A/D conversion result meets setting conditions in SARADC_CMP0, then this bit is set to 1. And it is cleared by write 1. ADCMPF0 0 = Converted result RESULT in SARADC_DAT does not meet SARADC_CMP0 setting.
Page 322 ISD91500 Technical Reference Manual SARADC Status Register1 (SARADC_STATUS1) Register Offset Description Reset Value SARADC_STATUS1 SARADC_BA+0x54 R/W SARADC Status Register1 0x0000_0000 Reserved Reserved VALID VALID Bits Description [31] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 323 ISD91500 Technical Reference Manual SARADC PDMA Result Register (SARADC PDMADAT) Register Offset R/W Description Reset Value SARADC_PDMADAT SARADC_BA+0x58 R/W SARADC PDMA result Register 0x0000_0000 Reserved Reserved DATA DATA Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 324 ISD91500 Technical Reference Manual SARADC H/W Parameter Control Register (SARADC_HWPARA) Register Offset Description Reset Value SARADC_HWPARA SARADC_BA+0x5C R/W SARADC H/W Parameter Control Register 0x0000_0B00 Reserved Reserved Reserved CONVN Reserved SHCLKN Bits Description [31:15] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 325: Pdma Controller (Pdma)
ISD91500 Technical Reference Manual 5.13 PDMA Controller (PDMA) 5.13.1 Overview This device incorporates a Peripheral Direct Memory Access (PDMA) controller that transfers data between SRAM and APB devices. The PDMA has eight channels of DMA (CH0~CH7). PDMA transfers are unidirectional and can be Peripheral-to-SRAM, SRAM-to-Peripheral or SRAM-to-SRAM.
Page 326: Functional Description
ISD91500 Technical Reference Manual 5.13.4 Functional Description The PDMA controller has eight channels of DMA, each channel can be configured to one of the following transfer types: Peripheral-to-SRAM SRAM-to-Peripheral or SRAM-to-SRAM. The SRAM and the AHB- APB bus bridge each has an AHB bus arbiter that allows AHB bus access to occur either from the CPU or the PDMA controller.
Page 327: Register Map
ISD91500 Technical Reference Manual 5.13.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMAx_BA = 0x5000_9000 + (0x100 * x) x = 0,1,2,3,4,5,6,7 PDMA_GCR_BA = 0x5000_9F00...
Page 328: Register Description
ISD91500 Technical Reference Manual 5.13.6 Register Description PDMA Channel x Controller Register (PDMA_CSR) Register Offset Description Reset Value PDMA_CSR PDMAx_BA+0x00 PDMA Channel x Control Register 0x0000_0000 Reserved TRGEN Reserved APBTWS Reserved WAINTSEL Reserved DASEL SASEL MODESEL SWRST PDMACEN Bits Description...
Page 329 ISD91500 Technical Reference Manual Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR=32 then an interrupt could be generated when 16 bytes were sent.
Page 330 ISD91500 Technical Reference Manual PDMA Channel x Source Address Register (PDMA_SAR) Register Offset Description Reset Value PDMA_SAR PDMAx_BA+0x04 PDMA Channel x Source Address Register 0x0000_0000 Bits Description PDMA Transfer Source Address Register [31:0] This register holds the initial Source Address of PDMA transfer.
Page 331 ISD91500 Technical Reference Manual PDMA Channel x Destination Address Register (PDMA_DAR) Register Offset Description Reset Value PDMA_DAR PDMAx_BA+0x08 PDMA Channel x Destination Address Register 0x0000_0000 Bits Description PDMA Transfer Destination Address Register [31:0] This register holds the initial Destination Address of PDMA transfer.
Page 332 ISD91500 Technical Reference Manual PDMA Channel x Transfer Byte Count Register (PDMA_BCR) Register Offset Description Reset Value PDMA_BCR PDMAx_BA+0x0C PDMA Channel x Transfer Byte Count Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 333 ISD91500 Technical Reference Manual PDMA Channel x Internal Buffer Pointer Register (PDMA_POINT) Register Offset Description Reset Value PDMA_POINT PDMAx_BA+0x10 PDMA Channel x Internal buffer pointer Register 0xXXXX_0000 Reserved Reserved Reserved Reserved POINT Bits Description [31:4] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 334 ISD91500 Technical Reference Manual PDMA Channel x Current Source Address Register (PDMA_CSAR) Register Offset Description Reset Value PDMA_CSAR PDMAx_BA+0x14 PDMA Channel x Current Source Address Register 0x0000_0000 CSAR CSAR CSAR CSAR Bits Description PDMA Current Source Address Register (Read Only)
Page 335 ISD91500 Technical Reference Manual PDMA Channel x Current Destination Address Register (PDMA_CDAR) Register Offset Description Reset Value PDMA_CDAR PDMAx_BA+0x18 PDMA Channel x Current Destination Address Register 0x0000_0000 CDAR CDAR CDAR CDAR Bits Description PDMA Current Destination Address Register (Read Only)
Page 336 ISD91500 Technical Reference Manual PDMA Channel x Current Transfer Byte Count Register (PDMA_CBCR) Register Offset R/W Description Reset Value PDMA_CBCR PDMAx_BA+0x1C PDMA Channel x Current Transfer Byte Count Register 0x0000_0000 Reserved Reserved CBCR CBCR Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 337 ISD91500 Technical Reference Manual PDMA Channel x Interrupt Enable Control Register (PDMA_IER) Register Offset Description Reset Value PDMA_IER PDMAx_BA+0x20 PDMA Channel x Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved WRAPIEN TXIEN ABTIEN Bits Description [31:3] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 338 ISD91500 Technical Reference Manual PDMA Channel x Interrupt Status Register (PDMA_ISR) Register Offset Description Reset Value PDMA_ISR PDMAx_BA+0x24 PDMA Channel x Interrupt Status Register 0x0X0X_0000 INTR Reserved Reserved Reserved WRAPIF Reserved TXIF ABTIF Bits Description Interrupt Pin Status (Read Only)
Page 339 ISD91500 Technical Reference Manual PDMA Global Control Register (PDMA_GCRCSR) Register Offset Description Reset Value PDMA_GCRCSR PDMA_GCR_BA+0x00 PDMA Global Control Register 0x0000_0000 Reserved Reserved HCLKEN Reserved Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 340 ISD91500 Technical Reference Manual PDMA Service Selection Control Register 0 (PDMA_PDSSR0) Register Offset R/W Description Reset Value PDMA_PDSSR0 PDMA_GCR_BA+0x04 R/W PDMA Service Selection Control Register 0 0xFFFF_FFFF PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral.
Page 341 ISD91500 Technical Reference Manual PDMA UART1 Receive Selection This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request. [19:16] UART1RXSEL n = Select channel n.(n= 0~7) Others = Reserved. PDMA I2S0 Transmit Selection This field defines which PDMA channel is connected to I2S0 peripheral transmit (PDMA destination) request.
Page 342 ISD91500 Technical Reference Manual PDMA Service Selection Control Register 1 (PDMA_PDSSR1) Register Offset R/W Description Reset Value PDMA_PDSSR1 PDMA_GCR_BA+0x08 R/W PDMA Service Selection Control Register 1 0xFFFF_FFFF Reserved SPI1TXSEL SPI1RXSEL Reserved SARADCSEL DACTXSEL SDADCSEL Bits Description [31:24] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 343 ISD91500 Technical Reference Manual PDMA SDADC Receive Selection This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request. [3:0] SDADCSEL n = Select channel n.(n= 0~7) Others = Reserved. Feb. 21, 2023 Page 343 of 500...
Page 344 ISD91500 Technical Reference Manual PDMA Global Interrupt Status Register (PDMA_GCRISR) Register Offset Description Reset Value PDMA_GCRISR PDMA_GCR_BA+0x0C PDMA Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved GCRISR Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 345: Uart Interface Controller (Uart)
ISD91500 Technical Reference Manual 5.14 UART Interface Controller (UART) 5.14.1 Overview This device includes two channels of Universal Asynchronous Receiver/Transmitter (UART). The UART supports normal speed operation and flow control functions. The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU.The UART channel supports six types of interrupts including transmitter FIFO empty...
Page 346: Functional Description
ISD91500 Technical Reference Manual APB BUS Status & control Status & control Control and TX_FIFO RX_FIFO Status registers TX shift register RX shift register Baud Rate Generator Baud out Baud out Serial Data Out UART_CLK Serial Data In Figure 5.14-2 UART Block Diagram 5.14.4 Functional Description...
Page 347 ISD91500 Technical Reference Manual System clock = 49.152MHz Baud rate Mode0 %err Mode1 %err Mode2 %err 3250000 A=13 1843200 A=25 -1.2 1000000 A=47 921600 A=4,B=8 A=51 -0.6 460800 A=10,B=8 A=104 A=22,B=8 230400 A=211 -0.2 A=7,B=11 A=37,B=10 115200 A=25 A=425 A=31,B=12...
Page 348: Figure 5.14-3 Auto Flow Control Block Diagram
ISD91500 Technical Reference Manual Baud Rate Generator Divides the UART_CLK clock by the divisor to get the desired baud rate clock. Refer to Table 5.14-1 for the baud rate equation. Control and Status Register This is a register set, including the FIFO control registers (FIFO), FIFO status registers (FIFOSTS), and line control register (LINE) for transmitter and receiver.
Page 349: Register Map
ISD91500 Technical Reference Manual 5.14.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UART Base Address: UARTx_BA= 0x4006_0000 + (0x1000 * x) x=0,1 UART_DAT UARTx_BA+0x00 R/W UART Receive/Transmit FIFO Register.
Page 350: Register Description
ISD91500 Technical Reference Manual 5.14.6 Register Description UART Receive/Transmit FIFO Data Register (UART_DAT) Register Offset Description Reset Value UART_DAT UARTx_BA+0x00 R/W UART Receive/Transmit FIFO Register. 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 351 ISD91500 Technical Reference Manual UART Interrupt Enable Register (UART_INTEN) Register Offset Description Reset Value UART_INTEN UARTx_BA+0x04 R/W UART Interrupt Enable Register. 0x0000_0000 Reserved Reserved DMARXEN DMATXEN ATOCTSEN ATORTSEN TOCNTEN Reserved Reserved BUFERRIEN RXTOIEN MODEMIEN RLSIEN THREIEN RDAIEN Bits Description [31:16] Reserved Reserved.
Page 352 ISD91500 Technical Reference Manual Receive Time out Interrupt Enable RXTOIEN 0 = Mask off TOUT_INT 1 = Enable TOUT_INT Modem Status Interrupt Enable MODEMIEN 0 = Mask off MODEM_INT 1 = Enable MODEM_INT Receive Line Status Interrupt Enable RLSIEN 0 = Mask off RLS_INT...
Page 353 ISD91500 Technical Reference Manual UART FIFO Control Register (UART_FIFO) Register Offset Description Reset Value UART_FIFO UARTx_BA+0x08 R/W UART FIFO Control Register. 0x0000_0000 Reserved Reserved RTSTRGLV Reserved RFITL Reserved TXRST RXRST Reserved Bits Description [31:20] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 354 ISD91500 Technical Reference Manual Transmit FIFO Reset When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. TXRST 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the transmit internal state machine and pointers.
Page 355 ISD91500 Technical Reference Manual UART Line Control Register (UART_LINE) Register Offset Description Reset Value UART_LINE UARTx_BA+0x0C R/W UART Line Control Register. 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 356 ISD91500 Technical Reference Manual Word Length Select This field sets UART word length. 00 = 5 bits. [1:0] 01 = 6 bits. 10 = 7 bits. 11 = 8 bits. Feb. 21, 2023 Page 356 of 500 Rev 2.3...
Page 357 ISD91500 Technical Reference Manual UART MODEM Control Register (UART_MODEM) Register Offset Description Reset Value UART_MODEM UARTx_BA+0x10 R/W UART Modem Control Register. 0x0000_0000 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 358 ISD91500 Technical Reference Manual UART Modem Status Register (UART_MODEMSTS) Register Offset Description Reset Value UART_MODEMSTS UARTx_BA+0x14 R/W UART Modem Status Register. 0x0000_0000 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Bits Description [31:9] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 359 ISD91500 Technical Reference Manual UART FIFO Status Register (UART_FIFOSTS) Register Offset Description Reset Value UARTx_BA+0x18 R/W UART FIFO Status Register. UART_FIFOSTS 0x1040_4000 Reserved TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY TXPTR RXFULL RXEMPTY RXPTR Reserved Reserved RXOVIF Bits Description [31:29] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 360 ISD91500 Technical Reference Manual Receive FIFO Full(Read Only) [15] RXFULL This bit indicates whether the Rx FIFO is full or not. This bit is set when RxFIFO is full; otherwise it is cleared by hardware. Receive FIFO Empty(Read Only) This bit indicates whether the Rx FIFO is empty or not.
Page 361 ISD91500 Technical Reference Manual UART Interrupt Status Register (UART_INTSTS) Register Offset Description Reset Value UARTx_BA+0x1C R/W UART Interrupt Status Register. UART_INTSTS 0x0000_0002 Reserved DBERRINT DRXTOINT DMODINT DRLSINT Reserved Reserved DBERRIF DRXTOIF DMODIF DRLSIF Reserved Reserved BUFERRINT RXTOINT MODEMINT RLSINT THREINT...
Page 362 ISD91500 Technical Reference Manual DMA MODE Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, [18] DRLSIF UART_FIFOSTS.BIF, UART_FIFOSTS.FEF UART_FIFOSTS.PEF, set). UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
Page 363: Table 5.14-3 Uart Interrupt Sources And Flags Table In Software Mode
ISD91500 Technical Reference Manual Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If RDAIF IER.RDA_IEN is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
Page 364 ISD91500 Technical Reference Manual UART Time Out Register (UART_TOUT) Register Offset Description Reset Value UARTx_BA+0x20 R/W UART Time Out Register UART_TOUT 0x0000_0000 Reserved Reserved Reserved Reserved TOIC Bits Description [31:7] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 365 ISD91500 Technical Reference Manual UART Baud Rate Divider Register (UART_BAUD) Register Offset Description Reset Value UARTx_BA+0x24 R/W UART Baud Rate Divisor Register UART_BAUD 0x0F00_0000 The baud rate generator takes the UART master clock UART_CLK and divides it to produce the baud rate (bit rate) clock. The divider has two division stages controlled by BRD and EDIVM1 fields.
Page 366: Table 5.14-5 Baud Rate Equations
ISD91500 Technical Reference Manual Table 5.14-5 Baud Rate Equations Mode BAUDM1 BAUDM0 EDIVM1[3:0] BRD[15:0] Baud rate equation Don’t care UART_CLK / [16 * (A+2)] UART_CLK / [(B+1) * (A+2)], requires B≥ 8 UART_CLK / (A+2), requires A ≥ 10 Don’t care Feb.
Page 367: Flash Memory Controller (Fmc)
ISD91500 Technical Reference Manual 5.15 Flash Memory Controller (FMC) 5.15.1 Overview This device is available with 64kbytes of on-chip embedded Flash EEPROM for application program and data flash memory. The memory can be updated through procedures for In-Circuit Programming (ICP) through the ARM Serial-Wire Debug (SWD) port or via In-System Programming (ISP) functions under software control.
Page 368: Flash Memory Organization
ISD91500 Technical Reference Manual Cortex-M0 Debug Access AHB Lite Port interface AHB Bus 0x0000_FFFF AHB Slave Interface Writer Interface Controller Flash Power On Operation Initialization Control 0x0000_17FF Application Memory ISP Program Data Out CONFIG & (APROM+DATA) Memory (LDROM) Control CBS=1...
Page 369: Boot Selection
ISD91500 Technical Reference Manual 0x0030_01FF User Configuration CONFIG 0x0030_0000 0x0010_17FF ISP Loader Program Memory LDROM 0x0010_0000 Reserved 0x0000_FFFF Data Flash DATAF DFBADR Application Program Memory APROM CONFIG1 0x0030_0004 CONFIG0 0x0030_0000 0x0000_0000 Figure 5.15-2 Flash Memory Organization 5.15.5 Boot Selection This device provides an in-system programming (ISP) feature to enable user to update the application program memory when the chip is mounted on a PCB.
Page 370: Data Flash (Dataf)
ISD91500 Technical Reference Manual when CBS = 0 are set to boot from LDROM, the software executed in LDROM will not be able to access APROM by memory read. The following figure shows the memory map when booting from APROM and LDROM.
Page 371: Figure 5.15-5 Flash Memory Structure
ISD91500 Technical Reference Manual 0x0000_FFFF DataFlash 0.5*N k bytes Programmable start DFBA[31:0] address Application Program (64-0.5*N) k bytes 64kB Flash Memory Structure Figure 5.15-5 Flash Memory Structure Feb. 21, 2023 Page 371 of 500 Rev 2.3...
Page 372: User Configuration (Config)
ISD91500 Technical Reference Manual 5.15.7 User Configuration (CONFIG) CONFIG0 (Address = 0x0030_0000) Reserved CLVR Reserved CBOV CBOV CBORST CBODEN Reserved Reserved RST_DEB Reserved LOCK DFEN CONFIG0 Address = 0x0030_0000 Bits Description Reserved. Any values read should be ignored. When writing to this field always write with...
Page 373 ISD91500 Technical Reference Manual CONFIG0 Address = 0x0030_0000 Bits Description Config BOD Voltage Sets the BOD detect voltage after configuration. 1111 = 3.4V 1110 = 3.4V 1101 = 3.4V 1100 = 3.4V 1011 = 3.4V 1010 = 3.4V 1001 = 3.1V...
Page 374 ISD91500 Technical Reference Manual CONFIG0 Address = 0x0030_0000 Bits Description 0 = Flash data locked. 1 = Flash data unlocked. When flash data is locked, only device ID, user configuration can be read by writer and ICP through serial debug interface. Others data is locked as 0xFFFFFFFF. ISP can read data anywhere regardless of LOCK bit value.
Page 375 ISD91500 Technical Reference Manual CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBA DFBA CONFIG1 Address = 0x0030_0004 Bits Descriptions [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. [15:0] DFBADR Data Flash Base Address The Data Flash base address is defined by user.
Page 376: In-System Programming (Isp)
ISD91500 Technical Reference Manual 5.15.8 In-System Programming (ISP) The program and data flash memory support both in hardware In-Circuit Programming (ICP) and firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-Wire Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang-writers are available to reduce programming and manufacturing costs.
Page 377: Figure 5.15-7 Boot Sequence And Isp Procedure
ISD91500 Technical Reference Manual Power CBS = 1 ? Enable ISPEN Write ISPADR/ ISPCMD/ Fetch code from Fetch code from ISPDAT LDROM APROM Set ISPTRIG = 1 Update LD-ROM or Execute ISP? write DataFlash End of Flash Operation (Read ISPDAT)
Page 378: Table 5.15-3 Isp Command Set
ISD91500 Technical Reference Manual Table 5.15-3 ISP Command Set ISPCMD ISPADR ISPDAT ISP Mode ISPCMD[5:0] A[19:0] D[31:0] Read Company ID 0x0B Returns 0x0000_00DA Read Device ID 0x0C 0x00000 FLASH Page Erase 0x22 A[20] A[19:0] FLASH Program 0x21 A[20] A[19:0] Data input...
Page 379: Register Map
ISD91500 Technical Reference Manual 5.15.10 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address FMC_BA = 0x5000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0002_0000 FMC_ISPADR FMC_BA+0x04 ISP Address Register...
Page 380: Register Description
ISD91500 Technical Reference Manual 5.15.11 Register Description ISP Control Register (FMC_ISPCTL) Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0002_0000 Reserved Reserved CACHE_DIS Reserved WAIT_CFG Reserved Reserved ISPFF LDUEN CFGUEN APUWEN Reserved ISPEN Bits Description [31:22] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 381 ISD91500 Technical Reference Manual ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. ISPFF (2) LDROM writes to itself. (3) Destination address is illegal, such as over an available range.
Page 382 ISD91500 Technical Reference Manual ISP Address Register (FMC_ISPADR) Register Offset Description Reset Value FMC_ISPADR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADR ISPADR ISPADR ISPADR Bits Description ISP Address Register [31:0] ISPADR This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD [1:0] must be 00b for correct ISP operation.
Page 383 ISD91500 Technical Reference Manual ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description ISP Data Register [31:0] ISPDAT Write data to this register before an ISP program operation.
Page 384 ISD91500 Technical Reference Manual ISP Command (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPCMD Bits Description [31:6] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 385 ISD91500 Technical Reference Manual ISP Trigger Control Register (FMC_ISPTRG) Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 386 ISD91500 Technical Reference Manual Data Flash Base Address Register (FMC_DFBADR) Register Offset Description Reset Value FMC_DFBADR FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA DFBA DFBA DFBA Bits Description Data Flash Base Address This register reports the data flash starting address. It is a read only register.
Page 387: Usb 1.1 Device Controller (Usbd)
ISD91500 Technical Reference Manual 5.16 USB 1.1 Device Controller (USBD) 5.16.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous transfer types.
Page 388: Block Diagram
ISD91500 Technical Reference Manual 5.16.3 Block Diagram Clock NVIC Generator VBUS Detection VBUS Interrupt Detection DPLL control control De-bouncing status registers USB_D+ APB Bus RXDP Endpoint USB_D- Control RXDM SRAM USB_VBUS Buffer Control Bytes) Transceiver Figure 5.16-1 USB Block Diagram 5.16.4 Basic Configuration...
Page 389: Functional Description
ISD91500 Technical Reference Manual 5.16.5 Functional Description 5.16.5.1 Serial Interface Engine (SIE) The SIE is the front-end of the device controller and handles most of the USB packet protocol. The SIE typically comprehends signaling up to the transaction level. The functions that it handles could include: ...
Page 390: Figure 5.16-2 Nevwk Interrupt Operation Flow
ISD91500 Technical Reference Manual on USB_VBUS, USB_D+ and USB_D- can wake up this chip if USB wake-up function is enabled. If this change is not intentionally, no interrupt but NEVWK interrupt will occur. After waking up by USB, this interrupt will occur when no the other USB interrupt events are presented for more than 20ms. The Figure 5.16-2 is the control flow of wake-up interrupt.
Page 391: Figure 5.16-3 Endpoint Sram Structure
ISD91500 Technical Reference Manual is set as 0x40h, the SRAM size of endpoint 0 is start from USBD_BA+0x108h and end in USBD_BA+0x148h. (Note: The USBD SRAM base is USBD_BA+0x100h). USBD_SRAM = USBD_BA + 0x0100h USB SRAM Start Address Setup Token Buffer: 8 bytes...
Page 392: Figure 5.16-5 Data Out Transfer
ISD91500 Technical Reference Manual Alternatively, when USB host wants to transmit data to the OUT endpoint in the device controller, hardware will buffer these data to the specified endpoint buffer. After this transaction is completed, hardware will record the data length in specified USBD_MXPLDx register and de-assert the internal signal “Out_Rdy”.
Page 393: Register Map
ISD91500 Technical Reference Manual 5.16.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USBD Base Address: USBD_BA = 0x400C_0000 USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 USBD_INTSTS...
Page 394 ISD91500 Technical Reference Manual Register Offset R/W Description Reset Value USBD Base Address: USBD_BA = 0x400C_0000 USBD_MXPLD3 USBD_BA+0x534 R/W Endpoint 3 Maximal Payload Register 0x0000_0000 USBD_CFG3 USBD_BA+0x538 R/W Endpoint 3 Configuration Register 0x0000_0000 USBD_CFGP3 USBD_BA+0x53C R/W Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x0000_0000...
Page 395 ISD91500 Technical Reference Manual Register Offset R/W Description Reset Value USBD Base Address: USBD_BA = 0x400C_0000 USBD_BUFSEG10 USBD_BA+0x5A0 R/W Endpoint 10 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD10 USBD_BA+0x5A4 R/W Endpoint 10 Maximal Payload Register 0x0000_0000 USBD_CFG10 USBD_BA+0x5A8 R/W Endpoint 10 Configuration Register...
Page 396: Register Description
ISD91500 Technical Reference Manual 5.16.7 Register Description USB Interrupt Enable Register (USBD_INTEN) Register Offset R/W Description Reset Value USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 Reserved Reserved INNAKEN Reserved WKEN Reserved SOFIEN NEVWKIEN VBDETIEN USBIEN BUSIEN Bits Description...
Page 397 ISD91500 Technical Reference Manual USB Event Interrupt Enable Bit USBIEN 0 = USB event interrupt Disabled. 1 = USB event interrupt Enabled. Bus Event Interrupt Enable Bit BUSIEN 0 = BUS event interrupt Disabled. 1 = BUS event interrupt Enabled.
Page 398 ISD91500 Technical Reference Manual USB Interrupt Event Status Register (USBD_INTSTS) Register Offset R/W Description Reset Value USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 SETUP Reserved EPEVT11 EPEVT10 EPEVT9 EPEVT8 EPEVT7 EPEVT6 EPEVT5 EPEVT4 EPEVT3 EPEVT2 EPEVT1 EPEVT0...
Page 399 ISD91500 Technical Reference Manual Endpoint 6’s USB Event Status 0 = No event occurred in endpoint 6. [22] EPEVT6 1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
Page 400 ISD91500 Technical Reference Manual 0 = No USB event occurred. 1 = USB event occurred, check EPSTS (USBD_EPSTS0 and USBD_EPSTS1) to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPEVT11~0 (USBD_INTSTS[27:16] and SETUP (USBD_INTSTS[31]).
Page 401 ISD91500 Technical Reference Manual USB Device Function Address Register (USBD_FADDR) A 7-bit value is used as the address of a device on the USB BUS. Register Offset R/W Description Reset Value USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register 0x0000_0000...
Page 402 ISD91500 Technical Reference Manual USB Endpoint Status Register (USBD_EPSTS) Register Offset R/W Description Reset Value USBD_EPSTS USBD_BA+0x00C USB Device Endpoint Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 403 ISD91500 Technical Reference Manual USB Bus Status and Attribution Register (USBD_ATTR) Register Offset R/W Description Reset Value USBD_ATTR USBD_BA+0x010 R/W USB Device Bus Status and Attribution Register 0x0000_0040 Reserved Reserved Reserved BYTEM PHYPD DPPUEN USBEN Reserved RWAKEUP PHYEN TOUT RESUME...
Page 404 ISD91500 Technical Reference Manual Time-out Status 0 = No time-out. TOUT 1 = No Bus response more than 18 bits time. Note: This bit is read only. Resume Status 0 = No bus resume. RESUME 1 = Resume from suspend.
Page 405 ISD91500 Technical Reference Manual USB Device VBUS Detection Register (USBD_VBUSDET) Register Offset R/W Description Reset Value USBD_VBUSDET USBD_BA+0x014 USB Device VBUS Detection Register 0x0000_0000 Reserved Reserved Reserved PULLD Reserved VBUSDET Bits Description [31:9] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 406 ISD91500 Technical Reference Manual USB SETUP Token Buffer Segmentation Register (USBD_STBUFSEG) Offset R/W Description Reset Value Register USBD_STBUFSEG USBD_BA+0x018 R/W SETUP Token Buffer Segmentation Register 0x0000_0000 Reserved Reserved Reserved STBUFSEG STBUFSEG Reserved Description Bits [31:9] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 407 ISD91500 Technical Reference Manual USB Endpoint Status Register 0 (USBD_EPSTS0) Register Offset R/W Description Reset Value USBD_EPSTS0 USBD_BA+0x020 USB Device Endpoint Status Register 0 0x0000_0000 EPSTS7 EPSTS6 EPSTS5 EPSTS4 EPSTS3 EPSTS2 EPSTS1 EPSTS0 Bits Description Endpoint 7 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK.
Page 408 ISD91500 Technical Reference Manual Endpoint 5 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK. 0001 = In NAK. [23:20] EPSTS5 0010 = Out Packet Data0 ACK. 0011 = Setup ACK. 0110 = Out Packet Data1 ACK.
Page 409 ISD91500 Technical Reference Manual Endpoint 0 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK. 0001 = In NAK. [3:0] EPSTS0 0010 = Out Packet Data0 ACK. 0011 = Setup ACK. 0110 = Out Packet Data1 ACK.
Page 410 ISD91500 Technical Reference Manual USB Endpoint Status Register 1 (USBD_EPSTS1) Register Offset R/W Description Reset Value USBD_EPSTS1 USBD_BA+0x024 USB Device Endpoint Status Register 1 0x0000_0000 Reserved Reserved EPSTS11 EPSTS10 EPSTS9 EPSTS8 Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 411 ISD91500 Technical Reference Manual Endpoint 9 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK. 0001 = In NAK. [7:4] EPSTS9 0010 = Out Packet Data0 ACK. 0011 = Setup ACK. 0110 = Out Packet Data1 ACK.
Page 412 ISD91500 Technical Reference Manual USB Frame Number Register (USBD_FN) Offset R/W Description Reset Value Register USBD_FN USBD_BA+0x08C USB Frame number Register 0x0000_0XXX Reserved Reserved Reserved Description Bits [31:11] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 413 ISD91500 Technical Reference Manual USB Drive SE0 Register (USBD_SE0) Offset R/W Description Reset Value Register USBD_SE0 USBD_BA+0x090 R/W USB Device Drive SE0 Control Register 0x0000_0001 Reserved Reserved Reserved Reserved Description Bits [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 414 ISD91500 Technical Reference Manual USB Device VBUS Detection De-bounce Control Register (USBD_VDDIS) Offset R/W Description Reset Value Register USBD_VDDIS USBD_BA+0x0A8 R/W USB Device VBUS Detection De-bounce Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VDDIS Description Bits [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 415 ISD91500 Technical Reference Manual USB Buffer Segmentation Register (USBD_BUFSEGx) Register Offset R/W Description Reset Value USBD_BUFSEG0 USBD_BA+0x500 R/W Endpoint 0 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG1 USBD_BA+0x510 R/W Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG2 USBD_BA+0x520 R/W Endpoint 2 Buffer Segmentation Register...
Page 416 ISD91500 Technical Reference Manual [2:0] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. Feb. 21, 2023 Page 416 of 500 Rev 2.3...
Page 417 ISD91500 Technical Reference Manual USB Maximal Payload Register (USBD_MXPLDx) Register Offset R/W Description Reset Value USBD_MXPLD0 USBD_BA+0x504 R/W Endpoint 0 Maximal Payload Register 0x0000_0000 USBD_MXPLD1 USBD_BA+0x514 R/W Endpoint 1 Maximal Payload Register 0x0000_0000 USBD_MXPLD2 USBD_BA+0x524 R/W Endpoint 2 Maximal Payload Register...
Page 418 ISD91500 Technical Reference Manual Maximal Payload Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
Page 419 ISD91500 Technical Reference Manual USB Configuration Register (USBD_CFGx) Register Offset R/W Description Reset Value USBD_CFG0 USBD_BA+0x508 R/W Endpoint 0 Configuration Register 0x0000_0000 USBD_CFG1 USBD_BA+0x518 R/W Endpoint 1 Configuration Register 0x0000_0000 USBD_CFG2 USBD_BA+0x528 R/W Endpoint 2 Configuration Register 0x0000_0000 USBD_CFG3 USBD_BA+0x538...
Page 420 ISD91500 Technical Reference Manual Data Sequence Synchronization 0 = DATA0 PID. DSQSYNC 1 = DATA1 PID. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit.
Page 421 ISD91500 Technical Reference Manual USB Extra Configuration Register (USBD_CFGPx) Register Offset R/W Description Reset Value USBD_CFGP0 USBD_BA+0x50C R/W Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_CFGP1 USBD_BA+0x51C R/W Endpoint 1 Set Stall and Clear In/Out Ready Control Register...
Page 422 ISD91500 Technical Reference Manual Clear Ready When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
Page 423: Companding (Cpd)
ISD91500 Technical Reference Manual 5.17 Companding (CPD) 5.17.1 Overview The companding is used in digital communication systems to optimize signal-to-noise ratio with reduced data bit rates using non-linear algorithms. The device supports telecommunications companding: A-law, u-law (G.711) and ADPCM (G.726). Both Encoder and Decoder has input and output FIFO. Encoder circuit has an 8-level 16 bits FIFO at encoder input, and an 8-level 8 bits output FIFO at encoder output.
Page 424: Figure 5.17-1 Cpd Controller Interrupt
ISD91500 Technical Reference Manual CPD_STS.DOTHIF CPD_STS.DOTHIE CPD_STS.DITHIF CPD_STS.DITHIE CPD_IRQ CPD_STS.EOTHIF CPD_STS.EOTHIE CPD_STS.EITHIF CPD_STS.EITHIE Figure 5.17-1 CPD controller interrupt 5.17.3.4 Configuring Companding setting To operate the companding setting the following configuration is recommended:  Enable Companding clock source by register CPDCKEN (CLK_AHBCLK[1]).
Page 425: Register Map
ISD91500 Technical Reference Manual 5.17.4 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value CPD Base Address: CPD_BA = 0x5000_E000 CPD_CTRL CPD_BA+0x00 R/W CPD Control Register 0x0000_0000 CPD_STS CPD_BA+0x04 R/W CPD FIFO Status Register...
Page 426: Register Description
ISD91500 Technical Reference Manual 5.17.5 Register Description CPD Control Register (CPD_CTRL) Register Offset R/W Description Reset Value CPD_CTRL CPD_BA+0x00 R/W CPD Control Register 0x0000_0000 DOTHIE DOTH DITHIE DITH EOTHIE EOTH EITHIE EITH Reserved DECRST ENCRST Reserved BITRATE TYPE MODE Bits...
Page 427 ISD91500 Technical Reference Manual Encoder input FIFO Threshold Level [18:16] EITH If the valid data count of the FIFO data buffer is less than or equal to EITH (CPD_CTRL[18:16]) setting, the EITHIF (CPD_STS[3]) will set to 1, else the DITHIF (CPD_STS[3]) will be cleared to 0.
Page 428 ISD91500 Technical Reference Manual CPD FIFO Status Register (CPD_STS) Register Offset Description Reset Value CPD_STS CPD_BA+0x04 CPD FIFO Status Register 0x0202_0202 DOFPTR DOTHIF Reserved DIFPTR DITHIF DIOV EOFPTR EOTHIF Reserved EIFPTR EITHIF EIOV Bits Description CPD decoder output FIFO Pointer (Read Only)
Page 429 ISD91500 Technical Reference Manual CPD decoder input FIFO Threshold Interrupt Status (Read Only) 0 = The valid data count within the FIFO data buffer is more than the setting value of DITH (CPD_CTL[26:24]). [19] DITHIF 1 = The valid data count within the FIFO data buffer is less than or equal to the setting value of DITH (CPD_CTL[26:24]).
Page 430 ISD91500 Technical Reference Manual CPD encoder input FIFO Threshold Interrupt Status (Read Only) 0 = The valid data count within the FIFO data buffer is more than the setting value of EITH (CPD_CTL[18:16]). EITHIF 1 = The valid data count within the FIFO data buffer is less than or equal to the setting value of EITH (CPD_CTL[18:16]).
Page 431 ISD91500 Technical Reference Manual CPD Encoder Input FIFO (CPD_ENCIN) Register Offset R/W Description Reset Value CPD_ENCIN CPD_BA+0x08 CPD Encoder Input FIFO 0x0000_0000 Reserved Reserved ENCIN ENCIN Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 432 ISD91500 Technical Reference Manual CPD Encoder Output FIFO (CPD_ENCOUT) Register Offset R/W Description Reset Value CPD_ENCOUT CPD_BA+0x0C CPD Encoder Output FIFO 0x0000_0000 Reserved Reserved Reserved ENCOUT Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 433 ISD91500 Technical Reference Manual CPD Decoder Input FIFO (CPD_DECIN) Register Offset R/W Description Reset Value CPD_DECIN CPD_BA+0x10 CPD Decoder Input FIFO 0x0000_0000 Reserved Reserved Reserved DECIN Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 434 ISD91500 Technical Reference Manual CPD Decoder Output FIFO (CPD_DECOUT) Register Offset R/W Description Reset Value CPD_DECOUT CPD_BA+0x14 CPD Decoder Output FIFO 0x0000_0000 Reserved Reserved DECOUT DECOUT Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 435: Digital-To-Analog Converter With Headphone Driver Output (Dac)
ISD91500 Technical Reference Manual 5.18 Digital-to-Analog Converter with Headphone Driver Output (DAC) 5.18.1 Overview This device includes stereo 24-bits Audio Digital -to- Analog converter(DAC). The DAC provides high quality audio playback suitable for all portable audio applications. There are also digital volume from - 80dB to 6dB with 0.5dB/step in front of DAC.
Page 436: Figure 5.18-2 Dac Clock Control Diagram
ISD91500 Technical Reference Manual The signal then sent to the DAC driver stage. Master clock rate of the Delta-Sigma modulator is controlled by DAC_CLK. 5.18.4.1 DAC Clock Generation The DAC module has six clock sources selected by register DACSEL (CLK_CLKSEL2[14:12]).
Page 437: Table 5.18-1 Effective Osr For Different Osr_Div Setting
ISD91500 Technical Reference Manual Table 5.18-1 Effective OSR for different OSR_DIV setting DAC_CTL1[15:13] OSR_DIV DAC_SD_CLK Effective OSR b’000 F_DAC_CLK/4 b’001 F_DAC_CLK/8 b’010 F_DAC_CLK/2 b’100 F_DAC_CLK/1 For CLKSET (DAC_CTL0[31]) = 1, OSR100 (DAC_CTL1[11]) and MIPS500 (DAC_CTL1[12]) must be set. The OSR_DIV is automatically set to 5. OSRSEL is invalid in this case. The effective OSR is as shown in Table 5.18-2.
Page 438: Table 5.18-4 Sample Rates For Clkset (Dac_Ctl0[31]) = 1
ISD91500 Technical Reference Manual 2.048MHz b’10000 1.024MHz b’01000 8KHz 2.048MHz 512KHz b’00000 256KHz b’00100 Table 5.18-4 Sample Rates for CLKSET (DAC_CTL0[31]) = 1 F_DAC_CLK DAC_SD_CLK OSR_DIV DAC_CTL1[15:11] 48KHz 12MHz 2.4MHz b’00011 32KHz 8MHz 1.6MHz b’00011 24KHz 6MHz 1.2MHz b’00011 16KHz...
Page 439: Figure 5.18-4 Audio Dac Fifo Contents For 16Bits
ISD91500 Technical Reference Manual MONO MODESEL(DAC_CLT[5:4]=01), FIFOWIDTH(DAC_CLT[1:0]=01) STEREO MODESEL(DAC_CLT[5:4]=00), FIFOWIDTH(DAC_CLT[1:0]=01) RIGHT LEFT Figure 5.18-4 Audio DAC FIFO Contents for 16bits MONO MODESEL(DAC_CLT[5:4]=01), FIFOWIDTH(DAC_CLT[1:0]=11) Redundant bits STEREO MODESEL(DAC_CLT[5:4]=00), FIFOWIDTH(DAC_CLT[1:0]=11) LEFT Redundant bits RIGHT Redundant bits Figure 5.18-5 Audio DAC FIFO Contents for 24bits...
Page 440: Figure 5.18-7 Audio Dac Fifo Pointer Block
ISD91500 Technical Reference Manual DAC FIFO Pointer = 32 32th word(32-bit) Pointer = 31 31th word(32-bit) Pointer = 30 30th word(32-bit) Pointer = 29 Total 29th word(32-bit) 32-level Pointer = 2 2nd word(32-bit) Pointer = 1 1st word(32-bit) Pointer = 0 Figure 5.18-7 Audio DAC FIFO pointer block...
Page 441: Figure 5.18-8 Headphone Output Clamp Options
ISD91500 Technical Reference Manual headphone outputs. When headphone outputs are in a not-used operating condition, setting CLPVMID (DAC_ANA1[24]) will connect the headphone outpus to internal DC voltage source to keep the voltage of headphone output capacitors the same as the headphone outputs in operating condition.
Page 442 ISD91500 Technical Reference Manual 5.18.4.8 Recommended Power up/down Sequence (RevC) In order to reduce headphone outputs pop noise, it is recommended to use the specific sequence to configure the DAC path. Table 5.18-5 summaries the value of register DAC_ANA1 in each phase.
Page 443: Table 5.18-5 Dac_Ana1 Register Setting In Each Phase
ISD91500 Technical Reference Manual Table 5.18-5 DAC_ANA1 Register Setting in Each Phase DAC_ANA1 Pre-charge Operational Clamp Register Phase Phase Phase CLPVMID PRECHG VOLEN2/1 PDBDAC2/1 PDIBGEN PDVBUF2/1 PDFLITSM2/1 ENHP2/1 ENDAC2/1 ENCLK2/1 Feb. 21, 2023 Page 443 of 500 Rev 2.3...
Page 444: Register Map
ISD91500 Technical Reference Manual 5.18.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value DAC Base Address: DAC_BA = 0x4007_0000 DAC_DAT DAC_BA+0x00 DAC FIFO Data Write Register 0xXXXX_XXXX DAC_CTL0 DAC_BA+0x04...
Page 445: Register Description
ISD91500 Technical Reference Manual 5.18.6 Register Description DAC FIFO Data Register(DAC_DAT) Register Offset R/W Description Reset Value DAC_DAT DAC_BA+0x00 DAC FIFO Data Write Register 0xXXXX_XXXX FIFO FIFO FIFO FIFO Bits Description FIFO Data Input Register DAC contains 32 words (32x32 bit) data buffer for data transmit. A write to this register pushes data onto...
Page 446 ISD91500 Technical Reference Manual DAC Control Register 0 (DAC_CTL0) Register Offset Description Reset Value DAC_CTL0 DAC_BA+0x04 DAC Control Register 0 0x0000_0000 CLKSET SWRST FCLR Reserved Reserved THIE Reserved FIFOEN MODESEL Reserved FIFOWIDTH Bits Description Working Clock Selection [31] CLKSET 0 = The sampling rate is DACCLK/256...
Page 447 ISD91500 Technical Reference Manual DAC FIFO enable control 00 = FIFO disable [7:6] FIFOEN 11 = FIFO enable Others = Reserved. Do not use. Data Control in FIFO 00 = Data is stereo format [5:4] MODESEL 01 = Data is monaural format Others = Reserved.
Page 448 ISD91500 Technical Reference Manual DAC Digital Volume Control Register (DAC_DVOL) Register Offset Description Reset Value DAC_DVOL DAC_BA+0x08 DAC Digital Volume Control Register 0x0000_CFCF Reserved Reserved DACRVOL DACLVOL Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 449 ISD91500 Technical Reference Manual DACL Digital Volume Control Register 0xff = +6dB 0xfe = +5.5dB ▼ 0xf3 = 0dB 0xf2= -0.5dBdB ▼ [7:0] DACLVOL 0x53= -80dB 0x52= Reserved ▼ 0x01= Reserved 0x00 = Mute Note: Volume per step 0.5dB Feb. 21, 2023 Page 449 of 500 Rev 2.3...
Page 450 ISD91500 Technical Reference Manual DAC FIFO Status Register (DAC_FIFOSTS) Register Offset Description Reset Value DAC_FIFOSTS DAC_BA+0x0C DAC FIFO Status Register 0x0000_0002 Reserved Reserved Reserved FIFOPTR FIFOPTR Reserved THIF EMPTY FULL Bits Description [31:10] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 451 ISD91500 Technical Reference Manual DAC PDMA Control Register (DAC_PDMACTL) Register Offset R/W Description Reset Value DAC_PDMACTL DAC_BA+0x10 R/W DAC PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMAEN Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 452 ISD91500 Technical Reference Manual DAC Control Register 1 (DAC_CTL1) Register Offset Description Reset Value DAC_CTL1 DAC_BA+0x200 DAC control register 1 0x0003_8000 Reserved Reserved DISDEM Reserved OSRDIV MISP500 OSR100 DEMDITHER DEMDITHER SDDITHER DACENR DACENL Bits Description [31:18] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 453 ISD91500 Technical Reference Manual SDMOD dither control Number of bits of dithering on SD Modulator . Each level increments dithering by 1 bit 0000 = No Dithering [6:2] SDDITHER 0001 = 1 1111 = 15 DACENR SDMOD enable control for right channel...
Page 454 ISD91500 Technical Reference Manual DAC Control Register 3 (DAC_CTL3) Register Offset R/W Description Reset Value DAC_CTL3 DAC_BA+0x20C R/W DAC control register 3 0x0000_0000 Reserved Reserved Reserved Reserved ZCEN Reserved UNMUTECTL Reserved SMCTL Bits Description [31:5] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 455 ISD91500 Technical Reference Manual DAC Analog Block Control Register 0 (DAC_ANA0) Register Offset R/W Description Reset Value DAC_ANA0 DAC_BA+0x300 R/W DAC Analog Block Control Register 0 0x0000_40B9 Reserved Reserved CLKINV VREFSEL IBADJV1P5 CKDLYV1P5 CAPV1P5 BV1P5 Bits Description [31:16] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 456 ISD91500 Technical Reference Manual Delay clock choice for DAC 000 = clk_3. 001 = clk_4. 010 = clk_5. [10:8] CKDLYV1P5 011 = clk_6. 100 = clk_7. 101 = clk_0. 110 = clk_1. 111 = clk_2. Bypass cap setting 00 = 0C.
Page 457 ISD91500 Technical Reference Manual DAC Analog Block Control Register 1 (DAC_ANA1) Register Offset R/W Description Reset Value DAC_ANA1 DAC_BA+0x304 R/W DAC Analog Block Control Register 1 0x0001_FF00 Reserved CLPVMID PRECHG Reserved VROI VOLMUTE VOLEN2 VOLEN1 PDBDAC2 PDBDAC1 Reserved Reserved PDIBGEN...
Page 458 ISD91500 Technical Reference Manual Volume mute control [21] VOLMUTE 0 = Unmute. 1 = Mute Right volume enable control [20] VOLEN2 0 = Disable. 1 = Enable. Left volume enable control [19] VOLEN1 0 = Disable. 1 = Enable. Right DAC power down control...
Page 459 ISD91500 Technical Reference Manual Left channel headphone driver block enable control 00 = Disable. [5:4] ENHP1 11 = Enable. Others = Reserved. Do not use. Right channel DAC enable control ENDAC2 0 = Disable. 1 = Enable Left channel DAC enable control ENDAC1 0 = Disable.
Page 460: Sigma- Delta Analog-To-Digital Converter (Sdadc)
ISD91500 Technical Reference Manual 5.19 Sigma- Delta Analog-to-Digital Converter (SDADC) 5.19.1 Overview This device series includes a Delta-Sigma Audio Analog-to-Digital converter.The converter can run at sampling rates up to 6.144MHz while a configurable decimation filter allows oversampling ratios of 64/128/256/384. A special oversampling ratio 62.5 is also supported when the input clock is 12M /24M/48M base.
Page 461: Figure 5.19-2 Sdadc Clock Control Diagram
ISD91500 Technical Reference Manual 5.19.4.1 SDADC Clock Generator SDADCSEL (CLK_CLKSEL2[14:12]) XCLK SDADCEN(CLK_APBCLK[30]) MCLKI HIRC MCLK 1/CLKDIV SD_CLK PCLK 1/(SDADCDIV + 1) PLLFOUT SDADCDIV(CLK_CLKDIV1[23:16]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Page 462: Table 5.19-1 Sample Rates For Mclk 24.576Mhz(Biq On Sdadc)
ISD91500 Technical Reference Manual Table 5.19-1 Sample Rates for MCLK 24.576MHz(BIQ on SDADC) SD_CLK CLKDIV SDADC_CTL.DSRATE BIQ_CTL.SDADCWNSR 6.144MHz 48KHz 3.072MHz 6.144MHz 4.096MHz 32KHz 2.048MHz 6.144MHz 4.096MHz 2.048MHz 16KHz 1.024MHz 3.072MHz 2.048MHz 8KHz 1.024MHz 512KHz Feb. 21, 2023 Page 462 of 500...
Page 463: Table 5.19-2 Sample Rates For Mclk 12.288Mhz(Biq On Sdadc)
ISD91500 Technical Reference Manual Table 5.19-2 Sample Rates for MCLK 12.288MHz(BIQ on SDADC) SD_CLK CLKDIV SDADC_CTL.DSRATE BIQ_CTL.SDADCWNSR 48KHz 3.072MHz 3.072MHz 32KHz 2.048MHz 2.048MHz 16KHz 1.024MHz 3.072MHz 2.048MHz 8KHz 1.024MHz 512KHz Feb. 21, 2023 Page 463 of 500 Rev 2.3...
Page 464: Table 5.19-3 Sample Rates For Sdadc Source Clock From Hirc 48Mhz(Biq On Sdadc)
ISD91500 Technical Reference Manual Table 5.19-3 Sample Rates for SDADC source clock from HIRC 48MHz(BIQ on SDADC) SDADC_DIV MCLK SD_CLK CLKDIV SDADC_CTL.DSRATE BIQ_CTL.SDADCWNSR 48MHz 6MHz 48KHz 62.5 24MHz 62.5 3MHz 187.5 6MHz 16MHz 32KHz 62.5 62.5 2MHz 24MHz 187.5 3MHz...
Page 465 ISD91500 Technical Reference Manual • Selecting and powering up VMID reference: power on VMID generator, power on both low and high value resistor. • Wait 7 RC time, then turn off lower value resistor, and then wait 1or 2 RC time.
Page 466: Figure 5.19-5 Sdadc Controller Interrupt
ISD91500 Technical Reference Manual SDADC_FIFOSTS.THIF SDADC_CTL.FIFOTHIE SDADC_CMPR0.CMPF SDADC_IRQ SDADC_CMPR0.CMPIE SDADC_CMPR1.CMPF SDADC_CMPR1.CMPIE Figure 5.19-5 SDADC controller interrupt 5.19.4.6 Peripheral DMA Request Normal use Normal use of the SDADC is with PDMA. In this mode SDADC requests PDMA service whenever data is in FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full.
Page 467: Register Map
ISD91500 Technical Reference Manual 5.19.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value SDADC Base Address: SDADC_BA = 0x400D_0000 SDADC_DAT SDADC_BA+0x00 SD ADC FIFO Data Read Register 0xXXXX_XXXX SDADC_EN...
Page 468: Register Description
ISD91500 Technical Reference Manual 5.19.6 Register Description SD ADC FIFO Data Register(SDADC_DAT) Register Offset Description Reset Value SDADC_DAT SDADC_BA+0x00 R SD ADC FIFO Data Read Register 0xXXXX_XXXX RESULT RESULT RESULT RESULT Bits Description Delta-Sigma ADC DATA FIFO Read A read of this register will read data from the audio FIFO and increment the read pointer. A read past...
Page 469 ISD91500 Technical Reference Manual SD ADC Enable Register(SDADC_EN) Register Offset Description Reset Value SDADC_EN SDADC_BA+0x04 R/W SD ADC Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved DINEDGE SDADCEN Bits Description [31:2] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 470 ISD91500 Technical Reference Manual SD ADC Clock Divider Register (SDADC_CLKDIV) Register Offset Description Reset Value SDADC_CLKDIV SDADC_BA+0x08 R/W SD ADC Clock Divider Register 0x0000_0000 Reserved Reserved Reserved CLKDIV Bits Description [31:8] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 471 ISD91500 Technical Reference Manual SD ADC Control Register (SDADC_CTL) Register Offset Description Reset Value SDADC_CTL SDADC_BA+0x0C R/W SD ADC Control Register 0x0000_0000 Reserved Reserved Reserved SPDS Reserved THIE FIFOTH FIFOBITS DSRATE Bits Description [31:13] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 472 ISD91500 Technical Reference Manual Down Sampling Ratio 00 = reserved [1:0] DSRATE 01 = down sample X 16 10 = down sample X 32 11 = down sample X 64 when SPDS = 0 or down sample X 62.5 when SPDS = 1 .
Page 473 ISD91500 Technical Reference Manual SD ADC FIFO Status Register(SDADC_FIFOSTS) Register Offset Description Reset Value SDADC_FIFOSTS SDADC_BA+0x10 R/W SD ADC FIFO Status Register 0x0000_0002 Reserved Reserved Reserved POINTER POINTER Reserved THIF EMPTY FULL Bits Description [31:9] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 474 ISD91500 Technical Reference Manual SD ADC PDMA Control Register(SDADC_PDMACTL) Register Offset Description Reset Value SDADC_PDMACTL SDADC_BA+0x14 R/W SD ADC PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMAEN Bits Description [31:1] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 475 ISD91500 Technical Reference Manual SD ADC Compare Register 0 (SDADC_CMPR0) Register Offset Description Reset Value SDADC_CMPR0 SDADC_BA+0x18 R/W SD ADC Comparator 0 Control Register 0x0000_0000 CMPOEN CMPD CMPD CMPD CMPMATCNT CMPF CMPCOND CMPIE ADCMPEN Bits Description Compare Match output FIFO zero...
Page 476 ISD91500 Technical Reference Manual Compare Enable 0 = Disable compare. ADCMPEN 1 = Enable compare. Set this bit to 1 to enable compare CMPDAT with FIFO data output. Feb. 21, 2023 Page 476 of 500 Rev 2.3...
Page 477 ISD91500 Technical Reference Manual SD ADC Compare Register 1 (SDADC_CMPR1) Register Offset Description Reset Value SDADC_CMPR1 SDADC_BA+0x1C R/W SD ADC Comparator 1 Control Register 0x0000_0000 CMPOEN CMPD CMPD CMPD CMPMATCNT CMPF CMPCOND CMPIE ADCMPEN Bits Description Compare Match output FIFO zero...
Page 478 ISD91500 Technical Reference Manual Compare Enable 0 = Disable compare. ADCMPEN 1 = Enable compare. Set this bit to 1 to enable compare CMPDAT with FIFO data output. Feb. 21, 2023 Page 478 of 500 Rev 2.3...
Page 479 ISD91500 Technical Reference Manual SD ADC Analog Block Control Register 0 (SDADC_ANA0) Register Offset Description Reset Value SDADC_ANA0 SDADC_BA+0x20 R/W SD ADC Analog Block Control Register 0 0x001C_9021 Reserved CHOPEN CHOPPH CHOPORD CHOPFIX CHOPCKPH CHOPF CHOPF Reserved CLASSA Reserved CMLCK...
Page 480 ISD91500 Technical Reference Manual [22:19] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value. Enable PGA Class A mode of operation [18] CLASSA 0 = Class AB 1 = Class A (default) [17:16] Reserved Reserved.
Page 481 ISD91500 Technical Reference Manual SD ADC Analog Block Control Register 1 (SDADC_ANA1) Register Offset Description Reset Value SDADC_ANA1 SDADC_BA+0x28 R/W SD ADC Analog Block Control Register 1 0x0000_2004 Reserved Reserved ACDC Reserved BSTPUP BSTMUTE BSTMODE Reserved Reserved DISCHRG CLASSAEN CMLCKEN...
Page 482 ISD91500 Technical Reference Manual BST Charge inputs selected by ACDC[1:0] to VMID DISCHRG 0 = Disable 1 = Enable CLASSAEN Default 0’b BST Common mode Threshold lock adjust enable CMLCKEN 0 = Enable 1 = Disable [1:0] CMLCKADJ Default 00’b Feb.
Page 483 ISD91500 Technical Reference Manual SD ADC Analog Block Control Register 2 (SDADC_ANA2) Register Offset Description Reset Value SDADC_ANA2 SDADC_BA+0x2C R/W SD ADC Analog Block Control Register 2 0x0000_0008 Reserved Reserved Reserved Reserved GAINSET Bits Description [31:5] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 484: Analog Functional Blocks (Ana)
ISD91500 Technical Reference Manual 5.20 Analog Functional Blocks (ANA) 5.20.1 Overview The device contains an analog functional blocks that facilitate audio processing. These blocks are controlled by registers in the analog block address space. This section describes these functions and registers.
Page 485: Figure 5.20-2 Micbias Block Diagram
ISD91500 Technical Reference Manual total resistance ( R ) is 4Kohms. MICBIAS output voltage should be such that the following �� > �� + ( �� + �� ) × �� condition is met: �� where V is the desired voltage across the microphone from specification and I is the current through the microphone (0.1-0.5mA)
Page 486: Register Map
ISD91500 Technical Reference Manual 5.20.4 Register Map R: read only, W: write only, R/W: read/write Register Offset Description Reset Value ANA Base Address: ANA_BA = 0x4008_0000 ANA_VMID ANA_BA+0x00 VMID Reference Control Register 0x0000_0077 ANA_MICBCTR Microphone Bias Control Register ANA_BA+0x04 0x0000_0000 Note: Any register not listed here is reserved and must not be written.
Page 487: Register Description
ISD91500 Technical Reference Manual 5.20.5 Register Description VMID Control Register (ANA_VMID) Register Offset Description Reset Value ANA_VMID ANA_BA+0x00 VMID Reference Control Register 0x0000_0077 Reserved Reserved Reserved Reserved VMIDLRH VMIDLRL VMIDLPD Reserved VMIDHRH VMIDHRL VMIDHPD Bits Description [31:7] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 488 ISD91500 Technical Reference Manual Power Down VMIDH Low Resistance Reference 0= Connect the Low Resistance reference to VMIDH. Use this setting for fast power up of VMIDH. VMIDHRL Can be turned off after 50ms to save power. 1= The Low Resistance reference is disconnected from VMIDH. Default power down and reset condition.
Page 489 ISD91500 Technical Reference Manual Microphone Bias Control (ANA_MICBCTR) Register Offset Description Reset Value ANA_MICBCTR ANA_BA+0x04 Microphone Bias Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MICBMODE MICBVSEL MICBEN Bits Description [31:4] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 490: Biquad Filter (Biq)
ISD91500 Technical Reference Manual 5.21 Biquad Filter (BIQ) 5.21.1 Overview A coefficient programmable 6-stage Biquad filter (12 -Order IIR filter) is available which can be used on either SDADC path to further reduce unwanted noise or filter the signal. 5.21.2 Features ...
Page 491 ISD91500 Technical Reference Manual 2. BIQ function work on 5 stages, set BIQ->BIQ_CTL.STAGE=1, BIQ function will call 25 coefficients from BIQ_BA+0x00 ~0x060 3. If 6 stage filter is on (BIQ->BIQ_CTL.SIXTHFON=1), BIQ function automatically set 6 stages. BIQ function will call 30 coefficients.
Page 492: Register Map
ISD91500 Technical Reference Manual 5.21.4 Register Map R: read only, W: write only, R/W: read/write Register Offset R/W Description Reset Value BIQ Base Address: BIQ_BA = 0x400B_0000 Coefficient b0 In H(z) Transfer Function BIQ_COEFF0 BIQ_BA+0x00 0x0000_0000 (3.16 format) - 1...
Page 493 ISD91500 Technical Reference Manual (3.16 format) - 4 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function BIQ_COEFF16 BIQ_BA+0x40 0x0000_0000 (3.16 format) - 4 stage BIQ Coefficients Coefficient b2 In H(z) Transfer Function BIQ_COEFF17 BIQ_BA+0x44 0x0000_0000 (3.16 format) - 4...
Page 494: Register Description
ISD91500 Technical Reference Manual 5.21.5 Register Description BIQ Coefficient Register (BIQ_COEFFn) Register Offset Description Reset Value Coefficient b0 In H(z) Transfer Function BIQ_COEFF0 BIQ_BA+0x00 0x0000_0000 (3.16 format) - 1 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function BIQ_COEFF1 BIQ_BA+0x04 0x0000_0000 (3.16 format) - 1...
Page 495 ISD91500 Technical Reference Manual (3.16 format) - 4 stage BIQ Coefficients Coefficient b2 In H(z) Transfer Function BIQ_COEFF17 BIQ_BA+0x44 0x0000_0000 (3.16 format) - 4 stage BIQ Coefficients Coefficient a1 In H(z) Transfer Function BIQ_COEFF18 BIQ_BA+0x48 0x0000_0000 (3.16 format) - 4...
Page 496 ISD91500 Technical Reference Manual COEFFDAT[7:0] Bits Description [31:0] COEFFDAT Coefficient Data Feb. 21, 2023 Page 496 of 500 Rev 2.3...
Page 497 ISD91500 Technical Reference Manual BIQ Control Register (BIQ_CTL) Register Offset Description Reset Value BIQ_CTL BIQ_BA+0x080 BIQ Control Register 0x0000_0110 Reserved Reserved Reserved STAGE Reserved PRGCOEFF SDADCWNSR DLCOEFF Reserved SIXTHFON BIQEN Bits Description [31:12] Reserved Reserved. Any values read should be ignored. When writing to this field always write with reset value.
Page 498 ISD91500 Technical Reference Manual stage Filter On/Off Control 0 = disable 6 stage filter. SIXTHFON 1 = enable 6 stage filter. Note1 : This register only work when STAGE set 5 stage. Note2 : SDADC path sixth stage coefficient is for this filter coefficient.
Page 499: Revision History
ISD91500 Technical Reference Manual REVISION HISTORY VERSION DATE DESCRIPTION NOTE Jul 1, 2021 Formal version release Add note for cache in FMC chapter Jul 30, 2021 Update to V2.0 for RevC 1.Update pin diagram & pin description chapter Oct 6, 2021 2.Update USB chapter...
Page 500 ISD91500 Technical Reference Manual Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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