Nuvoton ISD91300 Series Technical Reference Manual

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ISD91300 Series Technical Reference Manual

ISD ARM

Cortex

-M0 SoC

ISD91300 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of ISD91300 series microcontroller

based system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact:Nuvoton Technology Corporation.

www.nuvoton.com

Sep 9, 2019

Page 1 of 466

Revision 1.13

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Summary of Contents for Nuvoton ISD91300 Series

Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of ISD91300 series microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2: Table Of Contents
ISD91300 Series Technical Reference Manual TABLE OF CONTENTS LIST OF FIGURES ................... 8 LIST OF TABLES ..................... 12 1 GENERAL DESCRIPTION ................... 13 2 FEATURES ......................14 3 ABBREVIATIONS ....................18 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ........ 19 4.1 ISD91300 Product Selection Guide ............
Page 3 ISD91300 Series Technical Reference Manual 6.4.2 Features ....................113 6.4.3 Basic Configuration .................. 113 6.4.4 Functional Description ................114 6.4.5 Register Map ..................117 6.4.6 Register Description ................. 118 6.5 Brownout Detection and Temperature Alarm ..........129 6.5.1 Overview ....................129 6.5.2 Register Map ..................
Page 4 ISD91300 Series Technical Reference Manual 6.9.5 Timing Diagram ..................233 6.9.6 Programming Examples ................235 6.9.7 Register Map ..................237 6.9.8 Register Description ................. 238 6.10 Timer Controller (TIMER) ..............253 6.10.1 Overview ....................253 6.10.2 Features ....................253 6.10.3 Block Diagram ..................254 6.10.4 Functional Description ................
Page 5 ISD91300 Series Technical Reference Manual 6.14.3 Block Diagram ..................318 6.14.4 Functional Description ................320 6.14.5 Register Map ..................322 6.14.6 Register Description ................. 325 7 FLASH MEMORY CONTROLLER (FMC) ............353 7.1 Overview ..................353 7.2 Features ..................353 7.3 Block Diagram ..................
Page 6 ISD91300 Series Technical Reference Manual 8.3.4 Functional Description ................393 8.3.5 Register Map ..................394 8.3.6 Register Description ................. 395 8.4 Analog Functional Blocks ..............399 8.4.1 Overview ....................399 8.4.2 Features ....................399 8.4.3 VMID Reference Voltage Generation ............399 8.4.4 GPIO Current Source Generation ..............
Page 7 ISD91300 Series Technical Reference Manual 10.3 AC Electrical Characteristics ..............455 10.3.1 External 32kHz XTAL Oscillator ..............455 10.3.2 Internal 49.152MHz Oscillator ..............455 10.3.3 Internal 16kHz Oscillator ................455 10.4 Analog Characteristics ................. 456 10.4.1 Specification of ADC and Speaker Driver............456 10.4.2 ADC Filter Characteristics ................
Page 8 ISD91300 Series Technical Reference Manual LIST OF FIGURES Figure 4-1 ISD91300 Series Selection Code ................. 19 Figure 4-2 ISD91300 LQFP 64-pin Diagram .................. 20 Figure 5-1 ISD91300 Block Diagram ..................... 26 Figure 6-1 Functional Controller Diagram ..................27 Figure 6-2 ISD91300 Power Distribution Diagram ................. 30 Figure 6-3 Clock Generator Block Diagram ...................
Page 9 ISD91300 Series Technical Reference Manual Figure 6-34 SPI Block Diagram ....................221 Figure 6-35 SPI Master Mode Application Block Diagram ............222 Figure 6-36 SPI Slave Mode Application Block Diagram ............. 222 Figure 6-37 32-Bit in One Transaction ..................223 Figure 6-38 Word Sleep Suspend Mode ..................
Page 10 ISD91300 Series Technical Reference Manual Figure 6-71 MSB Justified Data Format Timing Diagram ............300 Figure 6-72 FIFO Contents for Various I S Modes ..............302 Figure 6-73 Master Mode Interface ....................303 Figure 6-74 Slave Mode Interface ....................303 Figure 6-75 DMA Controller Block Diagram .................
Page 11 ISD91300 Series Technical Reference Manual Figure 9-1 Application Diagram ....................449 Figure 10-1 Operating Current Curve ..................454 Figure 10-2 ADC Filter Characteristics ..................457 Figure 10-3 ADC Filter Characteristics Zoom In ................458 Sep 9, 2019 Page 11 of 466...
Page 12: List Of Tables
ISD91300 Series Technical Reference Manual LIST OF TABLES Table 3-1 List of Abbreviations ....................... 18 Table 6-1 Address Space Assignments for On-Chip Controllers ........... 32 Table 6-2 Exception Model ......................57 Table 6-3 System Interrupt Map ..................... 58 Table 6-4 Vector Table Format ...................... 59 Table 6-5 I C Status Code Description ..................
Page 13: General Description
GPIO, Analog Comparator, Low Voltage Detector and Brown-out detector. The ISD91300 series comes equipped with a rich set of power saving modes including a Deep Power Down (DPD) mode drawing less than 1µA. A micro-power 16KHz oscillator can periodically wake up the device from deep power down to check for other events.
Page 14: Features
ISD91300 Series Technical Reference Manual FEATURES The equipped features are dependent on the product line and their sub products.  Core – ARM® Cortex™-M0 core running up to 98.304MHz. – One 24-bit System tick timer for operating system support. –...
Page 15 ISD91300 Series Technical Reference Manual – I/O pin can be configured as interrupt source with edge/level setting. – Switchable pull-up.  Audio Analog to Digital converter – Sigma Delta ADC with configurable decimation filter and 16 bit output. – 90dB Signal-to-Noise (SNR) performance.
Page 16 ISD91300 Series Technical Reference Manual – Programmable baud-rate generator up to 1/16 of system clock.  SPI – SPI Clock up to 24MHz. – SPI data rate in Quad mode of 98 Mbps. – Support MICROWIRE/SPI master/slave mode (SSP). –...
Page 17 ISD91300 Series Technical Reference Manual temperature. – Temperature proportional voltage source which can be routed to ADC for temperature measurements. – Digital Microphone interface.  Operating Temperature: -40℃~85℃  Packages: – All Green package (RoHS). – LQFP 64-pin. Sep 9, 2019 Page 17 of 466 Revision 1.13...
Page 18: Abbreviations
ISD91300 Series Technical Reference Manual ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection FIFO First In, First Out Flash Memory Controller GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus...
Page 19: Parts Information List And Pin Configuration
Package R: LQFP-64 Family ID 3: Family Series ID SW Feature Blank: Standard Flash ROM C: Voice Recognition 3: 64+4KB 6: 145KB SRAM 1: 16KB Figure 4-1 ISD91300 Series Selection Code Sep 9, 2019 Page 19 of 466 Revision 1.13...
Page 20: Pin Configuration
ISD91300 Series Technical Reference Manual 4.2 Pin Configuration 4.2.1 ISD91300 Pin Diagram 4.2.1.1 ISD91300 LQFP 64 pin WAKEUP VCCLDO PA.0/SPI_MOSI0/MCLK CMP11/I2S_SDO/PB.11 CMP10/PB.10 PA.1/SPI_SCLK/I2C_SCL PB.12/SPI_MISO1/PWM1CH0/PWM1CH1_INV CMP9/I2S_BCLK/PB.9 CMP8/I2S_FS/PB.8 VDD33 PA.2/SPI_SSB0 CMP7/I2S_SDO/PB.7 PA.3/SPI_MISO0/I2C_SDA SPI_MOSI1/CMP6/I2S_SDI/PB.6 LQFP 64-pin PB.13/SPI_MOSI1/PWM1CH1/PWM1CH0_INV SPI_MISO1/CMP5/PWM0CH1_INV/PB.5 PA.4/I2S_FS SPI_MOSI0/CMP4/PWM0CH0_INV/PB.4 PA.5/I2S_BCLK/SPI_SSB1 SPI_MISO0/CMP3/I2C_SDA/PB.3 PA.6/I2S_SDI/UART_TX SPI_SCLK/CMP2/I2C_SCL/PB.2...
Page 21: Pin Description
ISD91300 Series Technical Reference Manual 4.3 Pin Description 4.3.1 ISD91300 Pin Description Pin No. Pin Name Pin Type Alt CFG Description (LQFP 64) WAKEUP Pull low to wake part from deep power down PB.11 A/I/O General purpose input/output pin, analog capable; Port B, bit 11...
Page 22 ISD91300 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description (LQFP 64) SPI_MISO0 Master In, Slave Out channel 0 for SPI interface A/I/O PB.2 General purpose input/output pin, analog capable; Port B, bit 2 I2C_SCL Serial Clock, I2C interface...
Page 23 ISD91300 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description (LQFP 64) VSSSPK Ground for PWM Speaker Driver SPK- Negative Speaker Driver Output VCCSPK Power Supply for PWM Speaker Driver External reset input. Pull this pin low to reset device to initial state.
Page 24 ISD91300 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description (LQFP 64) SPI_SSB0 Slave Select Bar 0 for SPI interface LDO Regulator Output. If used, a 1µF capacitor must be placed to VDD33 ground. If not used then tie to VCCD.
Page 25 ISD91300 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description (LQFP 64) VCCA Analog power supply. PA.11 General purpose input/output pin; Port A, bit 11 I2C_SCL Serial Clock, I2C interface I2S_SDO Serial Data Out I2S interface UART_CTSn UART Clear to Send Input.
Page 26: Block Diagram
ISD91300 Series Technical Reference Manual BLOCK DIAGRAM 5.1 ISD91300 Block Diagram 50MHz Internal Osc. CLK CTRL Debug interface 32kHz RTC Osc 10kHz low power Embedded Cortex M0 Flash 16KB 68/100/145KB AHB Lite Peripherals with PDMA LDO 3.0V GPIO PDMA LDO 1.8V...
Page 27: Functional Description
ISD91300 Series Technical Reference Manual FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex™-M0 Core The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex™-M profile processor.
Page 28 ISD91300 Series Technical Reference Manual  NVIC: 32 external interrupt inputs, each with four levels of priority Dedicated Non-maskable Interrupt (NMI) input Supports for both level-sensitive and pulse-sensitive interrupt lines Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode ...
Page 29: System Manager
ISD91300 Series Technical Reference Manual 6.2 System Manager 6.2.1 Overview System management includes thefollowing sections:  System Resets  System Memory Map  System management registersfor Product ID, chip reset and on-chip controllers reset , multi-functional pin control  System Timer (SysTick) ...
Page 30: System Power Distribution
ISD91300 Series Technical Reference Manual 6.2.3 System Power Distribution The ISD91300 implements several power domains:  Analog power from VCCA and VSSA provides the power for analog module operation.  Digital power from VCCD and VSSD supplies the power to the IO ring and the internal regulator which provides 1.8V power for digital operation.
Page 31: System Memory Map
ISD91300 Series Technical Reference Manual 6.2.4 System Memory Map The ISD91300 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip peripheral. The ISD91300 series only supports little-endian data format.
Page 32: Table 6-1 Address Space Assignments For On-Chip Controllers
ISD91300 Series Technical Reference Manual System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SYSTICK_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SYSINFO_BA System Control Registers Table 6-1 Address Space Assignments for On-Chip Controllers...
Page 33: Register Map
ISD91300 Series Technical Reference Manual 6.2.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYS Base Address: SYS_BA = 0x5000_0000 SYS_PDID SYS_BA+0x00 Product ID 0xXXXX_XXXX SYS_RSTSTS SYS_BA+0x04 System Reset Source Register...
Page 34: Register Description
ISD91300 Series Technical Reference Manual 6.2.6 Register Description Part Device ID Code Register (PDID) This register provides specific read-only information for software to identify this chip. Register Offset Description Reset Value SYS_PDID SYS_BA+0x00 Product ID 0xXXXX_XXXX PDID[31:24] PDID[23:16] PDID[15:8] PDID[7:0]...
Page 35 ISD91300 Series Technical Reference Manual System Reset Source Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Source Register 0x0000_00XX Reserved Reserved...
Page 36 ISD91300 Series Technical Reference Manual This bit is cleared by writing 1 to itself. Reset Source From PMU The PMURSTF flag is set if the PMU. PMURSTF 0= No reset from PMU. 1= PMU reset the system from a power down/standby event.
Page 37 ISD91300 Series Technical Reference Manual IP Reset Control Register1(SYS_IPRST0) Register Offset Description Reset Value SYS_IPRST0 SYS_BA+0x08 IP Reset Control Resister0 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST CPURST CHIPRST Bits Description [31:3] Reserved Reserved. PDMA Controller Reset Set “1” will generate a reset signal to the PDMA Block. User needs to set this bit to “0” to...
Page 38 ISD91300 Series Technical Reference Manual IP Reset Control Register1 (SYS_IPRST1) Setting these bits “1” will generate an asynchronous reset signal to the corresponding peripheral block. The user needs to set bit to “0” to release block from the reset state.
Page 39 ISD91300 Series Technical Reference Manual UART0 Controller Reset [16] UART0RST 0=Normal Operation. 1=Reset. DPWM Speaker Driver Reset [13] DPWMRST 0=Normal Operation. 1=Reset. SPI0 Controller Reset [12] SPI0 RST 0=Normal Operation. 1=Reset. I2C0 Controller Reset I2C0RST 0=Normal Operation. 1=Reset. Timer1 Controller Reset TMR1RST 0=Normal Operation.
Page 40 ISD91300 Series Technical Reference Manual GPIOA Input Type Control Register (SYS_PASMTEN) Register Offset Description Reset Value SYS_PASMTEN SYS_BA+0x30 GPIOA input type control register 0x0000_0000 SMTEN [15:8] SMTEN [7:0] Reserved Reserved Bits Description Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
Page 41 ISD91300 Series Technical Reference Manual GPIOB Input Type Control Register (SYS_PBSMTEN) Register Offset Description Reset Value SYS_PBSMTEN SYS_BA+0x34 GPIOB input type control register 0x0000_0000 Reserved SMTEN [7:0] Reserved Reserved Bits Description Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
Page 42 ISD91300 Series Technical Reference Manual GPIO Alternative Function Control Register (SYS_GPA_MFP, SYS_GPB_MFP) Each GPIO pin can take on multiple alternate functions depending on the setting of this register. Each pin has two bits of alternate function control. Set to 00 the pin is a standard GPIO pin whose attributes are defined by the GPIO control registers.
Page 43 ISD91300 Series Technical Reference Manual 01 = I2C_SCL. 10 = CMP15. 11 = UART_CTSn. Alternate Function Setting For PA10MFP 00 = GPIO. [21:20] PA10MFP 01 = I2C_SDA. 10 = CMP14. 11 = UART_RTSn. Alternate Function Setting For PA9MFP 00 = GPIO.
Page 44 ISD91300 Series Technical Reference Manual 01 = SPI_MOSI0. 10 = MCLK. Register Offset Description Reset Value SYS_GPB_MFP SYS_BA+0x3C GPIOB multiple alternatefunctions control register 0x0000_0000 PB15MFP PB14MFP PB13MFP PB12MFP PB11MFP PB10MFP PB9MFP PB8MFP PB7MFP PB6MFP PB5MFP PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP...
Page 45 ISD91300 Series Technical Reference Manual Alternate Function Setting For PB10MFP [21:20] PB10MFP 00 = GPIO. 10 = CMP10. Alternate Function Setting For PB9MFP 00 = GPIO. [19:18] PB9MFP 01 = I2S_BCLK(master). 10 = CMP9. Alternate Function Setting For PB8MFP 00 = GPIO.
Page 46 ISD91300 Series Technical Reference Manual Alternate Function Setting For PB0MFP 00 = GPIO. [1:0] PB0MFP 01 = SPI_SSB1. 10 = CMP0. 11 = SPI_SSB0. GPAn=01 GPAn =10 GPAn =11 GPIO Power Domain Function Type Function Type Function Type GPIOA0 VDD33...
Page 47 ISD91300 Series Technical Reference Manual GPIOB6 VCCD I2S_SDI CMP6 SPI_MOSI1 GPIOB7 VCCD I2S_SDO CMP7 GPIOB8 VCCD I2S_FS(master) CMP8 GPIOB9 VCCD I2S_BCLK (master) CMP9 GPIOB10 VCCD CMP10 GPIOB11 VCCD I2S_SDO CMP11 GPIOB12 VDD33 SPI_MISO1 PWM1CH0 PWM1CH1_INV GPIOB13 VDD33 SPI_MOSI1 PWM1CH1 PWM1CH0_INV...
Page 48 ISD91300 Series Technical Reference Manual Wakeup Pin Control Register (SYS_WKCTL) The WAKEUP pin of the ISD91300 is a special purpose pin that can be used to wake the device from a deep power down condition when all other pins of the device are inactive. When the device is active, this register can be used to set the state of the WAKEUP pin.
Page 49 ISD91300 Series Technical Reference Manual Protected Register Lock Key Register (SYS_REGLCTL) Certain critical system control registers are protected against inadvertent write operations which may disturb chip operation. These system control registers are locked after power on reset until the user specifically issues an unlock sequence to open the lock.
Page 50 ISD91300 Series Technical Reference Manual Oscillator Trim Control Register (SYS_IRCTCTL) The master oscillator of the ISD91300 has an adjustable frequency and is controlled by the SYS_IRCTCTL register. This register contains two oscillator frequency trim values, which one is active depends upon the setting of register CLK_CLKSEL0_HIRCFSEL bit. If this bit is 0, SYS_IRCTCTL[0] is active, if 1 then SYS_IRCTCTL[1] is active.
Page 51: System Timer (Syst)
ISD91300 Series Technical Reference Manual 6.2.7 System Timer (SYST) The Cortex-M0 includes an integrated system timer, SYST. SYST provides a simple, 24-bit,Clear- on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ...
Page 52 ISD91300 Series Technical Reference Manual 6.2.7.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYSTICK Base Address: SYSTICK_BA = 0xE000_E000 SYST_CSR SYSTICK_BA+ 0x10 SYST Control and Status Register...
Page 53 ISD91300 Series Technical Reference Manual 6.2.7.2 System Timer Control Register Description SysTick Control and Status (SYST_CSR) Register Offset Description Reset Value SYST_CSR SYSTICK_BA + 0x10 SYST Control and Status Register 0x0000_0004 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits...
Page 54 ISD91300 Series Technical Reference Manual SYST Reload Value Register（SYST_RVR） Register Offset Description Reset Value SYST_RVR SYSTICK_BA + 0x14 SYST Reload Value Register 0xXXXX_XXXX Reserved RELOAD[23:16] RELOAD[15:8] RELOAD[7:0] Bits Description [31:24] Reserved Reserved. SYST Reload Value to load into the Current Value register when the counter reaches 0.
Page 55 ISD91300 Series Technical Reference Manual SYST Current Value Register（SYST_CVR） Register Offset Description Reset Value SYST_CVR SYSTICK_BA + 0x18 SYST Current Value Register 0xXXXX_XXXX Reserved CURRENT[23:16] CURRENT[15:8] CURRENT[7:0] Bits Description Reserved [31:24] Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The...
Page 56: Nested Vectored Interrupt Controller (Nvic)
ISD91300 Series Technical Reference Manual 6.2.8 Nested Vectored Interrupt Controller (NVIC) The Cortex™-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel and provides following features: ...
Page 57: Table 6-2 Exception Model
ISD91300 Series Technical Reference Manual 6.2.8.1 Exception Modeland System Interrupt Map The following table lists the exception model supported by ISD91300 series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user- configurable priority is denoted as “0”...
Page 58: Table 6-3 System Interrupt Map
ISD91300 Series Technical Reference Manual Reserved Reserved Reserved I2C0_IRQn I2C0 I2C0 interrupt Reserved Reserved TALARM_IRQn TALARM Temperature Alarm Interrupt Reserved Reserved Reserved ACMP_IRQn ACMP Analog Comparator-0 or Comaprator-1 interrupt PDMA_IRQn PDMA PDMA interrupt I2S_IRQn I2S interrupt CAPS_IRQn CapSense Relaxation Oscillator Interrupt...
Page 59: Table 6-4 Vector Table Format
ISD91300 Series Technical Reference Manual 6.2.8.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers.
Page 60 ISD91300 Series Technical Reference Manual 6.2.8.4 NVIC Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NVIC Base Address: SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register...
Page 61 ISD91300 Series Technical Reference Manual 6.2.8.5 NVIC Control Register Description IRQ0 ~ IRQ31 Set-Enable Control Register (NVIC_ISER) Register Offset Description Reset Value NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 SETENA[31:24] SETENA[23:16] SETENA[15:8] SETENA[7:0] Bits Description Interrupt Enable Register Enable one or more interrupts.
Page 62 ISD91300 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 CLRENA[31:24] CLRENA[23:16] CLRENA[15:8] CLRENA[7:0] Bits Description Interrupt Disable Bits Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 63 ISD91300 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x200 IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 SETPEND[31:24] SETPEND[23:16] SETPEND[15:8] SETPEND[7:0] Bits Description Set Interrupt Pending Register Write Operation: 0 = No effect.
Page 64 ISD91300 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x280 IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CLRPEND[31:24] CLRPEND[23:16] CLRPEND[15:8] CLRPEND[7:0] Bits Description Clear Interrupt Pending Register Write Operation: 0 = No effect.
Page 65 ISD91300 Series Technical Reference Manual IRQ0 ~ IRQ3 PriorityRegister (NVIC_IPR0) Register Offset Description Reset Value NVIC_IPR0 SCS_BA+0x400 IRQ0 ~ IRQ3 Priority Control Register 0x0000_0000 PRI_3[1:0] Reserved PRI_2[1:0] Reserved PRI_1[1:0] Reserved PRI_0[1:0] Reserved Bits Description Priority Of IRQ3 PRI_3 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 66 ISD91300 Series Technical Reference Manual IRQ4 ~ IRQ7 PriorityRegister (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 SCS_BA+0x404 IRQ4 ~ IRQ7 Priority Control Register 0x0000_0000 PRI_7[1:0] Reserved PRI_6[1:0] Reserved PRI_5[1:0] Reserved PRI_4[1:0] Reserved Bits Description Priority Of IRQ7 PRI_7 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 67 ISD91300 Series Technical Reference Manual IRQ8 ~ IRQ11 PriorityRegister (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 SCS_BA+0x408 IRQ8 ~ IRQ11 Priority Control Register 0x0000_0000 PRI_11[1:0] Reserved PRI_10[1:0] Reserved PRI_9[1:0] Reserved PRI_8[1:0] Reserved Bits Description Priority Of IRQ11 PRI_11[1:0] [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 68 ISD91300 Series Technical Reference Manual IRQ12 ~ IRQ15 PriorityRegister (NVIC_IPR3) Register Offset Description Reset Value NVIC_IPR3 SCS_BA+0x40C IRQ12 ~ IRQ15 Priority Control Register 0x0000_0000 PRI_15[1:0] Reserved PRI_14[1:0] Reserved PRI_13[1:0] Reserved PRI_12[1:0] Reserved Bits Description Priority Of IRQ15 PRI_15 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 69 ISD91300 Series Technical Reference Manual IRQ16 ~ IRQ19 PriorityRegister (NVIC_IPR4) Register Offset Description Reset Value NVIC_IPR4 SCS_BA+0x410 IRQ16 ~ IRQ19 Priority Control Register 0x0000_0000 PRI_19[1:0] Reserved PRI_18[1:0] Reserved PRI_17[1:0] Reserved PRI_16[1:0] Reserved Bits Description Priority Of IRQ19 PRI_19 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 70 ISD91300 Series Technical Reference Manual IRQ20 ~ IRQ23 PriorityRegister (NVIC_IPR5) Register Offset Description Reset Value NVIC_IPR5 SCS_BA+0x414 IRQ20 ~ IRQ23 Priority Control Register 0x0000_0000 PRI_23[1:0] Reserved PRI_22[1:0] Reserved PRI_21[1:0] Reserved PRI_20[1:0] Reserved Bits Description Priority Of IRQ23 PRI_23 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 71 ISD91300 Series Technical Reference Manual IRQ24 ~ IRQ27 PriorityRegister (NVIC_IPR6) Register Offset Description Reset Value NVIC_IPR6 SCS_BA+0x418 IRQ24 ~ IRQ27 Priority Control Register 0x0000_0000 PRI_27[1:0] Reserved PRI_26[1:0] Reserved PRI_25[1:0] Reserved PRI_24[1:0] Reserved Bits Description Priority Of IRQ27 PRI_27 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 72 ISD91300 Series Technical Reference Manual IRQ28 ~ IRQ31 PriorityRegister (NVIC_IPR7) Register Offset Description Reset Value NVIC_IPR7 SCS_BA+0x41C IRQ28 ~ IRQ31 Priority Control Register 0x0000_0000 PRI_31[1:0] Reserved PRI_30[1:0] Reserved PRI_29[1:0] Reserved PRI_28[1:0] Reserved Bits Description Priority Of IRQ31 PRI_31 [31:30] “0” denotes the highest priority and “3” denotes the lowest priority.
Page 73 ISD91300 Series Technical Reference Manual 6.2.8.6 Interrupt Source Register Map Besides the interrupt control registers associated with the NVIC, the ISD91300 series also implement some specific control registers to facilitate the interrupt functions, including “interrupt source identification”, ”NMI source selection” and “interrupt test mode”, which are described below.
Page 74 ISD91300 Series Technical Reference Manual IRQ23_SRC INT_BA+0x5C IRQ23 (RESERVED) Interrupt Source Identity Register 0xXXXX_XXXX IRQ24_SRC INT_BA+0x60 IRQ24 (RESERVED) Interrupt Source Identity Register 0xXXXX_XXXX IRQ25_SRC INT_BA+0x64 IRQ25 (ACMP) Interrupt Source Identity Register 0xXXXX_XXXX IRQ26_SRC INT_BA+0x68 IRQ26 (PDMA) Interrupt Source Identity Register...
Page 75 ISD91300 Series Technical Reference Manual 6.2.8.7 Interrupt Source Register Description Interrupt Source IdentityRegister (IRQn_SRC) Register Offset Description Reset Value IRQ0_SRC INT_BA+0x00 IRQ0 (BOD) Interrupt Source Identity Register 0xXXXX_XXXX IRQ1_SRC INT_BA+0x04 IRQ1 (WDT) Interrupt Source Identity Register 0xXXXX_XXXX IRQ2_SRC INT_BA+0x08 IRQ2 (EINT0) Interrupt Source Identity Register...
Page 76 ISD91300 Series Technical Reference Manual IRQ27_SRC INT_BA+0x6C IRQ27 (I2S) Interrupt Source Identity Register 0xXXXX_XXXX IRQ28_SRC INT_BA+0x70 IRQ28 (CAPS) Interrupt Source Identity Register 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74 IRQ29 (ADC) Interrupt Source Identity Register 0xXXXX_XXXX IRQ30_SRC INT_BA+0x78 IRQ30 (RESERVED) Interrupt Source Identity Register...
Page 77 ISD91300 Series Technical Reference Manual Bit1: 0 Bit0: ALC_INT Bit2: 0 [2:0] INT_BA+0x18 Bit1: 0 Bit0: PWM0_INT Bit2: 0 [2:0] INT_BA+0x1C Bit1: 0 Bit0: PWM1_INT Bit2: 0 [2:0] INT_BA+0x20 Bit1: 0 Bit0: TMR0_INT Bit2: 0 [2:0] INT_BA+0x24 Bit1: 0 Bit0: TMR1_INT...
Page 78 ISD91300 Series Technical Reference Manual Bit2: 0 [2:0] INT_BA+0x54 Bit1: 0 Bit0: TALARM_INT Bit2: 0 [2:0] INT_BA+0x58 Bit1: 0 Bit0: 0 Bit2: 0 [2:0] INT_BA+0x5C Bit1: 0 Bit0: 0 Bit2: 0 [2:0] INT_BA+0x60 Bit1: 0 Bit0: 0 Bit2: 0 [2:0]...
Page 79 ISD91300 Series Technical Reference Manual NMI Source InterruptSelect Control Register (NMI_SEL) Register Offset Description Reset Value NMI_SEL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_0000 Reserved Reserved Reserved IRQ_TM Reserved Reserved NMI_SEL[4:0] Bits Description Reserved [31:8] Reserved. IRQ Test Mode...
Page 80 ISD91300 Series Technical Reference Manual MCU InterruptRequest Source Register (MCU_IRQ) Register Offset Description Reset Value MCU_IRQ INT_BA+0x84 MCU IRQ Number Identify Register 0x0000_0000 MCU_IRQ[31:24] MCU_IRQ[23:16] MCU_IRQ[15:8] MCU_IRQ[7:0] Bits Description MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex™-M0.
Page 81: System Control
ISD91300 Series Technical Reference Manual 6.2.9 System Control The Cortex™-M0 status and operating mode control are managed by System Control Registers. Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be controlled through these system control registers. ® For more detailed information, please refer to the “ARM Cortex™-M0 Technical Reference...
Page 82 ISD91300 Series Technical Reference Manual 6.2.9.2 System Control Register Description CPUID Base Register (SYSCTL_CPUID) Register Offset R/W Description Reset Value SYSCTL_CPUID SYSINFO_BA+0xD00 R CPUID Base Register 0x410C_C200 IMPCODE[7:0] Reserved PART[3:0] PARTNO[11:4] PARTNO[3:0] REVISION[3:0] Bits Description Implementer Code Assigned By ARM...
Page 83 ISD91300 Series Technical Reference Manual Interrupt Control State Register (SYSCTL_ICSR) Register Offset R/W Description Reset Value SYSCTL_ICSR SYSINFO_BA+0xD04 R/W Interrupt Control State Register 0x0000_0000 NMIPNSET Reserved PPSVISET PPSVICLR PSTKISET PSTKICLR Reserved ISRPREEM ISRPEND Reserved VTPNDING[8:4] VTPEND[3:0] Reserved Reserved Reserved VTACT[8]...
Page 84 ISD91300 Series Technical Reference Manual Application Interrupt and Reset Control Register (SYSCTL_AIRCTL) Register Offset R/W Description Reset Value SYSCTL_AIRCTL SYSINFO_BA+0xD0C R/W Application Interrupt and Reset Control Register 0x0000_0000 VTKEY [15:8] VTKEY [7:0] ENDIANES Reserved Reserved SRSTREQ CLRACTVT Reserved Bits Description...
Page 85 ISD91300 Series Technical Reference Manual System Control Register (SYSCTL_SCR) Register Offset R/W Description Reset Value SYSCTL_SCR SYSINFO_BA+0xD10 R/W System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLPDEEP SLPONEXC Reserved Bits Description Reserved [31:5] Reserved. Send Event On Pending Bit 0 = only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded.
Page 86 ISD91300 Series Technical Reference Manual System Handler Priority Register2 (SYSCTL_SHPR2) Register Offset R/W Description Reset Value SYSCTL_SHPR2 SYSINFO_BA+0xD1C R/W System Handler Priority Register 2 0x0000_0000 PRI11[1:0] Reserved Reserved Reserved Reserved Bits Description Priority Of System Handler 11 – SVCall PRI11 [31:30] “0”...
Page 87 ISD91300 Series Technical Reference Manual System Handler Priority Register3 (SYSCTL_SHPR3) Register Offset R/W Description Reset Value SYSCTL_SHPR3 SYSINFO_BA+0xD20 R/W System Handler Priority Register 3 0x0000_0000 PRI15[1:0] Reserved PRI14[1:0] Reserved Reserved Reserved Bits Description Priority Of System Handler 15 –SYST [31:30] PRI15 “0”...
Page 88: Clock Controller And Power Management Unit (Pmu)
ISD91300 Series Technical Reference Manual 6.3 Clock Controller and Power Management Unit (PMU) 6.3.1 Overview The clock controller generates the clock sources for the whole device, including all AMBA interface modules and all peripheral clocks. Clock gating is provided on all peripheral clocks to minimize power consumption.
Page 89: System Clock &Syst Clock
ISD91300 Series Technical Reference Manual 6.3.2 System Clock &SYST Clock The system clock has 4 clock sources from clock generator block. The clock source switch depends on the register HCLKSEL(CLK_CLKSEL0[2:0]). The clock is then divided by HCLK_N+1 to produce the master clock for the device. Note that CLK2X source is only available on M and H speed grade devices of the series.
Page 90: Peripheral Clocks
ISD91300 Series Technical Reference Manual 6.3.3 Peripheral Clocks Each peripheral has a selectable clock gate. The register CLK_APBCLK0 determines whether the clock is active for each peripheral. In addition, the CLK_SLEEP register determines whether these clocks remain on during M0 sleep mode. Certain peripheral clocks have selectable sources these are controlled by the CLK_CLKSEL1 &CLK_CLKSEL2 register.
Page 91: Power Management
ISD91300 Series Technical Reference Manual 6.3.4 Power Management The ISD91300 is equipped with a Power Management Unit (PMU) that implements a variety of power saving modes. There are four levels of power control with increasing functionality (and power consumption): ...
Page 92 ISD91300 Series Technical Reference Manual 6.3.4.1 Level0: Deep Power Down (DPD) Deep Power Down (DPD) is the lowest power state the device can obtain. In this state there is no power provided to the logic domain and power consumption is only from the higher voltage chip supply domain.
Page 93 ISD91300 Series Technical Reference Manual 6.3.4.2 Level1: Standby Power Down (SPD) mode Standby Power Down mode is the lowest power state that some logic operation can be performed. In this mode power is removed from the majority of the core logic, including the Cortex-M0 and main RAM.
Page 94 ISD91300 Series Technical Reference Manual 6.3.4.3 Level2: Deep Sleep mode The Deep Sleep mode is the lowest power state where the Cortex-M0 and all logic state are preserved. In Deep Sleep mode the CLK48M oscillator is shut down and a low speed oscillator is selected, if CLK32K is active this source is selected, if not then CLK16K is enabled and selected.
Page 95 ISD91300 Series Technical Reference Manual 6.3.4.4 Level3: Sleep mode The Sleep mode gates all clocks to the Cortex-M0 eliminating dynamic power in the core. In addition, clocks to peripherals are gated according to the CLK_SLEEP register. The mode is entered by executing a WFI/WFE instruction and is released when an event occurs. Peripheral functions, including PDMA can be continued while in Sleep mode.
Page 96: Register Map
ISD91300 Series Technical Reference Manual 6.3.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLKBase Address: CLK_BA = 0x5000_0200 CLK_PWRCTL CLK_BA + 0x00 System Power Control Register 0xXX00_0006 CLK_AHBCLK CLK_BA + 0x04...
Page 97: Register Description
ISD91300 Series Technical Reference Manual 6.3.6 Register Description System Power Control Register （CLK_PWRCTL） This is a protected register, to write to register, first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)). Register Offset Description Reset Value CLK_PWRCTL...
Page 98 ISD91300 Series Technical Reference Manual 1 = disabled. Wakeup Pin Enabled Control Determines whether WAKEUP pin is enabled in DPD mode. [16] WKPINEN 0=enabled. 1=disabled. [15:12] Reserved Reserved. Deep Power Down (DPD) Bit DPDEN [11] Set to ‘1’ and issue WFI/WFE instruction to enter DPD mode.
Page 99 ISD91300 Series Technical Reference Manual AHB Device Clock Enable Control Register （CLK_AHBCLK） These register bits are used to enable/disable the clock source for AHB (Advanced High-Performance Bus) blocks. This is a protected register, to write to register, first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)).
Page 100 ISD91300 Series Technical Reference Manual APB Device Clock Enable Control Register （CLK_APBCLK0） These register bits are used to enable/disable clocks for APB (Advanced Peripheral Bus) peripherals. To enable the clocks write ‘1’ to the appropriate bit. To reduce power consumption and disable the peripheral, write ‘0’...
Page 101 ISD91300 Series Technical Reference Manual PWM0CH0 And PWM0CH1 Block Clock Enable Control [20] PWM0CH01CKEN 0=Disable. 1=Enable. Cyclic Redundancy Check Block Clock Enable Control [19] CRCCKEN 0=Disable. 1=Enable. BiquadFilter And Automatic Level Control Block Clock Enable Control [18] BFALCKEN 0=Disable. 1=Enable.
Page 102 ISD91300 Series Technical Reference Manual DPD State Register （CLK_DPDSTATE） The Deep Power Down State register is a user settable register that is preserved during Deep Power Down (DPD). Software can use this register to store a single byte during a DPD event. The DPDSTSRD register reads back the current state of the CLK_DPDSTATE register.
Page 103 ISD91300 Series Technical Reference Manual Clock Source Select Control Register 0 （CLK_CLKSEL0） Register Offset Description Reset Value CLK_CLKSEL0 CLK_BA + 0x10 R/W Clock Source Select Control Register 0 0x0000_0038 Reserved Reserved Reserved HIRCFSEL STCLKSEL HCLKSEL Bits Description Reserved [31:8] Reserved.
Page 104 ISD91300 Series Technical Reference Manual Clock Source Select Control Register 1（CLK_CLKSEL1） Clock multiplexors are a glitch free design to ensure smooth transitions between asynchronous clock sources. As such, both the current clock source and the target clock source must be enabled for switching to occur.
Page 105 ISD91300 Series Technical Reference Manual 1xx = clock source from internal OSC48M oscillator clock Differential Speaker Driver PWM Clock Source Select DPWMCKSEL 0 = OSC48M clock. 1 = 2x OSC48M clock. WDT Clock Source Select 00 = clock source from internal OSC48M oscillator clock.
Page 106 ISD91300 Series Technical Reference Manual Clock Divider Register (CLK_CLKDIV0) Register Offset Description Reset Value CLK_CLKDIV0 CLK_BA + 0x18 R/W Clock Divider Number Register 0x0000_0000 Reserved ADCDIV Reserved UARTDIV Reserved HCLKDIV Bits Description ADC Clock Divide Number From ADC Clock Source...
Page 107 ISD91300 Series Technical Reference Manual Clock Source Select Control Register 2（CLK_CLKSEL2） Before changing clock source, ensure that related clock sources (pre-select and new-select) are enabled. Register Offset Description Reset Value CLK_CLKSEL2 CLK_BA + 0x1C R/W Clock Source Select Control Register 2...
Page 108 ISD91300 Series Technical Reference Manual Sleep Clock Enable Control Register （CLK_SLEEPCTL） These register bits are used to enable/disable clocks during sleep mode. It works in conjunction with CLK_AHBCLK and CLK_APBCLK0 clock register to determine whether a clock source remains active during CPU Sleep mode.
Page 109 ISD91300 Series Technical Reference Manual 0=Disable. 1=Enable. PWM0CH0 And PWM0CH1 Block Sleep Clock Enable Control [20] PWM0CH01CKEN 0=Disable. 1=Enable. Cyclic Redundancy Check Sleep Block Clock Enable Control [19] CRCCKEN 0=Disable. 1=Enable. Biquad Filter/ALC Block Sleep Clock Enable Control [18] BQALCKEN 0=Disable.
Page 110 ISD91300 Series Technical Reference Manual 1=Enable. Sep 9, 2019 Page 110 of 466 Revision 1.13...
Page 111 ISD91300 Series Technical Reference Manual Power State Flag Register (CLK_PWRSTSF) Register Offset Description Reset Value CLK_PWRSTSF CLK_BA+ 0x24 Power State Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved SPDF STOPF Bits Description [31:3] Reserved Reserved. Powered Down Flag SPDF This flag is set if core logic was powered down to Standby (SPD). Write ‘1’ to clearflag.
Page 112 ISD91300 Series Technical Reference Manual Debug Power Down Register (CLK_DBGPD) Register Offset Description Reset Value CLK_DBGPD CLK_BA+ 0x28 Debug Port Power Down Disable Register 0x0000_00XX Reserved Reserved Reserved ICEDATST ICECLKST Reserved DISPDREQ Bits Description [31:8] Reserved Reserved. ICEDATST Pin State ICEDATST Read Only.
Page 113: General Purpose I/O (Gpio)
6.4 General Purpose I/O (GPIO) 6.4.1 Overview The ISD91300 series has up to 32 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named as GPIOA and GPIOB.
Page 114: Functional Description
ISD91300 Series Technical Reference Manual 6.4.4 Functional Description The I/O mode of each GPIO pin is controlled by the register Px. (x=A or B). Each pin has two bits of control giving four possible states: 6.4.4.1 Input Mode Explanation For Px_MODEn = 00b the GPIOx port [n] pin is in Input Mode. The GPIO pin is in a tri-state (high impedance) condition without output drive capability.
Page 115: Figure 6-7 Open-Drain Output
ISD91300 Series Technical Reference Manual 6.4.4.3 Open-drain Output Mode Explanation For Px_MODEn = 10b the GPIOx port [n] pin is in Open-Drain mode. The GPIO pin supports a digital output function but only with sink current capability, an additional pull-up resister is needed for defining a high state.
Page 116 ISD91300 Series Technical Reference Manual 6.4.4.5 GPIO Interrupt and Wake-up Function Each GPIO pin can be set as chip interrupt source by setting correlative Px_INTEN bit and Px_INTTYPE. There are four types of interrupt condition can be selected: low level trigger, high level trigger, falling edge trigger and rising edge trigger.
Page 117: Register Map
ISD91300 Series Technical Reference Manual 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value GPIOBase Address: GPIO_BA = 0x5000_4000 PA_MODE GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control...
Page 118: Register Description
ISD91300 Series Technical Reference Manual 6.4.6 Register Description GPIO Port [A/B] I/O Mode Control (Px_MODE) Register Offset R/W Description Reset Value PA_MODE GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control 0xFFFF_FFFF PB_MODE GPIO_BA+0x040 R/W GPIO Port B Pin I/O Mode Control...
Page 119 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Input Disable (Px_DINOFF) Register Offset R/W Description Reset Value PA_DINOFF GPIO_BA+0x004 R/W GPIO Port A PinInput Disable 0x0000_0000 PB_DINOFF GPIO_BA+0x044 R/W GPIO Port B PinInput Disable 0x0000_0000 DINOFF DINOFF Reserved Reserved Bits...
Page 120 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Data Output Value (Px_DOUT) Register Offset R/W Description Reset Value PA_DOUT GPIO_BA+0x008 R/W GPIO Port A Data Output Value 0x0000_FFFF PB_DOUT GPIO_BA+0x048 R/W GPIO Port B Data Output Value 0x0000_FFFF Reserved Reserved...
Page 121 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Data Output Write Mask (Px _DATMSK) Register Offset R/W Description Reset Value PA_DATMSK GPIO_BA+0x00C R/W GPIO Port A Data Output Write Mask 0xXXXX_0000 PB_DATMSK GPIO_BA+0x04C R/W GPIO Port B Data Output Write Mask...
Page 122 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Pin Value (Px _PIN) Register Offset R/W Description Reset Value PA_PIN GPIO_BA+0x010 GPIO Port A Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 GPIO Port B Pin Value 0x0000_XXXX Reserved Reserved PIN[15:8] PIN[7:0] Bits Description...
Page 123 ISD91300 Series Technical Reference Manual GPIO Port [A/B] De-Bounce Enable (Px _DBEN) Register Offset R/W Description Reset Value PA_DBEN GPIO_BA+0x014 R/W GPIO Port A De-bounce Enable 0xXXXX_0000 PB_DBEN GPIO_BA+0x054 R/W GPIO Port B De-bounce Enable 0xXXXX_0000 Reserved Reserved DBEN[15:8] DBEN[7:0]...
Page 124 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Interrupt Mode Control (Px _INTTYPE) Register Offset R/W Description Reset Value PA_INTTYPE GPIO_BA+0x018 R/W GPIO Port A Interrupt Trigger Type 0xXXXX_0000 PB_INTTYPE GPIO_BA+0x058 R/W GPIO Port B Interrupt Trigger Type 0xXXXX_0000 Reserved...
Page 125 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Interrupt Enable Control (Px _INTEN) Register Offset R/W Description Reset Value PA_INTEN GPIO_BA+0x01C R/W GPIO Port A Interrupt Enable 0x0000_0000 PB_INTEN GPIO_BA+0x05C R/W GPIO Port B Interrupt Enable 0x0000_0000 RHIEN[15:8] RHIEN[7:0] FLIEN[15:8]...
Page 126 ISD91300 Series Technical Reference Manual GPIO Port [A/B] Interrupt Source Flag(Px _INTSRC) Register Offset R/W Description Reset Value PA_INTSRC GPIO_BA+0x020 R/W GPIO Port A Interrupt Source Flag 0x0000_0000 PB_INTSRC GPIO_BA+0x060 R/W GPIO Port B Interrupt Source Flag 0x0000_0000 Reserved Reserved...
Page 127 ISD91300 Series Technical Reference Manual Interrupt De-Bounce Control (GPIO_DBCTL ) Register Offset R/W Description Reset Value GPIO_DBCTL GPIO_BA+0x180 R/W Interrupt De-bounce Control 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description Interrupt Clock On Mode Set this bit “0” will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.
Page 128 ISD91300 Series Technical Reference Manual Sample interrupt input once per 32*256 clocks Sample interrupt input once per 64*256 clocks Sample interrupt input once per 128*256 clocks Sep 9, 2019 Page 128 of 466 Revision 1.13...
Page 129: Brownout Detection And Temperature Alarm
ISD91300 Series Technical Reference Manual 6.5 Brownout Detection and Temperature Alarm 6.5.1 Overview The ISD91300 is equipped with a Brown-Out voltage detector and Over Temperature Alarm. The Brown-Out detector features a configurable trigger level and can be configured by flash to be active upon reset.
Page 130: Register Description
ISD91300 Series Technical Reference Manual 6.5.3 Register Description Brown-Out Detector Select Register (BODTALM_BODSEL) Register Offset Description Reset Value BODTALM_BODSEL BODTALM_BA+0x00 Brown Out Detector Select Register 0x0000_0000 Reserved Reserved Reserved Reserved BODRANGE BODHYS BODVL Bits Description [31:5] Reserved Reserved. Range BODRANGE...
Page 131 ISD91300 Series Technical Reference Manual Brown-Out Detector Enable Register (BODTALM_BODCTL) This register is initialized by user flash configuration bit config0[23]. If config0[23]=1, then reset value is 0x7. The effect of this is to generate a NMI interrupt (default NMI interrupt is BODTALM_BODCTL BOD interrupt) if BOD circuit detects a voltage below 2.1V.
Page 132 ISD91300 Series Technical Reference Manual Detection Time Multiplex Register (BODTALM_BODDTMR) The BOD detector can be set up to take periodic samples of the supply voltage to minimize power consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can wake up the device if a BOD is event detected.
Page 133 ISD91300 Series Technical Reference Manual Temperature Alarm Select Register (BODTALM_TALMSEL) Register Offset R/W Description Reset Value BODTALM_TALMSEL BODTALM_BA+0x08 R/W Temperature Alarm Select Register 0x0000_0000 Reserved Reserved Reserved Reserved TALMVL Bits Description [31:4] Reserved Reserved. Temperature Alarm Sense Level 0000:105C 0001:115C...
Page 134 ISD91300 Series Technical Reference Manual Temperature Alarm Enable Register (BODTALM_TALMCTL) Register Offset R/W Description Reset Value BODTALM_TALMCTL BODTALM_BA+0x0C R/W Temperature Alarm Enable Register 0x0000_00XX Reserved Reserved Reserved Reserved TALMIF TALMIEN TALMOUT TALMEN Bits Description [31:4] Reserved Reserved. Current Status Of Interrupt TALMIF Latched whenever a Temperature Sense event occurs and IE=1.
Page 135: I 2 C Serial Interface Controller
ISD91300 Series Technical Reference Manual 6.6 I C Serial Interface Controller (I 6.6.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 136: Figure 6-9 I C Bus Timing
ISD91300 Series Technical Reference Manual I2Cn_SDA line while I2Cn_SCL is high is interpreted as a command (START or STOP). Please refer to the following figure for more detailed I C bus timing. Repeated STOP START STOP START I2Cn_SDA I2Cn_SCL HIGH HD;STA...
Page 137: Figure 6-11 Start And Stop Conditions
ISD91300 Series Technical Reference Manual of bytes followed by a stop condition. Instead of sending the stop condition it is also allowed to send another start condition again followed by an address (and of course including a read/write bit) and more data. The start condition is called as Repeat START (Sr). This is defined recursively allowing any number of start conditions to be sent.
Page 138: Figure 6-13 Acknowledge On The I C Bus
ISD91300 Series Technical Reference Manual Clock pulse for acknowledgement I2Cn_SCL (from master) I2Cn_SDA (data output by transmitter) not acknowlegde I2Cn_SDA (data output by receiver) acknowlegde START condition Figure 6-13 Acknowledge on the I C Bus 6.6.3.1.5 Data transfer on the I C bus The following figure shows a master transmits data to slave.
Page 139: Figure 6-16 Control I C Bus According To Current I C Status
ISD91300 Series Technical Reference Manual In a given application, I C port may operate as a master or as a slave. In Slave mode, the I C port hardware looks for its own slave address and the general call address. If one of these addresses...
Page 140: Figure 6-17 Master Transmitter Mode Control Flow
ISD91300 Series Technical Reference Manual 6.6.3.2.1 Master Mode In below figures, all possible protocols for I C master are shown. User needs to follow proper path of the flow to implement required I C protocol. In other words, user can send a START signal to bus and I...
Page 141: Figure 6-18 Master Receiver Mode Control Flow
ISD91300 Series Technical Reference Manual STATUS=0x08 STATUS=0xF8 STATUS=0x40 STATUS=0x50 I2CDAT I2CDAT (SLA+R) (Data) I2CDAT=SLA+R (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(1,0,1,X) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2CDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2CDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,X) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2CDAT ACK/ (SLA+R) I2CDAT=SLA+R (STA,STO,SI,AA)=(0,0,1,X)
Page 142: Figure 6-19 Save Mode Control Flow
ISD91300 Series Technical Reference Manual detect its own slave address in the same serial transfer. If the detected address is SLA+W (Master want to write data to Slave) after arbitration lost, the status code is 0x68. If the detected address is SLA+R (Master want to read data from Slave) after arbitration lost, the status code is 0xB0.
Page 143: Figure 6-20 Gc Mode
ISD91300 Series Technical Reference Manual Note: After slave gets status of 0x88, 0xC8, 0xC0 and 0xA0, slave can switch to not address mode and own SLA will not be recognized. If entering this status, slave will not receive any I signal or address from master.
Page 144: Figure 6-21 Arbitration Lost
ISD91300 Series Technical Reference Manual If I C is still receiving data in GC mode but got a STOP or Repeat START, the status code will be 0xA0. User could follow the action for status code 0x98 in above figure when getting 0xA0 status.
Page 145: Figure 6-22 I 2 C Data Shifting Direction
ISD91300 Series Technical Reference Manual 6.6.3.3 I C Protocol Registers The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL (control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL (Time-out counter register).
Page 146 ISD91300 Series Technical Reference Manual 6.6.3.3.3 Control Register (I2C_CTL) The CPU can be read from and written to I2C_CTLregister directly. When the I C port is enabled by setting ENS1 (I2C_CTL [6]) to high, the internal states will be controlled by I2C_CTL and I logic hardware.
Page 147: Table 6-5 I C Status Code Description
ISD91300 Series Technical Reference Manual 0xF8 Bus Released Note: Status “0xF8” exists in both master/slave modes, and it won’t raise interrupt. Table 6-5 I C Status Code Description Sep 9, 2019 Page 147 of 466 Revision 1.13...
Page 148: Figure 6-23 I 2 C Time-Out Count Block Diagram
ISD91300 Series Technical Reference Manual 6.6.3.3.5 Clock Baud Rate Bits (I2C_CLKDIV) The data baud rate of I C is determines by I2C_CLKDIV(I2C_CLKDIV[7:0]) when I C is in Master Mode, and it is not necessary in a Slave mode. In the Slave mode, I...
Page 149: Register Map
ISD91300 Series Technical Reference Manual 6.6.4 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value C Base Address: I2C_BA = 0x4002_0000 I2C_CTL I2C_BA+0x00 I2C Control Register 0x0000_0000 I2C_ADDR0 I2C_BA+0x04 I2C Slave address Register0...
Page 150: Register Description
ISD91300 Series Technical Reference Manual 6.6.5 Register Description C Control Register (I2C_CTL) Register Offset Description Reset Value I2C_CTL I2C_BA+0x00 I2C Control Register 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Bits Description [31:8] Reserved Reserved. Enable Interrupt INTEN 0 = Disable interrupt.
Page 151 ISD91300 Series Technical Reference Manual C Data Register (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2C_BA+0x08 I2C DATA Register 0x0000_0000 Reserved Reserved Reserved DAT[7:0] Bits Description [31:8] Reserved Reserved. C Data Register During master or slave transmit mode, data to be transmitted is written to this register.
Page 152 ISD91300 Series Technical Reference Manual C Status Register (I2C_STATUS ) Register Offset Description Reset Value I2C_STATUS I2C_BA+0x0C I2C Status Register 0x0000_0000 Reserved Reserved Reserved STATUS[7:0] Bits Description [31:8] Reserved Reserved. C Status Register The status register of I2C: The three least significant bits are always 0. The five most significant bits contain the status code.
Page 153 ISD91300 Series Technical Reference Manual C Clock Divided Register (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2C_BA+0x10 I2C clock divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER[7:0] Bits Description [31:8] Reserved Reserved. C Clock Divided Register DIVIDER [7:0] The I C clock rate bits: Data Baud Rate of I C = (system clock) / (4x (I2C_CLKDIV+1)).
Page 154 ISD91300 Series Technical Reference Manual C Time-out Counter Register (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2C_BA+0x14 I2C Time out control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Time-Out Counter Control Bit 0 = Disable.
Page 155 ISD91300 Series Technical Reference Manual C Slave Address Register (I2C_ADDRx) Register Offset Description Reset Value I2C_ADDR0 I2C_BA+0x04 I2C Slave address Register0 0x0000_0000 I2C_ADDR1 I2C_BA+0x18 I2C Slave address Register1 0x0000_0000 I2C_ADDR2 I2C_BA+0x1C I2C Slave address Register2 0x0000_0000 I2C_ADDR3 I2C_BA+0x20 I2C Slave address Register3...
Page 156 ISD91300 Series Technical Reference Manual C Slave Address Mask Register (I2C_ADDRMSKx) Register Offset Description Reset Value I2C_ADDRMSK0 I2C_BA+0x24 I2C Slave address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2C_BA+0x28 I2C Slave address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2C_BA+0x2C I2C Slave address Mask Register2 0x0000_0000...
Page 157: Pwm Generator And Capture Timer (Pwm)
6.7 PWM Generator and Capture Timer (PWM) 6.7.1 Overview The ISD91300 series has three PWM generators which can be configured as 6 independent PWM outputs,PWM0CH0, PWM0CH1, PWM0CH2,PWM0CH3,PWM1CH0 and PWM1CH1, or as a complementary PWM pairs with programmable dead-zone generator. Each PWM Generator...
Page 158: Features
ISD91300 Series Technical Reference Manual 6.7.2 Features 6.7.2.1 PWM Function:  PWM Generator, incorporating an 8-bit pre-scaler, clock divider, two PWM-timers (down counters), a dead-zone generator and two PWM outputs.  Up to 6 PWM channels or three paired PWM channel.
Page 159: Block Diagram
ISD91300 Series Technical Reference Manual 6.7.3 Block Diagram Figure 6-24 illustrate the architecture of PWM0CH01 in pair. CLK_CLKSEL1.PWM0CH01CKSEL[29:28] CLK_APBCLK0.PWM0CH01CKEN[20] CLK48M PWM0CH01_CLK HCLK CLK32K CLK16K Figure 6-24 PWM Generator Clock Source Control DTEN01 Dead Zone Generator 0 PERIOD0, PWM0_CLKDIV.CLKDIV0[2:0] CMPDAT0, CNT0 PWM- PA.12/PWM0CH0...
Page 160: Functional Description
ISD91300 Series Technical Reference Manual 6.7.4 Functional Description 6.7.4.1 PWM-Timer Operation The PWM controller supports Edge-aligned operation type. 6.7.4.2 Edge-aligned PWM (down-counter) In Edge-aligned PWM Output mode, the 16 bits PWM counter will starts down-counting from PWMx_PERIODx to match with the value of the duty cycle PWMx_CMPDATx (old), when this happen it will toggle the PWMn generator output to low.
Page 161: Figure 6-27 Pwm-Timer Operation Timing
ISD91300 Series Technical Reference Manual Comparator (CMPDAT) down-counter PWM -Timer output CMPDAT= 1 CMPDAT= 0 PERIOD= 3 Auto reload = 1 PERIOD= 4 (S/W write new value) CNTMODEn = 1 (Write initial setting) Auto- load Auto- load Set POENn =1...
Page 162: Figure 6-28 Pwm Double Buffering Illustration
6.7.4.3 PWM Double Buffering, Auto-reload and One-shot Operation The ISD91300 series PWM Timers are double buffered, the reload value is updated at the start of next period without affecting current timer operation. The PWM counter reset value can be written into PWM_PERIOD0~1 and current PWM counter value can be read from PWM_CNT0~1.
Page 163: Figure 6-29 Pwm Controller Output Duty Ratio
ISD91300 Series Technical Reference Manual 6.7.4.4 Modulate Duty Ratio The double buffering allows CMPDAT to be written at any point in current cycle. The loaded value will take effect from next cycle. Write Write Write CMPDAT=100 CMPDAT=50 CMPDAT=0 PERIOD=150 1 PWM cycle = 151...
Page 164: Figure 6-31 Capture Operation Timing
ISD91300 Series Technical Reference Manual 6.7.4.6 Capture Operation Instead of using the PWM generator to output a modulated signal, it can be configured as a capture timer to measure a modulated input. Capture channel 0 and PWM0 share one timer and Capture channel 1 and PWM1 share another timer.
Page 165: Figure 6-32 Pwm-Timer Interrupt Architecture Diagram
ISD91300 Series Technical Reference Manual 6.7.4.7 PWM-Timer Interrupt Architecture There are fourPWM interrupts, PWM0_INTEN.PIENn (n=0~3), which are multiplexed into PWM0_IRQ. PWM 0 and Capture 0 share one interrupt, PWM1 and Capture 1 share the same interrupt. Figure 6-32 demonstrates the architecture of PWM-Timer interrupts.
Page 166 ISD91300 Series Technical Reference Manual 6.7.4.8 PWM-Timer Start Procedure The following procedure is recommended for starting a PWM drive. Setup clock selector (PWM_CLKDIV) Setup prescaler(PWM_CLKPSC) Setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and Stop PWM-timer (PWM_CTL) Setup comparator register (PWM_CMPDAT)to set PWM duty cycle.
Page 167: Pwm0 Register Map
ISD91300 Series Technical Reference Manual 6.7.5 PWM0 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value PWM0 Base Address: PWM_BA = 0x4004_0000 PWM0_CLKPSC PWM_BA+0x000 PWM Prescaler Register 0x0000_0000 PWM0_CLKDIV PWM_BA+0x004 PWM Clock Select Register...
Page 168 ISD91300 Series Technical Reference Manual PWM0_FCAPDAT3 PWM_BA+0x074 Capture Falling Latch Register (Channel 3) 0x0000_0000 PWM0_CAPINEN Capture Input Enable Register PWM_BA+0x078 0x0000_0000 PWM0_POEN PWM0 Output Enable Register for CH0~CH3 PWM_BA+0x07C 0x0000_0000 Sep 9, 2019 Page 168 of 466 Revision 1.13...
Page 169: Register Description
ISD91300 Series Technical Reference Manual 6.7.6 Register Description PWM Pre-Scale Register (PWM0_CLKPSC) Register Offset R/W Description Reset Value PWM0_CLKPSC PWM_BA+0x000 R/W PWM Prescaler Register 0x0000_0000 DTCNT23 DTCNT01 CLKPSC23 CLKPSC01 Bits Description Dead Zone Interval Register For Pair Of PWM0CH2And PWM0CH3...
Page 170 ISD91300 Series Technical Reference Manual PWM Clock Select Register (PWM0_CLKDIV) Register Offset R/W Description Reset Value PWM0_CLKDIV PWM_BA+0x004 R/W PWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved CLKDIV3 Reserved CLKDIV2 Reserved CLKDIV1 Reserved CLKDIV0 Bits Description [31:15] Reserved Reserved. Timer 3 Clock Source Selection...
Page 171 ISD91300 Series Technical Reference Manual PWM Control Register (PWM0_CTL) Register Offset Description Reset Value PWM0_CTL PWM_BA+0x008 PWM Control Register 0x0000_0000 Reserved CNTMODE3 PINV3 Reserved CNTEN3 Reserved CNTMODE2 PINV2 Reserved CNTEN2 Reserved CNTMODE1 PINV1 Reserved CNTEN1 Reserved DTEN23 DTEN01 CNTMODE0 PINV0...
Page 172 ISD91300 Series Technical Reference Manual PWM-Timer 1 Output Inverter ON/OFF [10] PINV1 0 = Inverter OFF. 1 = Inverter ON. PWM-Timer 1 Enable/Disable Start Run CNTEN1 0 = Stop PWM-Timer 1. 1 = Enable PWM-Timer 1 Start/Run. Dead-Zone 23 Generator Enable/DisablePair Of PWM0CH2And PWM0CH3 0 = Disable.
Page 173 ISD91300 Series Technical Reference Manual PWM Counter Register 1-0 (PWM0_PERIOD1-0) Register Offset R/W Description Reset Value PWM0_PERIOD0 PWM_BA+0x00C R/W PWM Counter Register 0 0x0000_0000 PWM0_PERIOD1 PWM_BA+0x018 R/W PWM Counter Register 1 0x0000_0000 PWM0_PERIOD2 PWM_BA+0x024 R/W PWM Counter Register 2 0x0000_0000...
Page 174 ISD91300 Series Technical Reference Manual PWM Comparator Register 1-0 (PWM0_CMPDAT3-0) Register Offset Description Reset Value PWM0_CMPDAT0 PWM_BA+0x010 PWM Comparator Register 0 0x0000_0000 PWM0_CMPDAT1 PWM_BA+0x01C PWM Comparator Register 1 0x0000_0000 PWM0_CMPDAT2 PWM_BA+0x028 PWM Comparator Register 2 0x0000_0000 PWM0_CMPDAT3 PWM_BA+0x034 PWM Comparator Register 3...
Page 175 ISD91300 Series Technical Reference Manual PWM Data Register 1-0 (PWM0_CNT3~PWM0_CNT0) Register Offset Description Reset Value PWM0_CNT0 PWM_BA+0x014 PWM Data Register 0 0x0000_0000 PWM0_CNT1 PWM_BA+0x020 PWM Data Register 1 0x0000_0000 PWM0_CNT2 PWM_BA+0x02C PWM Data Register 2 0x0000_0000 PWM0_CNT3 PWM_BA+0x038 PWM Data Register 3...
Page 176 ISD91300 Series Technical Reference Manual PWM Interrupt Enable Register (PWM0_INTEN) Register Offset Description Reset Value PWM0_INTEN PWM_BA+0x040 PWM Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved PIEN3 PIEN2 PIEN1 PIEN0 Bits Description [31:4] Reserved Reserved. PWM Timer 3 Interrupt Enable PIEN3 0 = Disable.
Page 177 ISD91300 Series Technical Reference Manual PWM Interrupt Flag Register (PWM0_INTSTS) Register Offset R/W Description Reset Value PWM0_INTSTS PWM_BA+0x044 R/W PWM Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved PIF3 PIF2 PIF1 PIF0 Bits Description [31:4] Reserved Reserved. PWM Timer 3 Interrupt Flag...
Page 178 ISD91300 Series Technical Reference Manual Capture Control Register (PWM0_CAPCTL01) Register Offset Description Reset Value PWM0_CAPCTL01 PWM_BA+0x050 Capture Control RegisterFor Pair Of PWM0CH0And 0x0000_0000 PWM0CH1 Reserved CFLIF1 CRLIF1 Reserved CAPIF1 CAPEN1 CFLIEN1 CRLIEN1 CAPINV1 Reserved CFLIF0 CRLIF0 Reserved CAPIF0 CAPEN0 CFLIEN0...
Page 179 ISD91300 Series Technical Reference Manual Channel 1 Inverter ON/OFF [16] CAPINV1 0 = Inverter OFF. 1 = Inverter ON. Reverse the input signal from GPIO before Capture timer PWM_FCAPDAT0 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the...
Page 180 ISD91300 Series Technical Reference Manual Capture Control Register (PWM0_CAPCTL23) Register Offset Description Reset Value PWM0_CAPCTL23 PWM_BA+0x054 Capture Control RegisterFor Pair Of PWM0CH2And 0x0000_0000 PWM0CH3 Reserved CFLIF3 CRLIF3 Reserved CAPIF3 CAPEN3 CFLIEN3 CRLIEN3 CAPINV3 Reserved CFLIF2 CRLIF2 Reserved CAPIF2 CAPEN2 CFLIEN2...
Page 181 ISD91300 Series Technical Reference Manual Channel 3 Inverter ON/OFF [16] CAPINV3 0 = Inverter OFF. 1 = Inverter ON. Reverse the input signal from GPIO before Capture timer PWM_FCAPDAT2 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT2 was latched with the...
Page 182 ISD91300 Series Technical Reference Manual Capture Rising Latch Register n (PWM0_RCAPDATn) Register Offset R/W Description Reset Value PWM0_RCAPDAT0 PWM_BA+0x058 Capture Rising Latch Register (Channel 0) 0x0000_0000 PWM0_RCAPDAT1 PWM_BA+0x060 Capture Rising Latch Register (Channel 1) 0x0000_0000 PWM0_RCAPDAT2 PWM_BA+0x068 Capture Rising Latch Register (Channel 2)
Page 183 ISD91300 Series Technical Reference Manual Capture Falling Latch Register n(PWM0_FCAPDATn) Register Offset Description Reset Value PWM0_FCAPDAT0 PWM_BA+0x05C Capture Falling Latch Register (Channel 0) 0x0000_0000 PWM0_FCAPDAT1 PWM_BA+0x064 Capture Falling Latch Register (Channel 1) 0x0000_0000 PWM0_FCAPDAT2 PWM_BA+0x06C Capture Falling Latch Register (Channel 2)
Page 184 ISD91300 Series Technical Reference Manual Capture Input Enable Register (PWM0_CAPINEN) Register Offset R/W Description Reset Value PWM0_CAPINEN PWM_BA+0x078 R/W Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN[3:0] Bits Description [31:4] Reserved Reserved. Capture Input Enable Register 0 : OFF (GPA[13:12], GPB[15:14] pin input disconnected from Capture block)
Page 185 ISD91300 Series Technical Reference Manual PWM Output Enable Register (PWM0_POEN) for CH0~CH3 Register Offset Description Reset Value PWM0_POEN PWM_BA+0x07C PWM0 Output Enable Register for CH0~CH3 0x0000_0000 Reserved Reserved Reserved Reserved POEN3 POEN2 POEN1 POEN0 Bits Description [31:4] Reserved Reserved. PWM0CH3 Output Enable Register 0 = Disable PWM0CH3 output to pin.
Page 186: Pwm1 Register Map
ISD91300 Series Technical Reference Manual 6.7.7 PWM1 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value PWM1 Base Address: PWM_BA = 0x4004_0000 PWM1_CLKPSC PWM_BA+0x080 PWM Prescaler Register 0x0000_0000 PWM1_CLKDIV PWM_BA+0x084 PWM Clock Select Register...
Page 187: Register Description
ISD91300 Series Technical Reference Manual 6.7.8 Register Description PWM Pre-Scale Register (PWM1_CLKPSC) Register Offset R/W Description Reset Value PWM1_CLKPSC PWM_BA+0x080 R/W PWM Prescaler Register 0x0000_0000 Reserved DTCNT01 Reserved CLKPSC01 Bits Description [31:24] Reserved Reserved Dead Zone Interval Register For Pair Of PWM1CH0And PWM1CH1...
Page 188 ISD91300 Series Technical Reference Manual PWM Clock Select Register (PWM1_CLKDIV) Register Offset R/W Description Reset Value PWM1_CLKDIV PWM_BA+0x084 R/W PWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKDIV1 Reserved CLKDIV0 Bits Description [31:7] Reserved Reserved. Timer 1 Clock Source Selection...
Page 189 ISD91300 Series Technical Reference Manual PWM Control Register (PWM1_CTL) Register Offset Description Reset Value PWM1_CTL PWM_BA+0x088 PWM Control Register 0x0000_0000 Reserved Reserved Reserved CNTMODE1 PINV1 Reserved CNTEN1 Reserved DTEN01 CNTMODE0 PINV0 Reserved CNTEN0 Bits Description [31:12] Reserved Reserved. PWM-Timer 1 Auto-Reload/One-Shot Mode 0 = One-Shot Mode.
Page 190 ISD91300 Series Technical Reference Manual Reserved Reserved. PWM-Timer 0 Enable/Disable Start Run CNTEN0 0 = Stop PWM-Timer 0 Running. 1 = Enable PWM-Timer 0 Start/Run. Sep 9, 2019 Page 190 of 466 Revision 1.13...
Page 191 ISD91300 Series Technical Reference Manual PWM Counter Register 1-0 (PWM1_PERIOD1-0) Register Offset R/W Description Reset Value PWM1_PERIOD0 PWM_BA+0x08C R/W PWM Counter Register 0 0x0000_0000 PWM1_PERIOD1 PWM_BA+0x098 R/W PWM Counter Register 1 0x0000_0000 Reserved Reserved PERIOD [15:8] PERIOD [7:0] Bits Description...
Page 192 ISD91300 Series Technical Reference Manual PWM Comparator Register 1-0 (PWM1_CMPDAT3-0) Register Offset Description Reset Value PWM1_CMPDAT0 PWM_BA+0x090 PWM Comparator Register 0 0x0000_0000 PWM1_CMPDAT1 PWM_BA+0x09C PWM Comparator Register 1 0x0000_0000 Reserved Reserved CMPDATx [15:8] CMPDATx [7:0] Bits Description [31:16] Reserved Reserved.
Page 193 ISD91300 Series Technical Reference Manual PWM Data Register 1-0 (PWM1_CNT1~PWM1_CNT0) Register Offset Description Reset Value PWM1_CNT0 PWM_BA+0x094 PWM Data Register 0 0x0000_0000 PWM1_CNT1 PWM_BA+0x0A0 PWM Data Register 1 0x0000_0000 Reserved Reserved CNT[15:8] CNT[7:0] Bits Description [31:16] Reserved Reserved. PWM Data Register [15:0] User can monitor PDR to know the current value in 16-bit counter.
Page 194 ISD91300 Series Technical Reference Manual PWM Interrupt Enable Register (PWM1_INTEN) Register Offset Description Reset Value PWM1_INTEN PWM_BA+0x0C0 PWM Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved PIEN1 PIEN0 Bits Description [31:2] Reserved Reserved. PWM Timer 1 Interrupt Enable PIEN1 0 = Disable.
Page 195 ISD91300 Series Technical Reference Manual PWM Interrupt Flag Register (PWM1_INTSTS) Register Offset R/W Description Reset Value PWM1_INTSTS PWM_BA+0x0C4 R/W PWM Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved PIF1 PIF0 Bits Description [31:2] Reserved Reserved. PWM Timer 1 Interrupt Flag...
Page 196 ISD91300 Series Technical Reference Manual Capture Control Register (PWM1_CAPCTL01) Register Offset Description Reset Value PWM1_CAPCTL01 PWM_BA+0x0D0 Capture Control RegisterFor Pair Of PWM1CH0And 0x0000_0000 PWM1CH1 Reserved CFLIF1 CRLIF1 Reserved CAPIF1 CAPEN1 CFLIEN1 CRLIEN1 CAPINV1 Reserved CFLIF0 CRLIF0 Reserved CAPIF0 CAPEN0 CFLIEN0...
Page 197 ISD91300 Series Technical Reference Manual Channel 1 Inverter ON/OFF [16] CAPINV1 0 = Inverter OFF. 1 = Inverter ON. Reverse the input signal from GPIO before Capture timer PWM_FCAPDAT0 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the...
Page 198 ISD91300 Series Technical Reference Manual Capture Rising Latch Register n (PWM1_RCAPDATn) Register Offset R/W Description Reset Value PWM1_RCAPDAT0 PWM_BA+0x0D8 Capture Rising Latch Register (Channel 0) 0x0000_0000 PWM1_RCAPDAT1 PWM_BA+0x0E0 Capture Rising Latch Register (Channel 1) 0x0000_0000 Reserved Reserved RCAPDAT [15:8] RCAPDAT [7:0]...
Page 199 ISD91300 Series Technical Reference Manual Capture Falling Latch Register n(PWM1_FCAPDATn) Register Offset Description Reset Value PWM1_FCAPDAT0 PWM_BA+0x0DC R Capture Falling Latch Register (Channel 0) 0x0000_0000 PWM1_FCAPDAT1 PWM_BA+0x0E4 Capture Falling Latch Register (Channel 1) 0x0000_0000 Reserved Reserved FCAPDAT [15:8] FCAPDAT [7:0]...
Page 200 ISD91300 Series Technical Reference Manual Capture Input Enable Register (PWM1_CAPINEN) Register Offset R/W Description Reset Value PWM1_CAPINEN PWM_BA+0x0F8 R/W Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN[3:0] Bits Description [31:2] Reserved Reserved. Capture Input Enable Register 0 : OFF (GPA[15:14] pin input disconnected from Capture block)
Page 201 ISD91300 Series Technical Reference Manual PWM Output Enable Register (PWM1_POEN) for CH0~CH1 Register Offset Description Reset Value PWM1_POEN PWM_BA+0x0FC PWM1 Output Enable Register for CH0~CH1 0x0000_0000 Reserved Reserved Reserved Reserved POEN1 POEN0 Bits Description [31:2] Reserved Reserved. PWM1CH1 Output Enable Register 0 = Disable PWM1CH1 output to pin.
Page 202: Real Time Clock (Rtc)
ISD91300 Series Technical Reference Manual 6.8 Real Time Clock (RTC) 6.8.1 Overview Real Time Clock (RTC) unit provides real time clock, calendar and alarm functions. The clock source of the RTC is an external 32.768 kHz crystal connected at pins XI32K and XO32K or from an external 32.768 kHz oscillator output fed to pin XI32K.
Page 203: Block Diagram
ISD91300 Series Technical Reference Manual 6.8.3 Block Diagram The block diagram of Real Time Clock is depicted as follows: Time Alarm Calendar Register Alarm Register ( TALM ) ( CAR) ALMIEN[0] Calendar Time Loading Loading Alarm Interrupt Compare Register Register...
Page 204: Functional Description
ISD91300 Series Technical Reference Manual 6.8.4 Functional Description 6.8.4.1 Access to RTC register Due to clock frequency difference between RTC clock and system clock, when the user writes new data to any one of the RTC registers, the register will not be updated until 2 RTC clock periods later (60us).
Page 205 ISD91300 Series Technical Reference Manual Example 2:(RTC source clock ≦ 32768 Hz) RTC source clock measured: 32765.27Hz ( ≦ 32768 Hz) Integer part: 32765 => 0x7FFD INTEGER (FCR [11:8] Integer Part) = 0x0D – 0x01 – 0x08 = 0x04 Fraction part: 0.27 FRACTION (FCR [5:0] Fraction Part) = 0.27 x 60 = 16.2= 0x10...
Page 206 ISD91300 Series Technical Reference Manual 6.8.4.8 Alarm Interrupt When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting in RTC_TALM and RTC_CALM the alarm interrupt flag (RTC_INTSTS.AIF) is set. If alarm interrupt is enabled (RTC_INTEN.AIER=1) the alarm interrupt is also requested.
Page 207: Register Map
ISD91300 Series Technical Reference Manual 6.8.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value RTC Base Address: RTC_BA = 0x4000_8000 RTC_INIT RTC_BA+0x000 RTC Initialization Register 0x0000_0000 RTC_RWEN RTC_BA+0x004 RTC Access Enable Register...
Page 208: Register Description
ISD91300 Series Technical Reference Manual 6.8.6 Register Description RTC Initiation Register (RTC_INIT) Register Offset Description Reset Value RTC_INIT RTC_BA+0x000 RTC Initialization Register 0x0000_0000 INIT INIT INIT INIT ATVSTS Bits Description RTC Initialization [31:1] INIT After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIT.
Page 209 ISD91300 Series Technical Reference Manual RTC Access Enable Register (RTC_RWEN) Register Offset Description Reset Value RTC_BA+0x004 RTC_RWEN RTC Access Enable Register 0x0000_0000 Reserved Reserved RWENF RWEN RWEN Bits Description [31:17] Reserved Reserved. RTC Register Access Enable Flag (Read Only) 1 = RTC register read/write enable.
Page 210 ISD91300 Series Technical Reference Manual RTC Frequency Compensation Register (RTC_FREQADJ) Register Offset R/W Description Reset Value RTC_BA+0x008 RTC_FREQADJ R/W RTC Frequency Compensation Register 0x0000_0700 Reserved Reserved Reserved INTEGER Reserved FRACTION Bits Description [31:12] Reserved Reserved. Integer Part Register should contain the value (INT(F ) –...
Page 211 ISD91300 Series Technical Reference Manual RTC Time Load Register (RTC_TIME) This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current time. Register Offset Description Reset Value RTC_BA+0x00C RTC_TIME Time Load Register...
Page 212 ISD91300 Series Technical Reference Manual RTC Calendar Load Register (RTC_CAL) This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current date. Register Offset Description Reset Value RTC_BA+0x010 RTC_CAL Calendar Load Register...
Page 213 ISD91300 Series Technical Reference Manual RTC Time Scale Selection Register (RTC_CLKFMT) Register Offset Description Reset Value RTC_CLKFMT RTC_BA+0x014 Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24HEN Bits Description [31:1] Reserved Reserved. 24-Hour / 12-Hour Time Scale Selection It indicates that RTC_TIME and RTC_TALMcounter are in 24-hour time scale or 12-hour time scale.
Page 214 ISD91300 Series Technical Reference Manual RTC Day of the Week Register (RTC_WEEKDAY) Register Offset R/W Description Reset Value RTC_BA+0x018 RTC_WEEKDAY R/W Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved WEEKDAY Bits Description [31:3] Reserved Reserved. Day Of The Week Register 000 = Sunday.
Page 215 ISD91300 Series Technical Reference Manual RTC Time Alarm Register (RTC_TALM) Register Offset Description Reset Value RTC_BA+0x01C RTC_TALM Time Alarm Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Bits Description [31:22] Reserved Reserved. TENHR [21:20] 10-Hour Time Digit of Alarm Setting (0~2)
Page 216 ISD91300 Series Technical Reference Manual RTC Calendar Alarm Register (RTC_CALM) Register Offset Description Reset Value RTC_BA+0x020 RTC_CALM Calendar Alarm Register 0x0000_0000 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Bits Description [31:24] Reserved Reserved. TENYEAR [23:20] 10-Year Calendar Digit of Alarm Setting (0~9)
Page 217 ISD91300 Series Technical Reference Manual RTC Leap year Indication Register (RTC_LEAPYEAR) Register Offset Description Reset Value RTC_LEAPYEAR RTC_BA+0x024 R Leap year Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved LEAPYEAR Bits Description [31:1] Reserved Reserved. Leap Year Indication Register (Read Only) LEAPYEAR 0 = This year is not a leap year.
Page 218 ISD91300 Series Technical Reference Manual RTC Interrupt Enable Register (RTC_INTEN) Register Offset Description Reset Value RTC_BA+0x028 RTC_INTEN RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIEN ALMIEN Bits Description [31:2] Reserved Reserved. Time-Tick Interrupt And Wakeup-By-Tick Enable TICKIEN 1 = RTC Time-Tick Interrupt is enabled.
Page 219 ISD91300 Series Technical Reference Manual RTC Interrupt Indication Register (RTC_INTSTS) Register Offset Description Reset Value RTC_INTSTS RTC_BA+0x02C RTC Interrupt Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIF ALMIF Bits Description [31:2] Reserved Reserved. RTC Time-Tick Interrupt Flag When RTC Time-Tick Interrupt is enabled (RTC_INTEN.TICKIF=1), RTC unit will set TIF high at the rate selected by RTC_TICK[2:0].
Page 220 ISD91300 Series Technical Reference Manual RTC Time-Tick Register (RTC_TICK) Register Offset Description Reset Value RTC_BA+0x030 RTC_TICK RTC TimeTick Register 0x0000_0000 Reserved Reserved Reserved Reserved TWKEN TICKSEL Bits Description [31:4] Reserved Reserved. RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up.
Page 221: Serial Peripheral Interface (Spi)
Devices communicate in Master/Slave mode with the 4-wire bi- direction interface. The ISD91300 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Page 222: Functionaldescription
ISD91300 Series Technical Reference Manual 6.9.4 FunctionalDescription 6.9.4.1 Terminology SPI Peripheral Clock and SPI Bus Clock The SPI controller derives its clock source from the system HCLK as determined by the CLK_SEL1 register. The frequency of the SPI master clock is determined by the divisor ratio SPI_CLKDIV.
Page 223: Figure 6-37 32-Bit In One Transaction
ISD91300 Series Technical Reference Manual If more slave address lines are required, GPIO pins can be manually configured to provide additional SSB lines. In slave mode, the off-chip master device drives the slave select signal SPI_SSB0 to address the SPI controller. The slave selectsignal can be programmed to be active low or active high via the SPI_SSCTL.SSACTPOL bit.In addition the SPI_SSCTL.SS_LTRIG bit...
Page 224: Figure 6-38 Word Sleep Suspend Mode
ISD91300 Series Technical Reference Manual LSB/MSB First The SPI_CTL.LSB bit defines the bit order of data transmission. If LSB=0 then MSB of transfer word is sent first in time. If LSB=1 then LSB of transfer word is sent first in time. If REORDER is active, then the LSB=1 causes the bit order of each byte to be reversed, not the bit order of the short or word transmission.
Page 225: Figure 6-39 Byte Reorder Function
ISD91300 Series Technical Reference Manual BYTE0, BYTE1, and BYTE2.For Quad and Dual SPI transactions, REORDER is only valid for receive operation. For transmit in Dual/Quad modes, REORDER must be set to 0. REORDER = 1 REODRER = 0 SPI->TX[0]/SPI->RX[0] TX/ RX Buffer...
Page 226: Figure 6-41 Byte Reorder In Memory
ISD91300 Series Technical Reference Manual transfer data to SPI via word transfers. Consider the situation of where a int pointer points to the byte data array. Now if we set DWIDTH=32 and sent word-by-word SPI_TX[0] = uiSPI_DATA[i++], the order transmitted would be {0x04, 0x03, 0x02, 0x01, 0x08, 0x07, 0x06, 0x05}. However if we set REORDER=1, we would reverse this order to the desired stream: {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}.
Page 227 ISD91300 Series Technical Reference Manual If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.  Slave Under-run and Slave Error 1 interrupts In Slave mode, if there is no any data is written to the SPI_TX register, the under-run event, TXUFIF (SPI_STATUS[19]) will active when the slave select active and the serial clock input this controller.
Page 228: Figure 6-42 2-Bit System Architecture
ISD91300 Series Technical Reference Manual SPI_MOSI0 and SPI_MOSI1 pin, same as Master mode. SPICLKx SCLK MISOx [0] MISOx[1:0] MISO Slave 0 MOSIx [0] MOSIx[1:0] MOSI SPI Controller Master SPISSx 0 SPISSx1 SCLK MISOx[1] MISO Slave 1 MOSIx[1] MOSI Figure 6-42 2-bit System Architecture...
Page 229: Figure 6-44 Bit Sequence Of Dual Output Mode
ISD91300 Series Technical Reference Manual is set as 1 and QDIODIR is set as 0, both the SPI_MISO0 and SPI_MOSI0 will be set as data input ports. SPIn_SS0 SPIn_CLK SPIn_MOSI0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0...
Page 230: Figure 6-46 Quad Modesystem Architecture
ISD91300 Series Technical Reference Manual SPICLKx SCLK MISOx[1] MISOx[0] MISOx[1:0] HOLDB MISO Quad SpiFlash MOSIx[0] MOSIx[1:0] MOSI SPI Controller MOSIx[1] Master SPISSx0 SPISSx1 Figure 6-46 Quad ModeSystem Architecture SPI_SS SPI_CLK DI (IO SPI_MOSI0 7 6 5 4 3 2 1 0...
Page 231: Figure 6-48 Fifo Mode Block Diagram
ISD91300 Series Technical Reference Manual receive control logic will store the received data to this buffer. The FIFO buffer data can be read from SPI_RX register by software. There are FIFO related status bits, like RXEMPTY and RXFULL, to indicate the current status of FIFO buffer.
Page 232 ISD91300 Series Technical Reference Manual If there is no any data is written to the SPI_TX register, the under-run event, TXUFIF (SPI_STATUS[19]) will active when the slave select active and the serial clock input this controller. Under the previous condition, the Slave mode error 1, SLVURIF, SPI_STATUS[7], will be set to 1 when SS goes to inactive state and transmit under-run occurs.
Page 233: Timing Diagram
ISD91300 Series Technical Reference Manual 6.9.5 Timing Diagram In master/slave mode, the device address/slave select (SPI_SSB0/1) signal can be configured as active low or active high by the SPI_SSCTL.SSACTPOL bit. The serial clock phase and polarity is controlled by CLKPOL, RXNEG and TXNEG bits. The bit length of a transfer word is configured by the DWIDTH parameter.Whether data transmission is...
Page 234: Figure 6-51 Spi Timing In Slave Mode
ISD91300 Series Technical Reference Manual SS_LVL=1 SPIn_SS0 SS_LVL=0 CLKP=0 SPIn_CLK CLKP=1 SPIn_MISO0 TX0[6] TX0[0] TX0[7] TX0[6] TX0[7] TX0[0] SPIn_MOSI0 RX0[6] RX0[0] RX0[7] RX0[6] RX0[7] RX0[0] Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=0, CNTRL[TX_BIT_LEN]=0x08 1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0 or 2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1 Figure 6-51 SPI Timing in Slave Mode...
Page 235: Programming Examples
ISD91300 Series Technical Reference Manual 6.9.6 Programming Examples Example 1:The SPI controller is set as a master to access an off-chip slave device with the following specifications:  Data bit is latched on positive edge of SPI clock.  Data bit is driven on negative edge of SPI clock.
Page 236 ISD91300 Series Technical Reference Manual  Only one byte of data to be transmitted/received in a transaction.  Slave select signal is high level trigger. The operation flow is as follows. Configure the SPI_SSCTL register. SPI_SSCTL.SSACTPOL=1 for active high slave select, SPI_SSCTL.SS_LTRIG=1 for level sensitive trigger.
Page 237: Register Map
ISD91300 Series Technical Reference Manual 6.9.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI0 Base Address: SPI0_BA = 0x4003_0000 SPI_CTL SPI0_BA + 0x00 R/W Control and Status Register 0x0000_0004...
Page 238: Register Description
ISD91300 Series Technical Reference Manual 6.9.8 Register Description SPI Control and Status Register (SPI_CTL) Register Offset Description Reset Value SPI_CTL SPI0_BA + 0x00 Control and Status Register 0x0000_0004 Reserved RXMODEEN RXTCNTEN QUADIOEN DUALIOEN QDIODIR REORDER SLAVE UNITIEN TWOBIT Reserved DWIDTH...
Page 239 ISD91300 Series Technical Reference Manual For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0. Master Slave Mode Control [18] SLAVE 0 = Master mode. 1 = Slave mode. Unit Transfer Interrupt Enable [17] UNITIEN 0 = Disable SPI Unit Transfer Interrupt.
Page 240 ISD91300 Series Technical Reference Manual Transmit At Negative Edge TXNEG 0 = The transmitted data output signal is changed at the rising edge of SCLK. 1 = The transmitted data output signal is changed at the falling edge of SCLK.
Page 241 ISD91300 Series Technical Reference Manual SPI Divider Register (SPI_CLKDIV) Register Offset Description Reset Value SPI_CLKDIV SPI0_BA + 0x04 Clock Divider Register (Master Only) 0x0000_0000 Reserved Reserved Reserved DIVIDER[7:0] Bits Description [31:8] Reserved Reserved. Clock Divider Register The value in this field is the frequency divider for generating the SPI engine clock,f ,and the SPI serial clock of SPI master.
Page 242 ISD91300 Series Technical Reference Manual SPI Slave Select Register (SPI_SSCTL) Register Offset Description Reset Value SPI_SSCTL SPI0_BA + 0x08 Slave Select Register 0x0000_0000 SLVTOCNT[15:8] SLVTOCNT[7:0] Reserved SSINAIEN SSACTIEN Reserved SLVUDRIEN SLVBCEIEN Reserved SLVTORST SLVTOIEN SLV3WIRE AUTOSS SSACTPOL Bits Description Slave Mode Time-Out Period...
Page 243 ISD91300 Series Technical Reference Manual Slave 3-Wire Mode Enable This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI. SLV3WIRE 0 = 4-wire bi-directional interface.
Page 244 ISD91300 Series Technical Reference Manual SPI DMA Control Register (SPI_PDMACTL) Register Offset Description Reset Value SPI_PDMACTL SPI0_BA+0x0C R/W SPI PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST RXPDMAEN TXPDMAEN Bits Description [31:3] Reserved Reserved. PDMA Reset 0 = No effect.
Page 245 ISD91300 Series Technical Reference Manual SPI FIFO Control Register (SPI_FIFOCTL) Register Offset Description Reset Value SPI_FIFOCTL SPI0_BA+0x10 FIFO Control/Status Register 0x4400_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXUDFIEN TXUDFPOL RXOVIEN RXTOIEN TXTHIEN RXTHIEN TXRST RXRST Bits Description [31] Reserved Reserved.
Page 246 ISD91300 Series Technical Reference Manual 0 = TX FIFO threshold interrupt Disabled. 1 = TX FIFO threshold interrupt Enabled. Receive FIFO Threshold Interrupt Enable RXTHIEN 0 = RX FIFO threshold interrupt Disabled. 1 = RX FIFO threshold interrupt Enabled. Clear Transmit FIFO Buffer 0 = No effect.
Page 247 ISD91300 Series Technical Reference Manual SPI Status Register (SPI_STATUS) Register Offset Description Reset Value SPI_STATUS SPI0_BA+0x14 Status Register 0x0005_0110 TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL TXEMPTY SPIENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY SLVURIF SLVBEIF SLVTOIF SSLINE SSINAIF SSACTIF...
Page 248 ISD91300 Series Technical Reference Manual SPI Enable Bit Status (Read Only) 0 = Indicate the transmit control bit is disabled. 1 = Indicate the transfer control bit is active. [15] SPIENSTS Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock.
Page 249 ISD91300 Series Technical Reference Manual Slave Select Line Bus Status (Read Only) 0 = Indicates the slave select line bus status is 0. SSLINE 1 = Indicates the slave select line bus status is 1. Note: If SPI_SSCTL.SSACTPOL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
Page 250 ISD91300 Series Technical Reference Manual SPI Receive Transaction Count (SPI_RXTSNCNT) Register Offset Description Reset Value SPI_RXTSNCNT SPI0_BA+0x18 Receive Transaction Count Register 0x0000_0000 Reserved Reserved RXTSNCNT RXTSNCNT Bits Description [31:16] Reserved Reserved. DMA Receive Transaction Count When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of...
Page 251 ISD91300 Series Technical Reference Manual SPI Data Transmit Register (SPI_TX) Register Offset Description Reset Value SPI_TX SPI0_BA+0x20 FIFO Data Transmit Register 0x0000_0000 Bits Description Data Transmit Register A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer.
Page 252 ISD91300 Series Technical Reference Manual SPI Data Receive Register (SPI_RX) Register Offset Description Reset Value SPI_RX SPI0_BA+0x30 FIFO Data Receive Register 0x0000_0000 Bits Description Data Receive Register [31:0] A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS.
Page 253: Timer Controller (Timer)
ISD91300 Series Technical Reference Manual 6.10 Timer Controller (TIMER) 6.10.1 Overview The ISD91300 provides two general 24bit timer modules, TIMER0 and TIMER1. They allow the user to implement event counting or provide timing control for applications. The timer can perform functions such as frequency measurement, event counting, interval measurement, clock generation and delay timing.
Page 254: Block Diagram
ISD91300 Series Technical Reference Manual 6.10.3 Block Diagram Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-counter, a 24-bit compare register and an interrupt request signal. Refer to Figure 6-53 Timer Controller Block Diagramfor the timer controller block diagram. There are five options of clock source for each channel, Figure 6-54 Clock Source of Timer Controllerillustrate the clock source control function.
Page 255: Functional Description
ISD91300 Series Technical Reference Manual 6.10.4 Functional Description 6.10.4.1 Timer Interrupt Flag Timer controller supports interrupt flags; TIF flag set while timer counter value (CNT) matches the timer compared value (CMPDAT). 6.10.4.2 One–shot Mode If timer controller is configured at one-shot mode (OPMODE[28:27] is 00) and CNTEN (TIMERx_CTL[30]) bit is set, the timer counter starts up counting.
Page 256: Figure 6-55 Continuous Counting Mode
ISD91300 Series Technical Reference Manual TIF = 1 and TIF = 1 and TIF = 1 and Interrupt Interrupt Interrupt Generation Generation Generation Clear TIF as 0 Clear TIF as 0 Clear TIF as 0 CMPDAT = 80 and Set...
Page 257: Register Map
ISD91300 Series Technical Reference Manual 6.10.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TMR Base Address: TMRn_BA=0x4001_0000+(0x20*n) n=0,1 TIMERx_CTL TMRn_BA+0x00 Timer Control and Status Register 0x0000_0005 TIMERx_CMP TMRn_BA+0x04 Timer Compare Register...
Page 258: Register Description
ISD91300 Series Technical Reference Manual 6.10.6 Register Description Timer Control Register (TIMERx_CTL) Register Offset Description Reset Value TIMERx_CTL TMRn_BA+0x00 Timer Control and Status Register 0x0000_0005 Reserved CNTEN INTEN OPMODE[1:0] RSTCNT ACTSTS RESERVED Reserved CNTDATEN Reserved PSC[7:0] Bits Description [31] Reserved Reserved.
Page 259 ISD91300 Series Technical Reference Manual 0 = Timer is not active. 1 = Timer is active. [24:17] Reserved Reserved. Data Latch Enable When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
Page 260 ISD91300 Series Technical Reference Manual Timer Compare Register (TIMERx_CMP) Register Offset Description Reset Value TIMERx_CMP TMRn_BA+0x04 Timer Compare Register 0x0000_0000 Reserved CMPDAT[23:16] CMPDAT [15:8] CMPDAT[7:0] Bits Description [31:24] Reserved Reserved. Timer Comparison Value CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN=1.
Page 261 ISD91300 Series Technical Reference Manual Timer Interrupt Status Register (TIMERx_INTSTS) Register Offset Description Reset Value TIMERx_INTSTS TMRn_BA+0x08 Timer Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Timer Interrupt Flag This bit indicates the interrupt status of Timer.
Page 262 ISD91300 Series Technical Reference Manual Timer Data Register (TIMERx_CNT) Register Offset Description Reset Value TIMERx_CNT TMRn_BA+0x0C Timer Data Register 0x0000_0000 Reserved CNT[23:16] CNT[15:8] CNT[7:0] Bits Description [31:24] Reserved Reserved. Timer Data Register [23:0] When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT.
Page 263: Watchdog Timer (Wdt)
ISD91300 Series Technical Reference Manual 6.11 Watchdog Timer (WDT) 6.11.1 Overview The purpose of Watchdog Timer is to perform a system reset if software is not responding as designed. This prevents system from hanging for an infinite period of time. The watchdog timer includes a 18-bit free running counter with programmable time-out intervals.
Page 264: Block Diagram
ISD91300 Series Technical Reference Manual 6.11.3 Block Diagram The Watchdog Timer clock control and block diagram are shown as follows. CLK_CLKSEL1.WDTSEL CLK_APBCLK0.WDTCKEN 16KHz WDT_CLK HCLK OSC48M Figure 6-56 Watchdog Timer Clock Control WDT_CTL.RSTCNT Reset WDT Watchdog Counter WDT_CTL.IF Interrupt 18-bit WDT Counter WDT_CTL.INTEN...
Page 265: Functional Description
ISD91300 Series Technical Reference Manual 6.11.4 Functional Description The Watchdog Timer (WDT) includes an 18-bit free running up counter with programmable time- out intervals. Table 6-6 Watchdog Timer Time-out Interval Period Selectionand Figure 6-56 Watchdog Timer Clock Controlshows the WDT time-out interval and reset period timing.
Page 266: Register Map
ISD91300 Series Technical Reference Manual 6.11.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4000_4000 WDT_CTL WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Sep 9, 2019 Page 266 of 466 Revision 1.13...
Page 267: Register Description
ISD91300 Series Technical Reference Manual 6.11.6 Register Description Watchdog Timer Control Register (WDT_CTL) This is a protected register, to write to register, Protected Register first issue the unlock sequence (see Lock Key Register (SYS_REGLCTL) ). Only flag bits, IF and RSTF are unprotected and can be write-cleared at any time.
Page 268 ISD91300 Series Technical Reference Manual has no effect on this bit. 0 = Watchdog timer reset has not occurred. 1= Watchdog timer reset has occurred. NOTE: This bit is cleared by writing 1 to this bit. Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function.
Page 269: Uart Interface Controller (Uart)
ISD91300 Series Technical Reference Manual 6.12 UART Interface Controller (UART) 6.12.1 Overview The ISD91300 includes a Universal Asynchronous Receiver/Transmitter (UART). The UART supports high speed operation and flow control functions as well as protocols for Serial Infrared (IrDA) and Local interconnect Network (LIN).
Page 270: Figure 6-59 Uart Block Diagram
ISD91300 Series Technical Reference Manual APB BUS Status & control Status & control Control and TX_FIFO RX_FIFO Status registers TX shift register RX shift register Baud Rate Generator Baud out Baud out Serial Data Out UART0_CLK Serial Data In Figure 6-59 UART Block Diagram...
Page 271: Basic Configuration
ISD91300 Series Technical Reference Manual also includes the interrupt enable register (UART_INTEN) and interrupt status register (UART_INTSTS) to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt. There are six types of interrupts, transmitter FIFO empty...
Page 272: Table 6-9 Uart Controller Interrupt Source And Flag List In Dma Mode
ISD91300 Series Technical Reference Manual 6.12.5.2 UART Controller FIFO Control and Status The UART0 is built-in with a8-byte transmitter FIFO (TX_FIFO) and a 8-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The CPU can read the status of the UART at any time during operation.
Page 273: Figure 6-60 Auto Flow Control Block Diagram
ISD91300 Series Technical Reference Manual MODEMINT (CTSDETF) Receive Line Status Interrupt RLSIEN RLSINT RLSIF = Write ‘1’ to RLSINT (BIF or FEF or PEF) BIF/FEF/PEF Transmit Holding Register THREIEN THERINT THREIF Write data FIFO Empty Interrupt THERINT Table 6-10 Controller Interrupt Source and Flag in Software ModeList 6.12.5.4 UART Function Mode...
Page 274: Figure 6-61 Uart Cts Auto Flow Control Enabled
ISD91300 Series Technical Reference Manual CTS pin input status of UART function mode CTSACTLV = 0 UART_MODEMSTS. CTSSTS Active CTS pin input CTSACTLV = 1 ( default) MODEM _ INT interrupt MODEM _ INT interrupt CTSDETF Clear by softwave Clear by softwave...
Page 275: Figure 6-63 Uart Rts Flow With Software Control
ISD91300 Series Technical Reference Manual RTS pin output status of UART function mode Set UART_MODEM.RTS = 0 Set UART_MODEM.RTS = 1 RTS control bit By Software By Software Active UART_MODEM.RTS UART_MODEM.RTSACTLV = 0 UART_MODEM.RTSSTS RTS pin output UART_MODEM.RTSACTLV = 1...
Page 276: Figure 6-65 Irda Tx/Rx Timing Diagram
ISD91300 Series Technical Reference Manual In Normal mode, the transmitted pulse width is specified as 3/16 period of baud rate. IrDA SIR Receive Decoder The IrDA SIR Receive Decoder demodulates the return-to-zero bit stream from the input detector and outputs the NRZ serial bit stream to the UART received data input. The IR_SIN decoder input is normally high in the idle state.
Page 277: Figure 6-66 Structure Of Lin Frame
ISD91300 Series Technical Reference Manual Frame slot Frame Inter- Response frame space space Header Response Check Protected Data 1 Data 2 Data N Break Synch Identifier Field field field Figure 6-66 Structure of LIN Frame 6.12.5.6.2 Structure of LIN Byte...
Page 278 ISD91300 Series Technical Reference Manual The program flow of LIN Bus Receiver transfer (Rx) is show as following. Procedure with software error monitoring in Master mode: 1. Set the UART_FUNCSEL.LINEN bit to enable LIN Bus mode. 2. Set the UART_ALTCTL.LINRXEN bit register to enable LIN Rx mode.
Page 279: Register Map
ISD91300 Series Technical Reference Manual 6.12.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART0 Base Address: UART0_BA = 0x4005_0000 UART_DAT UART0_BA + 0x00 UART0 Receive/Transfer FIFO Register. Undefined UART_INTEN UART0_BA + 0x04 UART0 Interrupt Enable Register.
Page 280: Register Description
ISD91300 Series Technical Reference Manual 6.12.7 Register Description Receive FIFO Data Register (UART_DAT) Register Offset Description Reset Value UART_DAT UART0_BA + 0x00 R/W UART0 Receive/Transfer FIFO Register. Undefined Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receive FIFO Register [7:0] Reading this register will return data from the receive data FIFO.
Page 281 ISD91300 Series Technical Reference Manual Interrupt Enable Register (UART_INTEN) Register Offset Description Reset Value UART_INTEN UART0_BA + 0x04 R/W UART0 Interrupt Enable Register. 0x0000_0000 Reserved Reserved DMARXEN DMATXEN ATOCTSEN ATORTSEN TOCNTEN Reserved LINIEN Reserved BUFERRIEN RXTOIEN MODEMIEN RLSIEN THREIEN RDAIEN...
Page 282 ISD91300 Series Technical Reference Manual Receive Time Out Interrupt Enable RXTOIEN 0 = Mask off RXTOINT. 1 = Enable RXTOINT. Modem Status Interrupt Enable MODEMIEN 0 = Mask off MODEMINT. 1 = Enable MODEMINT. Receive Line Status Interrupt Enable RLSIEN 0 = Mask off RLSINT.
Page 283 ISD91300 Series Technical Reference Manual FIFO Control Register (UART_FIFO) Register Offset Description Reset Value UART_FIFO UART0_BA + 0x08 R/W UART0 FIFO Control Register. 0x0000_0000 Reserved Reserved RTSTRGLV Reserved RFITL Reserved TXRST RXRST Reserved Bits Description [31:20] Reserved Reserved. RTS Trigger Level For Auto-Flow Control Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).
Page 284 ISD91300 Series Technical Reference Manual Line Control Register (UART_LINE) Register Offset Description Reset Value UART_LINE UART0_BA + 0x0C R/W UART0 Line Control Register. 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the ‘Space’ state (logic 0).
Page 285 ISD91300 Series Technical Reference Manual MODEM Control Register (UART_MODEM) Register Offset Description Reset Value UART_MODEM UART0_BA + 0x10 R/W UART0 Modem Control Register. 0x0000_0000 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved LBMEN Reserved Reserved Bits Description [31:14] Reserved Reserved.
Page 286 ISD91300 Series Technical Reference Manual Modem Status Register (UART_MODEMSTS) Register Offset Description Reset Value UART_MODEMSTS UART0_BA + 0x14 UART0 Modem Status Register. 0x0000_0000 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Bits Description Reserved [31:9] Reserved. Clear-To-Send (CTS) Active Trigger Level This bit can change the CTS trigger level.
Page 287 ISD91300 Series Technical Reference Manual FIFO Status Register (UART_FIFOSTS) Register Offset Description Reset Value UART_FIFOSTS UART0_BA + 0x18 R/W UART0 FIFO Status Register. 0x1040_4000 Reserved TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY TXPTR RXFULL RXEMPTY RXPTR Reserved Reserved RXOVIF Bits Description [31:29] Reserved Reserved.
Page 288 ISD91300 Series Technical Reference Manual Receive FIFO Empty (Read Only) This bit indicates whether the Rx FIFO is empty or not. [14] RXEMPTY When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
Page 289 ISD91300 Series Technical Reference Manual Interrupt Status Register (UART_INTSTS) Register Offset Description Reset Value UART0 Interrupt Status Register. UART_INTSTS UART0_BA + 0x1C 0x0000_0002 DLININT Reserved DBERRINT DRXTOINT DMODEMI DRLSINT Reserved DLINIF Reserved DBERRIF DRXTOIF DMODEMIF DRLSIF Reserved LININT Reserved BUFERRINT...
Page 290 ISD91300 Series Technical Reference Manual interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it. DMA MODE MODEM Interrupt Flag (Read Only) This bit is set when the CTS pin has changed state (UART_MODEMSTS.CTSDETF=1).
Page 291 ISD91300 Series Technical Reference Manual by a write 1. Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one RLSIF of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
Page 292 ISD91300 Series Technical Reference Manual Time Out Register (UART_TOUT) Register Offset Description Reset Value UART0_BA + 0x20 R/W UART0 Time Out Register UART_TOUT 0x0000_0000 Reserved Reserved Reserved Reserved TOIC Bits Description [31:7] Reserved Reserved. Time Out Interrupt Comparator The time out counter resets and starts counting whenever the Rx FIFO receives a new data word.
Page 293 ISD91300 Series Technical Reference Manual Baud Rate Divider Register (UART_BAUD) Register Offset Description Reset Value UART0_BA + 0x24 R/W UART0 Baud Rate Divisor Register UART_BAUD 0x0F00_0000 Reserved BAUDM1 BAUDM0 EDIVM1 Reserved Bits Description [31:30] Reserved Reserved. Divider X Enable The baud rate equation is: Baud Rate =UART_CLK / [ M * (BRD + 2) ] ;...
Page 294 ISD91300 Series Technical Reference Manual IrDA Control Register (UART_IRDA) Register Offset Description Reset Value UART_IRDA UART0_BA + 0x28 R/W UART0 IrDA Control Register. 0x0000_0040 Reserved Reserved Reserved Reserved RXINV TXINV Reserved LOOPBACK TXEN Reserved Bits Description [31:7] Reserved Reserved. Receive Inversion Enable RXINV 0= No inversion.
Page 295 ISD91300 Series Technical Reference Manual UART LIN Network Control Register (UART_ALTCTL) Register Offset Description Reset Value UART_ALTCTL UART0_BA + 0x2C R/W UART0 LINControlRegister. 0x0000_0000 Reserved Reserved Reserved LINTXEN LINRXEN Reserved BRKFL Bits Description [31:8] Reserved Reserved. LIN TX Break Mode Enable 0 = Disable LIN Tx Break Mode.
Page 296 ISD91300 Series Technical Reference Manual UART Function Select Register (UART_FUNCSEL) Register Offset Description Reset Value UART0 Function Select Register. UART_FUNCSEL UART0_BA + 0x30 0x0000_0000 Reserved Reserved Reserved Reserved IRDAEN LINEN Bits Description Reserved [31:2] Reserved. Enable IrDA Function IRDAEN 0 = UART Function.
Page 297: I 2 S Controller
ISD91300 Series Technical Reference Manual 6.13 I S Controller (I S)Audio PCM Controller 6.13.1 Overview The I S controller is a peripheral for serial transmission and reception of audio PCM (Pulse-Code Modulated) signals across a 4-wire bus. The bus consists of a bit clock (I2S_BCLK) a frame synchronization clock (I2S_FS) and serial data in (I2S_SDI) and out (I2S_SDO) lines.
Page 298: Block Diagram
ISD91300 Series Technical Reference Manual 6.13.3 Block Diagram I2S_MCLK I2S_CLK_GEN I2S_FS Transmit Contrl I2S_SDO Tx Shift Register & TXFIFO Interface I2S_BCLK & Shift Clock dma_req Control Registers Receive dma_ack Control & Rx Shift Register I2S_SDI RXFIFO SLAVE_MODE Figure 6-68 I...
Page 299: Functional Description
ISD91300 Series Technical Reference Manual 6.13.4 Functional Description 6.13.4.1 I S Clock The I S controller has four clock sources selected by I2S_S (CLKSEL2[1:0]). The I S clock rate must be slower than or equal to system clock rate. CLK_CLKSEL2.I2S0SEL CLK_APBCLK0.I2SCKEN...
Page 300: Figure 6-70 I 2 S Data Format Timing Diagram
ISD91300 Series Technical Reference Manual 6.13.4.2 I S Operation The I S controller supports MSB justified and I S data format. The I2SLRCLK signal indicates which audio channel is in transferring. The bit count of an audio channel is determined by WDWIDTH (I2S_CTL[5:4]).
Page 301 ISD91300 Series Technical Reference Manual 6.13.4.3 I S Interrupt Sources The I S controller supports left channel zero-cross interrupt, right channel zero-cross interrupt, transmit FIFO threshold level interrupt, transmit FIFO overflow interrupt and transmit FIFO underflow interrupt in transmit operation. In receive operation, it supports receive FIFO threshold level interrupt, receive FIFO overflow interrupt and receive FIFO underflow interrupt.
Page 302: Figure 6-72 Fifo Contents For Various I
ISD91300 Series Technical Reference Manual 6.13.4.4 FIFO Operation The word width of an audio channel can be 8, 16, 24 or 32 bits. The memory arrangements for various settings are shown below. Mono 16-bit data mode Stereo 16-bit data mode...
Page 303: Figure 6-73 Master Mode Interface
ISD91300 Series Technical Reference Manual 6.13.4.5 Zero Cross Detection When playing audio by I S function, the output data comes from the memory by PDMA or by CPU. However, it may result some pop noise if the playing gain level is changed by user at any time.
Page 304: Register Map
ISD91300 Series Technical Reference Manual 6.13.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SBase Address: I2S_BA = 0x400A_0000 I2S_CTL I2S_BA+0x00 I2S Control Register 0x0000_0000 I2S_CLKDIV I2S_BA+0x04 I2S Clock Divider Register...
Page 305: Register Description
ISD91300 Series Technical Reference Manual 6.13.6 Register Description S Control Register (I2S_CTL) Register Offset Description Reset Value I2S_CTL I2S_BA + 0x00 I2S Control Register 0x0000_0000 Reserved Reserved RXPDMAEN TXPDMAEN RXCLR TXCLR LZCEN RZCEN MCLKEN RXTH TXTH SLAVE FORMAT MONO WDWIDTH...
Page 306 ISD91300 Series Technical Reference Manual Right Channel Zero Cross Detect Enable If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
Page 307 ISD91300 Series Technical Reference Manual Transmit Mute Enable MUTE 0 = Transmit data is shifted from FIFO. 1= Transmit channel zero. Receive Enable RXEN 0 = Disable data receive. 1 = Enable data receive. Transmit Enable TXEN 0 = Disable data transmit.
Page 308 ISD91300 Series Technical Reference Manual S Clock Divider Register (I2S_CLKDIV) Register Offset Description Reset Value I2S_CLKDIV I2S_BA + 0x04 I2S Clock Divider Register 0x0000_0000 Reserved Reserved BCLKDIV Reserved MCLKDIV Bits Description Reserved [31:16] Reserved. Bit Clock Divider If I2S operates in master mode, bit clock is provided by ISD91300. Software can program these bits to generate bit clock frequency for the desired sample rate.
Page 309 ISD91300 Series Technical Reference Manual S Interrupt Enable Register (I2S_IEN) Register Offset Description Reset Value I2S_IEN I2S_BA + 0x08 I2S Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved LZCIEN RZCIEN TXTHIEN TXOVIEN TXUDIEN Reserved RXTHIEN RXOVIEN RXUDIEN Bits Description [31:13] Reserved Reserved.
Page 310 ISD91300 Series Technical Reference Manual Receive FIFO Threshold Level Interrupt Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0]. RXTHIEN 0 = Disable interrupt. 1 = Enable interrupt.
Page 311 ISD91300 Series Technical Reference Manual S Status Register (I2S_STATUS) Register Offset Description Reset Value I2S_STATUS I2S_BA + 0x0C I2S Status Register 0x0014_1000 TXCNT RXCNT LZCIF RZCIF TXBUSY TXEMPTY TXFULL TXTHIF TXOVIF TXUDIF Reserved RXEMPTY RXFULL RXTHIF RXOVIF RXUDIF Reserved RIGHT...
Page 312 ISD91300 Series Technical Reference Manual Transmit FIFO Threshold Flag (Read Only) When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater...
Page 313 ISD91300 Series Technical Reference Manual I2S Transmit Interrupt (Read Only) This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To TXIF clear interrupt the corresponding source(s) must be cleared.
Page 314 ISD91300 Series Technical Reference Manual S Transmit FIFO Register (I2S_TX) Register Offset Description Reset Value I2S_TX I2S_BA + 0x10 I2S Transmit FIFO Register 0x0000_0000 TX [31:24] TX [23:16] TX [15:8] TX [7:0] Bits Description Transmit FIFO Register (Write Only) A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight [31:0] words deep.
Page 315 ISD91300 Series Technical Reference Manual S Receive FIFO Register (I2S_RX) Register Offset Description Reset Value I2S_RX I2S_BA + 0x14 I2S Receive FIFO Register 0x0000_0000 RX[31:24] RX[23:16] RX[15:8] RX[7:0] Bits Description Receive FIFO Register (Read Only) A read of this register will pop data from the receive FIFO. The receive FIFO is eight words [31:0] deep.
Page 316: Pdma Controller (Pdma)
ISD91300 Series Technical Reference Manual 6.14 PDMA Controller (PDMA) 6.14.1 Overview The ISD91300 series DMA contains nine-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA has four channels of DMA PDMA CH0~CH3). PDMA transfers are unidirectional and can be Peripheral-to-SRAM,SRAM-to-Peripheral or SRAM-to-SRAM.
Page 317: Features
ISD91300 Series Technical Reference Manual 6.14.2 Features  Provides access to SPI, UART, I2S, ADC and DPWM peripherals  AMBA AHB master/slave interface, transfers can occur concurrently with CPU access to flash memory  PDMA source and destination addressing modes allow fixed, incrementing, wrap- around and spanned addressing ...
Page 318: Block Diagram
ISD91300 Series Technical Reference Manual 6.14.3 Block Diagram SRAM CortexM0 APB Bridge APB Bus AHB ARB AHB ARB Peripherals AHB BUS1 AHB BUS2 PDMA PDMA Service Controller Request Signals from Peripherals PDMA Control Registers Figure 6-75 DMA Controller Block Diagram...
Page 319: Figure 6-76 Crc Generator Block Diagram
ISD91300 Series Technical Reference Manual CRC Checksum Reg CRC CTL CRC Seed CCITT Checksum Reverse / CRC-8 1' s COMP In Data Bit Reverse / 1' s COMP CRC-16 CRC-32 CRC Control Unit CRC BM FSM Control Figure 6-76 CRC Generator Block Diagram...
Page 320: Functional Description
ISD91300 Series Technical Reference Manual 6.14.4 Functional Description The direct memory access (DMA) controller module transfers data from one address to another address, without CPU intervention. The DMA controller contains nine PDMA (Peripheral-to- Memory or Memory-to-Peripheral or Memory-to-Memory) channels and one CRC generator channel.
Page 321 ISD91300 Series Technical Reference Manual PDMA_CRCCTL[TRGEN] = 0) and DMA transfer mode (PDMA_CRCCTL [CRCEN] = 1, PDMA_CRCCTL [TRGEN] = 1). Procedure when operating in CPU PIO mode:  Enable CRC engine by setting CRCEN bit in PDMA_CRCCTL register.  Initial Setting. Set the data format (DATREV, CHKSREV, DATFMT and CHKSFMT by setting PDMA_CRCCTL register), initial seed value (PDMA_CRCSEED) and select the data length by setting PDMA_CRCCTL [DATLEN] register.
Page 322: Register Map
ISD91300 Series Technical Reference Manual 6.14.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMA_BA = 0x5000_8000 PDMA_DSCT0_CTL PDMA_BA+0x00 R/W PDMA ControlRegister of Channel 0 0x0000_0000...
Page 323 ISD91300 Series Technical Reference Manual PDMA_DSCT2_ENDSA PDMA_BA+0x204 R/W PDMA Transfer Source Address Register of Channel 2 0x0000_0000 PDMA Transfer Destination Address Register of PDMA_DSCT2_ENDDA PDMA_BA+0x208 0x0000_0000 Channel 2 PDMA_TXBCCH2 PDMA_BA+0x20C R/W PDMA Transfer Byte Count Register of Channel 2 0x0000_0000...
Page 324 ISD91300 Series Technical Reference Manual PDMA_CRCINTF R/W CRC DMA Interrupt Status Register 0x0000_0000 PDMA_BA+0xE24 PDMA_CRCDAT PDMA_BA+0xE80 R/W CRC Write Data Register 0x0000_0000 PDMA_CRCSEED PDMA_BA+0xE84 R/W CRC Seed Register 0xFFFF_FFFF PDMA_CRCCHKS PDMA_BA+0xE88 CRC Checksum Register 0x0000_0000 PDMA_GLOCTL PDMA_BA+0xF00 R/W PDMA Global Control Register...
Page 325: Register Description
ISD91300 Series Technical Reference Manual 6.14.6 Register Description PDMA ControTXENl and Status Register (PDMA_DSCTn_CTL)(n=0~3) Register Offset Description Reset Value PDMA_DSCT0_CTL PDMA_BA+0x00 PDMA Control Registerof Channel 0 0x0000_0000 PDMA_DSCT1_CTL PDMA_BA+0x100 R/W PDMA Control Register of Channel 1 0x0000_0000 PDMA_DSCT2_CTL PDMA_BA+0x200 R/W...
Page 326 ISD91300 Series Technical Reference Manual Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT=32 then an interrupt could be generated when 16 bytes were sent.
Page 327 ISD91300 Series Technical Reference Manual PDMA Transfer Source Address Register (PDMA_DSCTn_ENDSA)(n=0~3) Register Offset Description Reset Value PDMA_DSCT0_ENDSA PDMA_BA+0x04 PDMA Transfer Source Address Register of Channel 0 0x0000_0000 PDMA_DSCT1_ENDSA PDMA_BA+0x104 R/W PDMA Transfer Source Address Register of Channel 1 0x0000_0000 PDMA_DSCT2_ENDSA PDMA_BA+0x204 R/W...
Page 328 ISD91300 Series Technical Reference Manual PDMA Transfer Destination Address Register (PDMA_DSCTn_ENDDA)(n=0~3) Register Offset Description Reset Value PDMA Transfer Destination Address Register of PDMA_DSCT0_ENDDA PDMA_BA+0x08 0x0000_0000 Channel 0 PDMA Transfer Destination Address Register of PDMA_DSCT1_ENDDA PDMA_BA+0x108 R/W 0x0000_0000 Channel 1 PDMA Transfer Destination Address Register of...
Page 329 ISD91300 Series Technical Reference Manual PDMA Transfer Byte Count Register (PDMA_TXBCCHn)(n=0~3) Register Offset Description Reset Value PDMA_TXBCCH0 PDMA_BA+0x0C PDMA Transfer Byte Count Register of Channel 0 0x0000_0000 PDMA_TXBCCH1 PDMA_BA+0x10C PDMA Transfer Byte Count Register of Channel 1 0x0000_0000 PDMA_TXBCCH2 PDMA_BA+0x20C...
Page 330 ISD91300 Series Technical Reference Manual PDMA Internal Buffer Pointer Register (PDMA_INLBPCHn)(n=0~3) Register Offset Description Reset Value PDMA_INLBPCH0 PDMA_BA+0x10 PDMA Internal Buffer Pointer Register of Channel 0 0xXXXX_XX00 PDMA_INLBPCH1 PDMA_BA+0x110 PDMA Internal Buffer Pointer Register of Channel 1 0xXXXX_XX00 PDMA_INLBPCH2 PDMA_BA+0x210...
Page 331 ISD91300 Series Technical Reference Manual PDMA Current Source Address Register (PDMA_CURSACHn) (n=0~3) Register Offset Description Reset Value PDMA_CURSACH0 PDMA_BA+0x14 PDMA Current Source Address Register of Channel 0 0x0000_0000 PDMA_CURSACH1 PDMA_BA+0x114 PDMA Current Source Address Register of Channel 1 0x0000_0000 PDMA_CURSACH2 PDMA_BA+0x214...
Page 332 ISD91300 Series Technical Reference Manual PDMA Current Destination Address Register (PDMA_CURDACHn) (n=0~3) Register Offset R/W Description Reset Value PDMA Current Destination Address Register of Channel PDMA_CURDACH0 PDMA_BA+0x18 0x0000_0000 PDMA Current Destination Address Register of Channel PDMA_CURDACH1 PDMA_BA+0x118 0x0000_0000 PDMA Current Destination Address Register of Channel...
Page 333 ISD91300 Series Technical Reference Manual PDMA Current Byte Count Register (PDMA_CURBCCHn) (n=0~3) Register Offset R/W Description Reset Value PDMA_CURBCCH0 PDMA_BA+0x1C PDMA Current Byte Count Register of Channel 0 0x0000_0000 PDMA_CURBCCH1 PDMA_BA+0x11C PDMA Current Byte Count Register of Channel 1 0x0000_0000...
Page 334 ISD91300 Series Technical Reference Manual PDMA Interrupt Enable Control Register (PDMA_INTENCHn) (n=0~3) Register Offset Description Reset Value PDMA_INTENCH0 PDMA_BA+0x20 PDMA Interrupt Enable Control Register of Channel 0 0x0000_0001 PDMA_INTENCH1 PDMA_BA+0x120 PDMA Interrupt Enable Control Register of Channel 1 0x0000_0001 PDMA_INTENCH2 PDMA_BA+0x220...
Page 335 ISD91300 Series Technical Reference Manual PDMA Interrupt Status Register (PDMA_CHnIF) (n=0~3) Register Offset Description Reset Value PDMA_CH0IF PDMA_BA+0x24 PDMA Interrupt Status Register of Channel 0 0x0000_0000 PDMA_CH1IF PDMA_BA+0x124 PDMA Interrupt Status Register of Channel 1 0x0000_0000 PDMA_CH2IF PDMA_BA+0x224 PDMA Interrupt Status Register of Channel 2...
Page 336 ISD91300 Series Technical Reference Manual PDMA Span Increment Register (PDMA_SPANRCHn) (n=0~3) Register Offset Description Reset Value PDMA_SPANRCH0 PDMA_BA+0x34 PDMA Span Increment Register of Channel 0 0x0000_0000 PDMA_SPANRCH1 PDMA_BA+0x134 PDMA Span Increment Register of Channel 1 0x0000_0000 PDMA_SPANRCH2 PDMA_BA+0x234 PDMA Span Increment Register of Channel 2...
Page 337 ISD91300 Series Technical Reference Manual PDMA Current Span Increment Register (PDMA_CURSRCHn) (n=0~3) Register Offset Description Reset Value PDMA_CURSRCH0 PDMA_BA+0x38 PDMA Current Span Increment Register of Channel 0 0x0000_0000 PDMA_CURSRCH1 PDMA_BA+0x138 PDMA Current Span Increment Register of Channel 1 0x0000_0000 PDMA_CURSRCH2 PDMA_BA+0x238...
Page 338 ISD91300 Series Technical Reference Manual CRC Control Register (PDMA_CRCCTL) Register Offset Description Reset Value PDMA_CRCCTL PDMA_BA+0xE00 CRC Control Register 0x2000_0000 CRCMODE DATLEN CHKSFMT DATFMT CHKSREV DATREV TRGEN Reserved Reserved Reserved CRCRST CRCEN Bits Description CRC Polynomial Mode 00 = CRC-CCITT Polynomial mode.
Page 339 ISD91300 Series Technical Reference Manual Write Data Order Reverse 0 = No bit order reversed for CRC write data in. [24] DATREV 1 = Bit order reversed for CRC write data in (per byte). Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is...
Page 340 ISD91300 Series Technical Reference Manual CRCDMA Transfer Source Address Register (PDMA_CRCSA) Register Offset Description Reset Value PDMA_CRCSA PDMA_BA+0xE04 CRC DMA Source Address Register 0x0000_0000 SRCADDR [31:24] SRCADDR [23:16] SRCADDR [15:8] SRCADDR [7:0] Bits Description CRC DMA Transfer Source Address Register...
Page 341 ISD91300 Series Technical Reference Manual CRCDMA Transfer Byte Count Register (PDMA_CRCBC) Register Offset Description Reset Value PDMA_CRCBC PDMA_BA+0xE0C CRC DMA Transfer Byte Count Register 0x0000_0000 Reserved Reserved BYTECNT [15:8] BYTECNT [7:0] Bits Description [31:16] Reserved Reserved. CRC DMA Transfer Byte Count Register...
Page 342 ISD91300 Series Technical Reference Manual CRC DMA Current Source Address Register (PDMA_CRCCSA) Register Offset Description Reset Value PDMA_CRCCSA PDMA_BA+0xE14 CRC DMA Current Source Address Register 0x0000_0000 CURSA [31:24] CURSA [23:16] CURSA [15:8] CURSA [7:0] Bits Description CRC DMA Current Source Address Register (Read Only)
Page 343 ISD91300 Series Technical Reference Manual CRC DMA Current Byte Count Register (PDMA_CRCCBC) Register Offset Description Reset Value PDMA_CRCCBC PDMA_BA+0xE1C CRC DMA Current Transfer Byte Count Register 0x0000_0000 Reserved Reserved CURBC [15:8] CURBC [7:0] Bits Description [31:16] Reserved Reserved. CRC DMA Current Byte Count Register (Read Only)
Page 344 ISD91300 Series Technical Reference Manual CRC DMA Interrupt Enable Control Register (PDMA_CRCINTEN) Register Offset Description Reset Value PDMA_CRCINTEN PDMA_BA+0xE20 CRC DMA Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved TXOKIEN TXABTIEN Bits Description [31:2] Reserved Reserved. CRC DMA Transfer Done Interrupt Enable TXOKIEN 0 = Interrupt generator DisabledwhenCRC DMA transfer is done.
Page 345 ISD91300 Series Technical Reference Manual CRC DMA Interrupt Status Register (PDMA_CRCINTF) Register Offset Description Reset Value PDMA_CRCINTF PDMA_BA+0xE24 CRC DMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TXOKIF TXABTIF Bits Description [31:2] Reserved Reserved. Block Transfer Done Interrupt Flag This bit indicates that CRC DMA has finished all transfer.
Page 346 ISD91300 Series Technical Reference Manual CRC Write Data Register (PDMA_CRCDAT) Register Offset Description Reset Value PDMA_CRCDAT PDMA_BA+0xE80 CRC Write Data Register 0x0000_0000 DATA [31:24] DATA [23:16] DATA [15:8] DATA [7:0] Bits Description CRC Write Data Register When operated in CPU PIO (PDMA_CRCCTL.CRCEN = 1, PDMA_CRCCTL.TRGEN = 0) mode, software can write data to this field to perform CRC operation;...
Page 347 ISD91300 Series Technical Reference Manual CRC Seed Register (PDMA_CRCSEED) Register Offset Description Reset Value PDMA_CRCSEED PDMA_BA+0xE84 CRC Seed Register 0xFFFF_FFFF SEED [31:24] SEED [23:16] SEED [15:8] SEED [7:0] Bits Description CRC Seed Register SEED [31:0] This field indicates the CRC seed value.
Page 348 ISD91300 Series Technical Reference Manual CRC Checksum Register (PDMA_CRCCHKS) Register Offset Description Reset Value PDMA_CRCCHKS PDMA_BA+0xE88 CRC Checksum Register 0x0000_0000 CHECKSUM [31:24] CHECKSUM [23:16] CHECKSUM [15:8] CHECKSUM [7:0] Bits Description CRC Checksum Register CHECKSUM [31:0] This field indicates the CRC checksum.
Page 349 ISD91300 Series Technical Reference Manual PDMA Global Control Register (PDMA_GLOCTL) Register Offset Description Reset Value PDMA_GLOCTL PDMA_BA+0xF00 PDMA Global Control Register 0x0000_0000 Reserved Reserved CHCKEN Reserved SWRST Bits Description [31:17] Reserved Reserved. PDMA Controller Channel Clock Enable Control To enable clock for channel n CHCKEN[n] must be set.
Page 350 ISD91300 Series Technical Reference Manual PDMA Service Selection Control Register (PDMA_SVCSEL) PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral.
Page 351 ISD91300 Series Technical Reference Manual PDMA SPI0 Receive Selection [3:0] SPIRXSEL This field defines which PDMA channel is connected to SPI0peripheral receive (PDMA source) request. Sep 9, 2019 Page 351 of 466 Revision 1.13...
Page 352 ISD91300 Series Technical Reference Manual PDMA Global Interrupt Status Register (PDMA_GLOBALIF) Register Offset Description Reset Value PDMA_GLOBALIF PDMA_BA+0xF0C PDMA Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:4] Reserved Reserved. Interrupt Pin Status (Read Only) GLOBALIF [3:0] GLOBALIF[n] is the interrupt status of PDMA channel n.
Page 353: Flash Memory Controller (Fmc)
FLASH MEMORY CONTROLLER (FMC) 7.1 Overview The ISD91300 series is available with 145/100/68Kbytes of on-chip embedded Flash EEPROM for application program and data flash memory. The memory can be updated through procedures for In-Circuit Programming (ICP) through the ARM Serial-Wire Debug (SWD) port or via In- System Programming (ISP) functions under software control.
Page 354: Block Diagram
ISD91300 Series Technical Reference Manual 7.3 Block Diagram The flash memory controller consist of AHB slave interface, ISP control logic, writer interface and flash macro interface timing control logic. The block diagram of flash memory controller is shown as following:...
Page 355: Functionaldescription
ISD91300 Series Technical Reference Manual 7.4 FunctionalDescription 7.4.1 Flash Memory Organization The ISD9300series flash memory consists of program memory (APROM), Data Flash, ISP loader program memory (LDROM), and user configuration. Program memory is main memory for user applications and called APROM. User can write their application to APROM and set system to boot from APROM.
Page 356: Figure 7-2 Flash Memory Organization
ISD91300 Series Technical Reference Manual 0x0030_01FF User Configuration CONFIG 0x0030_0000 0x0010_0FFF ISP Loader Program Memory LDROM 0x0010_0000 Reserved ISD9361: 0x0002_33FF Data Flash DATAF DFBADR Application Program Memory APROM CONFIG1 0x0030_0004 CONFIG0 0x0030_0000 0x0000_0000 Figure 7-2 Flash Memory Organization Sep 9, 2019 Page 356 of 466 Revision 1.13...
Page 357: Boot Selection
ISD91300 Series Technical Reference Manual 7.4.2 Boot Selection The ISD91300 provides an in-system programming (ISP) feature to enable user to update the application program memory when the chip is mounted on a PCB. A dedicated 4KBboot loader program memory is used to store ISP firmware. The user customizes this firmware to implement a protocol specific to their system to download updated application code.
Page 358: Data Flash (Dataf)
ISD91300 Series Technical Reference Manual 7.4.3 Data Flash (DATAF) The ISD91300 provides a data flash partition for user to store non-volatile data such as audio recordings. It accessed through ISP procedures via the Flash Memory Controller (FMC). The size of each erasable sector is 1Kbyte and minimum write size is one word (4Bytes).An erase operation resets all memory in sector to value 0xFF.
Page 359: User Configuration
ISD91300 Series Technical Reference Manual 7.4.4 User Configuration User configuration is internal programmable configuration area for boot options. The user configuration is located at 0x300000 of Flash Memory Organization and they are two 32 bits words. Any change on user configuration will take effect after system reboot.
Page 360 ISD91300 Series Technical Reference Manual DFENB Data Flash Enable Bar When data flash is enabled, flash memory is partitioned between APROM and DATAF memory depending on the setting of data flash base address in Config1 register. If set to ‘0’ then no DATAF partition exists.
Page 361 ISD91300 Series Technical Reference Manual CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBADR.19 DFBADR.18 DFBADR.17 DFBADR.16 DFBADR.15 DFBADR.14 DFBADR.13 DFBADR.12 DFBADR.11 DFBADR.10 DFBADR.9 DFBADR.8 DFBADR.7 DFBADR.6 DFBADR.5 DFBADR.4 DFBADR.3 DFBADR.2 DFBADR.1 DFBADR.0 Config Address =0x0030_0004 Bits Description [31:20] Reserved Reserved (It is mandatory to program 0x00 to theseReserved bits)
Page 362: In-System-Programming (Isp)
ISD91300 Series Technical Reference Manual 7.4.5 In-System-Programming (ISP) The program and data flash memory support both in hardware In-Circuit Programming (ICP) and firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-Wire Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang- writers are available to reduce programming and manufacturing costs.
Page 363: Table 7-2 Isp Command List
Table 7-2 ISP Command List There is an ISP command to read the device ID register. This register returns a code that reports the memory configuration of the ISD91300 series part as given inTable 7-3 Device ID Memory Size DID[7:0]...
Page 364: Register Map
ISD91300 Series Technical Reference Manual 7.4.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address: FMC_BA=0x5000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000...
Page 365: Register Description
ISD91300 Series Technical Reference Manual 7.4.7 Register Description ISP Control Register (FMC_ISPCTL) The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence Protected Register Lock Key Register (SYS_REGLCTL) ) to gain access. Register Offset Description Reset Value...
Page 366 ISD91300 Series Technical Reference Manual CONFIG Update Enable 0 = Disable. CFGUEN 1 = Enable. When enabled, ISP functions can access the CONFIG address space and modifydevice configuration area. [3:2] Reserved Reserved. Boot Select 0 = APROM. 1 = LDROM.
Page 367 ISD91300 Series Technical Reference Manual ISP Address Register (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADDR[31:24] ISPADDR[23:16] ISPADDR[15:8] ISPADDR[7:0] Bits Description ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP...
Page 368 ISD91300 Series Technical Reference Manual ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT[31:24] ISPDAT [23:16] ISPDAT [15:8] ISPDAT [7:0] Bits Description ISP Data Register [31:0] ISPDAT Write data to this register before an ISP program operation.
Page 369 ISD91300 Series Technical Reference Manual ISP Command (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:6] Reserved Reserved. ISP Command ISP command table is shown below: 0x00 = Read. 0x0B = Read Company ID (0xDA).
Page 370 ISD91300 Series Technical Reference Manual ISP Trigger Control Register (FMC_ISPTRG) The FMC_ISPTRG register is a protected register, user must first follow the unlock sequence Protected Register Lock Key Register (SYS_REGLCTL) ) to gain access. Register Offset Description Reset Value FMC_ISPTRG...
Page 371 ISD91300 Series Technical Reference Manual Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA[31:23] DFBA[23:16] DFBA[15:8] DFBA[7:0] Bits Description Data Flash Base Address This register reports the data flash starting address. It is a read only register.
Page 372: Analog Signal Path Blocks
8.1 Audio Analog-to-Digital Converter (ADC) 8.1.1 Overview The ISD91300 series includes a 2 Order Delta-Sigma Audio Analog-to-Digital converter providing SNR >85dB and THD >70dB.The converter can run at sampling rates up to 6.144MHz while a configurable decimation filter allows oversampling ratios of 64/128/192 and 384. This provides support for standard audio sampling rates from 8kHz to 48kHz.
Page 373: Figure 8-2 Adc Clock Control
ISD91300 Series Technical Reference Manual 8.1.4.1 ADC Clock Generator CLK_APBCLK0.ADCCKEN[28] ADC_CLK HCLK SD_CLK ÷ CLK_DIV ADC_CLKDIV.CLKDIV[7:0] Figure 8-2 ADC Clock Control 8.1.4.2 Determining Sample Rate The maximum clock rate of the Delta-Sigma Converter is 6.144MHz. Best performance is gained with clocks rates between 1.024MHz and 4.096MHz. Sample rate is given by the following ��...
Page 374: Figure 8-3 Sdadc Controller Interrupt
ISD91300 Series Technical Reference Manual ADC CLKDIV 3,072,000 48,000 24,000 16,000 8,000 2,048,000 32,000 16,000 10,667 5,333 1,536,000 24,000 12,000 8,000 4,000 1,024,000 16,000 8,000 5,333 2,667 Table 8-3 Sample Rates for HCLK=24.576MHz HCLK=16.384MHz Sample Rate (Hz) for OVSPLRAT SDCLK...
Page 375 ISD91300 Series Technical Reference Manual 8.1.4.5 Peripheral DMA Request Normal use of the ADC is with PDMA. In this mode ADC requests PDMA service whenever data is in FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full. In this way an entire buffer of data can be collected without any CPU intervention.
Page 376: Register Map
ISD91300 Series Technical Reference Manual 8.1.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ADCBase Address: ADC_BA = 0x400E_0000 ADC_DAT ADC_BA+0x00 ADC FIFO Data Out 0x0000_XXXX ADC_CHEN ADC_BA+0x04 R/W ADC Enable Register...
Page 377: Register Description
ISD91300 Series Technical Reference Manual 8.1.6 Register Description FIFO Audio Data Register (ADC_DAT) Register Offset Description Reset Value ADC_DAT ADC_BA+0x00 ADC FIFO Data Out 0x0000_XXXX Reserved Reserved RESULT [15:8] RESULT[7:0] Bits Description [31:16] Reserved Reserved. ADC Audio Data FIFO Read A read of this register will read data from the audio FIFO and increment the read pointer.
Page 378 ISD91300 Series Technical Reference Manual ADC Enable Register (ADC_CHEN) Register Offset Description Reset Value ADC_CHEN ADC_BA+0x04 ADC Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CHEN Bits Description [31:1] Reserved Reserved. ADC Enable CHEN 0 = Conversion stopped and ADC is reset including FIFO pointers.
Page 379 ISD91300 Series Technical Reference Manual ADC Clock Division Register (ADC_CLKDIV) Register Offset Description Reset Value ADC_CLKDIV ADC_BA+0x08 ADCClock Divider Register 0x0000_0000 Reserved Reserved Reserved CLKDIV Bits Description [31:8] Reserved Reserved. ADC Clock Divider This register determines the clock division ration between the incoming ADC_CLK (=HCLK by default) and the Delta-Sigma sampling clock of the ADC.
Page 380 ISD91300 Series Technical Reference Manual ADC Decimation Control Register (ADC_DCICTL) Register Offset Description Reset Value ADC_DCICTL ADC_BA+0x0C ADC Decimation Control Register 0x0000_0000 Reserved Reserved GAIN Reserved Reserved OVSPLRAT Bits Description [31:20] Reserved Reserved. CIC Filter Additional Gain [19:16] GAIN This should normally remain default 0. Can be set to non-zero values to provide additional digital gain from the decimation filter.
Page 381 ISD91300 Series Technical Reference Manual ADC Interrupt Control Register (ADC_INTCTL) Register Offset Description Reset Value ADC_INTCTL ADC_BA+0x10 ADC Interrupt Control Register 0x0000_0000 INTEN Reserved Reserved Reserved Reserved FIFOINTLV Bits Description Interrupt Enable INTEN [31] If set to ‘1’ an interrupt is generated whenever FIFO level exceeds that set in FIFOINTLV.
Page 382 ISD91300 Series Technical Reference Manual ADC PDMA Control Register (ADC_PDMACTL) Register Offset Description Reset Value ADC_PDMACTL ADC_BA+0x14 ADC PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RXDMAEN Bits Description [31:1] Reserved Reserved. Enable ADC PDMA Receive Channel RXDMAEN Enable ADC PDMA. If set, then ADC will request PDMA service when data is available.
Page 383 ISD91300 Series Technical Reference Manual A/D Compare Register 0/1 (ADC_CMP0/1) Register Offset Description Reset Value ADC_CMP0 ADC_BA+0x18 ADC Comparator 0 Control Register 0x0000_0000 ADC_CMP1 ADC_BA+0x1C ADC Comparator 1 Control Register 0x0000_0000 CMPDAT[15:8] CMPDAT[15:8] Reserved CMPMCNT CMPFLAG Reserved CMPCOND ADCMPIE ADCPMEN...
Page 384: Audio Class D Speaker Driver (Dpwm)
8.2 Audio Class D Speaker Driver (DPWM) 8.2.1 Overview The ISD91300 series includes a differential Class D (PWM) speaker driver capable of delivering 1W into an 8Ω load at 5V supply voltage. The driver works by up-sampling and modulating a PCM input to differentially drive the SPK+ and SPK- pins.
Page 385: Table 8-5 Dpwm Sample Rates For Various Hclk
ISD91300 Series Technical Reference Manual 8.2.4.1 Determining Sample Rate �� = �� ÷ ��_�� ÷ 64 The sample rate at which the DPWM block consumes audio data is given by: �� Where HCLK is the master CPU clock rate and DPWM_ZOHDIV is the divider control register. A table of common audio sample rates is provided below.
Page 386: Register Map
ISD91300 Series Technical Reference Manual 8.2.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value DPWM Base Address: DPWM_BA = 0x4007_0000 DPWM_CTL DPWM_BA+0x00 R/W DPWM Control Register 0x0000_0000 DPWM_STS DPWM_BA+0x04 R...
Page 387: Register Description
ISD91300 Series Technical Reference Manual 8.2.6 Register Description DPWM Control Register (DPWM_CTL) Register Offset Description Reset Value DPWM_CTL DPWM_BA+0x00 DPWM Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DPWMEN DITHEREN DEADTIME MODUFRQ Bits Description [31:7] Reserved Reserved. DPWM Enable 0 = Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset DPWMEN (FIFO data is not reset).
Page 388 ISD91300 Series Technical Reference Manual DPWM FIFO Status Register (DPWM_STS) Register Offset Description Reset Value DPWM_STS DPWM_BA+0x04 DPWM DATA FIFO Status Register 0x0000_0002 Reserved Reserved Reserved Reserved EMPTY FULL Bits Description [31:2] Reserved Reserved. FIFO Empty EMPTY 0= FIFO is not empty.
Page 389 ISD91300 Series Technical Reference Manual DPWM PDMA Control Register(DPWM_DMACTL) Register Offset Description Reset Value DPWM_DMACTL DPWM_BA+0x08 DPWM PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DMAEN Bits Description [31:1] Reserved Reserved. Enable DPWM DMA Interface 0= Disable PDMA. No requests will be made to PDMA controller.
Page 390 ISD91300 Series Technical Reference Manual DPWM FIFO Input (DPWM_DATA) Register Offset Description Reset Value DPWM_DATA DPWM_BA+0x0C W DPWM DATA FIFO Input 0x0000_0000 Reserved Reserved INDATA[15:8] INDATA[7:0] Bits Description [31:16] Reserved Reserved. DPWM FIFO Audio Data Input [15:0] INDATA A write to this register pushes data onto the DPWM FIFO and increments the write pointer.
Page 391 ISD91300 Series Technical Reference Manual DPWM ZOH Division (DPWM_ZOHDIV) Register Offset Description Reset Value DPWM_ZOHDIV DPWM_BA+0x10 DPWM Zero Order Hold Division Register 0x0000_0030 Reserved Reserved Reserved ZOHDIV[7:0] Bits Description [31:8] Reserved Reserved. DPWM Zero Order Hold, Down-Sampling Divisor The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this...
Page 392: Analog Comparator (Acmp)
8.3 Analog Comparator (ACMP) 8.3.1 Overview ISD91300 series contains two analog comparators. The comparator output is a logical one when positive input greater than negative input, otherwise the output is a zero. Each comparator can be configured to cause an interrupt when the comparator output value changes. The block diagram is shown inFigure 8-5 Analog Comparator Block Diagram.
Page 393: Functional Description
ISD91300 Series Technical Reference Manual 8.3.4 Functional Description 8.3.4.1 Setup Procedure To use the Analog Comparator block, use the following sequence:  Configure GPIO for use as analog input by setting type to input.  Enable the peripheral clock (CLK_APBCLK0.ACMPCKEN) ...
Page 394: Register Map
ISD91300 Series Technical Reference Manual 8.3.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ACMPBase Address: ACMP_BA = 0x400D_0000 ACMP_CTL0 ACMP_BA+0x00 Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP_BA+0x04 Analog Comparator 1 Control Register...
Page 395: Register Description
ISD91300 Series Technical Reference Manual 8.3.6 Register Description Comparator 0 Control Register (ACMP_CTL0) Register Offset Description Reset Value ACMP_CTL0 ACMP_BA+0x00 Analog Comparator 0 Control Register 0x0000_0000 Reserved Reserved Reserved Reserved NEGSEL Reserved ACMPIE ACMPEN Bits Description [31:5] Reserved Reserved. Comparator0Negative Input Select NEGSEL 0 = VBG, Bandgap reference voltage = 1.2V.
Page 396 ISD91300 Series Technical Reference Manual Comparator 1 Control Register (ACMP_CTL1) Register Offset Description Reset Value ACMP_CTL1 ACMP_BA+0x04 Analog Comparator 1 Control Register 0x0000_0000 Reserved Reserved Reserved Reserved NEGSEL Reserved ACMPIE ACMPEN Bits Description [31:5] Reserved Reserved. Comparator1Negative Input Select NEGSEL 0 = GPIOB[7].
Page 397 ISD91300 Series Technical Reference Manual CMP Status Register (ACMP_STATUS) Register Offset Description Reset Value ACMP_STATUS ACMP_BA+0x08 Comparator Status Register 0x0000_00XX Reserved Reserved Reserved Reserved ACMPO1 ACMPO0 ACMPIF1 ACMPIF0 Bits Description [31:4] Reserved Reserved. Comparator1 Output ACMPO1 Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN = 0).
Page 398 ISD91300 Series Technical Reference Manual CMP Select Register (ACMP_POSSEL) Register Offset Description Reset Value ACMP_POSSEL ACMP_BA+0x0C Comparator Select Register 0x0000_0000 Reserved Reserved Reserved Reserved POSSEL Bits Description [31:3] Reserved Reserved. Comparator0 GPIO Selection [2:0] POSSEL GPIOB[POSSEL] is the active analog GPIO input selected to Comparator 0 positive input.
Page 399: Analog Functional Blocks
ISD91300 Series Technical Reference Manual 8.4 Analog Functional Blocks 8.4.1 Overview The ISD91300 contains a variety of analog functional blocks that facilitate audio processing, enable analog GPIO functions (current source, relaxation oscillator, and comparator), adjust and measure internal oscillator and provide voltage regulation. These blocks are controlled by registers in the analog block address space.
Page 400: Gpio Current Source Generation
ISD91300 Series Technical Reference Manual 8.4.4 GPIO Current Source Generation The GPIOB[11:0] and GPIOA[11:8] provide 16 pins of analog enabled GPIO. One of the features of these pins is the ability to route a current source to the pin. This is useful for a variety of purposes such as providing a current load to a sensor such as a photo-transistor or CDS cell.
Page 401: Ldo Power Domain Control
ISD91300 Series Technical Reference Manual 8.4.5 LDO Power Domain Control The ISD91300 provides a Low Dropout Regulator (LDO) that provides power to the I/O domain of GPIOA[7:0]& GPIOB[13:12]. Using this regulator device can operate from a 5V supply rail and generate a 2.4-3.3V regulated supply to operate the GPIOA[7:0]&...
Page 402: Microphone Bias Generator
ISD91300 Series Technical Reference Manual 8.4.6 Microphone Bias Generator The ISD91300 provides a microphone bias generator (MICBIAS) for improved recording quality. The MICBIAS can provide a maximum current of 1mA with a -60dB power supply rejection. The MICBIAS output voltage can be configured with ANA_MICBSEL[1:0] to select bias voltages from 50% to90% of the VCCA supply voltage (seedescription below).
Page 403: Analog Multiplexer
ISD91300 Series Technical Reference Manual 8.4.7 Analog Multiplexer The ISD91300 provides an analog multiplexer (ANA_MUXCTL) which allows the PGA input to be switched from the dedicated MICP/MICN analog inputs to any of the analog enabled GPIO (GPIOB[7:0]). The negative input of the PGA connects to GPIOB[7:0], while the positive PGA input connects to the odd numbered GPIOB[7:1].
Page 404: Temperature Sensor Measurement
ISD91300 Series Technical Reference Manual 8.4.8 Temperature Sensor Measurement In addition, the multiplexer can route a PTC (positive temperature coefficient) current, PTAT current, to the ADC to perform temperature measurements. To configure the signal path to do temperature measurement, configure the ADC path as follows: ...
Page 405: Programmable Gain Amplifier
ISD91300 Series Technical Reference Manual 8.4.9 Programmable Gain Amplifier The ISD91300 provides a Programmable Gain Amplifier (PGA) as the front-end to the ADC to allow the adjustment of signal path gain. It is used in conjunction with the ALC block to provide automatic level control of incoming audio signals.
Page 406: Table 8-7 Pga Input Impedance Variation With Gain Setting
ISD91300 Series Technical Reference Manual Gain (dB) 35.2 MICN Impedance (kΩ) 75 MICPImpedance (kΩ) Table 8-7 PGA Input Impedance Variation with Gain Setting Sep 9, 2019 Page 406 of 466 Revision 1.13...
Page 407: Capsense Relaxation Oscillator/Counter
ISD91300 Series Technical Reference Manual 8.4.10 CapSense Relaxation Oscillator/Counter The ISD91300 provides a functional unit that is used with analog GPIO functions to form a relaxation oscillator. The major application of this function is to measure the capacitive load on a GPIO pin.
Page 408 ISD91300 Series Technical Reference Manual the resolution. The higher the cycle count the slower the measurement but the higher the accuracy and noise immunity. Sep 9, 2019 Page 408 of 466 Revision 1.13...
Page 409: Oscillator Frequency Measurement And Control
ISD91300 Series Technical Reference Manual 8.4.11 Oscillator Frequency Measurement and Control The ISD91300 provides a functional unit that can be used to measure PCLK frequency given a reference frequency such as the 32.768kHz crystal or an I2S frame synchronization signal. This is simply a special purpose timer/counter as shown inFigure 8-17 Oscillator Frequency Measurement Block Diagram.
Page 410: Figure 8-18 Example Superfine Trim Frequency Adjustment
ISD91300 Series Technical Reference Manual 49400000 Oscillator Frequency (Hz) 49300000 49200000 SUPERFINE trim value 49100000 49000000 48900000 48800000 48700000 48600000 -128 SUPERFINE Figure 8-18 Example SUPERFINE Trim Frequency Adjustment 79872000 76800000 73728000 70656000 67584000 64512000 61440000 58368000 55296000 52224000 49152000...
Page 411: Register Map
ISD91300 Series Technical Reference Manual 8.4.12 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ANA Base Address: ANA_BA = 0x4008_0000 ANA_VMID ANA_BA+0x00 VMID Reference Control Register 0x0000_0007 ANA_CURCTL0 ANA_BA+0x08 Current Source Control Register...
Page 412: Register Description
ISD91300 Series Technical Reference Manual 8.4.13 Register Description VMID Control Register (ANA_VMID) Register Offset Description Reset Value ANA_VMID ANA_BA+0x00 VMID Reference Control Register 0x0000_0007 Reserved Reserved Reserved Reserved PDHIRES PDLORES PULLDOWN Bits Description [31:3] Reserved Reserved. Power Down High (360kΩ) Resistance Reference 0= Connect the High Resistance reference to VMID.
Page 413 ISD91300 Series Technical Reference Manual Current Source Control Register (ANA_CURCTL0) Register Offset Description Reset Value ANA_CURCTL0 ANA_BA+0x08 Current Source Control Register 0x0000_0000 Reserved Reserved Reserved VALSEL CURSRCEN[7:0] Bits Description [31:10] Reserved Reserved. Current Source Value Select master current for source generation 0= 0.5uA.
Page 414 ISD91300 Series Technical Reference Manual Current Source Control Register (ANA_CURCTL1) Register Offset Description Reset Value ANA_CURCTL1 ANA_BA+0x0C Current Source Control Register 1 0x0000_0000 Reserved Reserved CURSRCEN[15:8] CURSRCEN[7:0] Bits Description [31:16] Reserved Reserved. Enable Current Source To GPIOB[X], GPIOA[X-4] Individually enable current source to GPIO pins. Each GPIOB[11:0] and GPIOA[11:8] pin has a separate current source.
Page 415 ISD91300 Series Technical Reference Manual LDO Voltage Control Register (ANA_LDOSEL) Register Offset Description Reset Value ANA_LDOSEL ANA_BA+0x20 LDO Voltage Select Register 0x0000_0000 Reserved Reserved Reserved Reserved LDOSEL Bits Description [31:2] Reserved Reserved. Select LDO Output Voltage Note that maximum I/O pad operation speed only specified for voltage >2.4V.
Page 416 ISD91300 Series Technical Reference Manual LDO Power Down Register (ANA_LDOPD) Register Offset Description Reset Value ANA_LDOPD ANA_BA+0x24 LDO Power DownRegister 0x0000_0001 Reserved Reserved Reserved Reserved DISCHAR Bits Description [31:2] Reserved Reserved. Discharge DISCHAR 0 = No load on VD33. 1 = Switch discharge resistor to VD33.
Page 417 ISD91300 Series Technical Reference Manual Microphone Bias Select (ANA_MICBSEL) Register Offset Description Reset Value ANA_MICBSEL ANA_BA+0x28 Microphone Bias Select Register 0x0000_0000 Reserved Reserved Reserved Reserved REFSEL VOLSEL Bits Description [31:3] Reserved Reserved. Select Reference Source For MICBIAS Generator VMID provides superior noise performance for MICBIAS generation and should be used...
Page 418 ISD91300 Series Technical Reference Manual Microphone Bias Enable Register (ANA_MICBEN) Register Offset Description Reset Value ANA_MICBEN ANA_BA+0x2C Microphone Bias Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved MICBEN Bits Description [31:1] Reserved Reserved. Enable Microphone Bias Generator MICBEN 0 = Powered Down.
Page 419 ISD91300 Series Technical Reference Manual Analog Multiplexer Control Register (ANA_MUXCTL) Register Offset Description Reset Value ANA_MUXCTL ANA_BA+0x50 Analog Multiplexer Control Register 0x0000_0000 Reserved Reserved Reserved MUXEN PGAINSEL PTATCUR POSINSEL NEGINSEL Bits Description [31:15] Reserved Reserved. Enable The Analog Multiplexer [14] MUXEN 0 = All channels disabled.
Page 420 ISD91300 Series Technical Reference Manual PGA Enable Register (ANA_PGACTL) Register Offset R/W Description Reset Value ANA_PGACTL ANA_BA+0x60 R/W PGA EnableRegister 0x0000_0000 Reserved Reserved Reserved Reserved BSTGAIN PUBOOST PUPGA REFSEL Bits Description [31:4] Reserved Reserved. Boost Stage Gain Setting BSTGAIN 0 = Gain = 0dB.
Page 421 ISD91300 Series Technical Reference Manual Signal Path Control Register (ANA_SIGCTL) Register Offset R/W Description Reset Value ANA_SIGCTL ANA_BA+0x64 R/W Signal Path Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MUTEBST MUTEPGA PUADCOP PUCURB PUBUFADC PUBUFPGA PUZCDCMP Bits Description [31:7] Reserved Reserved.
Page 422 ISD91300 Series Technical Reference Manual 0 = Power down. 1 = Power up and enable zero cross detection. Sep 9, 2019 Page 422 of 466 Revision 1.13...
Page 423 ISD91300 Series Technical Reference Manual PGA GAIN Control Register (ANA_PGAGAIN) Register Offset R/W Description Reset Value ANA_PGAGAIN ANA_BA+0x68 R/W PGA Gain Select Register 0x0000_0010 Reserved Reserved Reserved GAINREAD Reserved GAINSET Bits Description [31:14] Reserved Reserved. Current PGA Gain Value [13:8] GAINREAD Read Only.
Page 424 ISD91300 Series Technical Reference Manual Capacitive Touch Sensing Control Register (ANA_CAPSCTL) Register Offset Description Reset Value ANA_CAPSCTL ANA_BA+0x8C Capacitive Touch Sensing Control Register 0x0000_0000 CAPSEN INTEN RSTCNT Reserved Reserved CLKDIV Reserved CLKMODE CYCLECNT LOWTIME Bits Description Enable CAPSEN [31] 0 = Disable/Reset block.
Page 425 ISD91300 Series Technical Reference Manual Capacitive Touch Sensing Count Register (ANA_CAPSCNT) Register Offset Description Reset Value ANA_CAPSCNT ANA_BA+0x90 Capacitive Touch Sensing Count Register 0x0000_0000 Reserved CAPSCNT[23:16] CAPSCNT[15:8] CAPSCNT[7:0] Bits Description [31:24] Reserved Reserved. [23:0] CAPSCNT Counter Read Back Value Of Capacitive Touch Sensing Block...
Page 426 ISD91300 Series Technical Reference Manual Oscillator Trim Register (ANA_TRIM) Register Offset R/W Description Reset Value ANA_TRIM ANA_BA+0x84 R/W Oscillator Trim Register 0x0000_XXXX Reserved SUPERFINE COARSE OSCTRIM Bits Description [31:24] Reserved Reserved. Superfine The SUPERFINE trim setting is an 8bit signed integer. It adjusts the master oscillator by...
Page 427 ISD91300 Series Technical Reference Manual Frequency Measurement Control Register (ANA_FQMMCTL) Register Offset R/W Description Reset Value ANA_FQMMCTL ANA_BA+0x94 R/W Frequency Measurement Control Register 0x0000_0001 FQMMEN Reserved CYCLESEL Reserved Reserved MMSTS CLKSEL Bits Description FQMMEN [31] FQMMEN 0 = Disable/Reset block.
Page 428 ISD91300 Series Technical Reference Manual Frequency Measurement Count (ANA_FQMMCNT) Register Offset R/W Description Reset Value ANA_FQMMCNT ANA_BA+0x98 Frequency Measurement Count Register 0x0000_0000 Reserved Reserved FQMMCNT[15:8] FQMMCNT[7:0] Bits Description [31:16] Reserved Reserved. Frequency Measurement Count When MMSTS=1 and FQMMEN=1, this is number of PCLK periods counted for frequency measurement.
Page 429 ISD91300 Series Technical Reference Manual Frequency Measurement Cycle (ANA_FQMMCYC) Register Offset R/W Description Reset Value ANA_FQMMCYC ANA_BA+0x9C R/W Frequency Measurement Cycle Register 0x0000_0000 Reserved FQMMCYC[23:16] FQMMCYC[15:8] FQMMCYC[7:0] Bits Description [31:24] Reserved Reserved. Frequency Measurement Cycles Number of reference clock periods plus one to measure target clock (PCLK). For example if...
Page 430: Automatic Level Control (Alc)
ISD91300 Series Technical Reference Manual 8.5 Automatic Level Control (ALC) 8.5.1 Overview The ALC seeks to control the PGA gain such that the PGA output maintains a constant envelope. This helps to prevent clipping at the input of the sigma delta ADC while maximizing the full dynamic range of the ADC.
Page 431: Basic Configuration
ISD91300 Series Technical Reference Manual 8.5.3 Basic Configuration The ALC is enabled by setting ALCEN. The ALC shares a clock source with the Biquad filter so CLK_APBCLK0.BQALCKENmust be set to operate ALC. The ALC has two functional modes, which is set by MODESEL.
Page 432: Figure 8-22 Alc Normal Mode Operation
ISD91300 Series Technical Reference Manual 8.5.4.1 Normal Mode Normal mode is selected when MODESEL is set LOW and the ALC is enabled by setting ALCEN HIGH. This block adjusts the PGA gain setting up and down in response to the input level. A peak detector circuit measures the envelope of the input signal and compares it to the target level set by TARGETLV.
Page 433: Figure 8-24 Alc Limit Mode Operation
ISD91300 Series Technical Reference Manual 8.5.4.2 Peak Limiter Mode Peak Limiter mode is selected when MODESEL is set to HIGH and the ALC is enabled by setting ALCEN. In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at the time the limiter mode is enabled.
Page 434: Figure 8-25 Alc Operation With Noise Gate Disabled
ISD91300 Series Technical Reference Manual (Signal at ADC – PGA gain – MIC Boost gain) < NGTH (dB) Levels at the extremes of the range may cause inappropriate operation, so care should be taken when setting up the function. PGA Input...
Page 435 ISD91300 Series Technical Reference Manual If the zero crossing function is enabled (using either register), the zero cross timeout function may take effect. If the zero crossing flag does not change polarity within 0.25 seconds of a PGA gain update (either via ALC update or PGA gain register update), then the gain will update. This backup system prevents the gain from locking up if the input signal has a small swing and a DC offset that prevents the zero crossing flag from toggling.
Page 436: Register Map
ISD91300 Series Technical Reference Manual 8.5.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ALC Base Address: ALC_BA = 0x400B_0048 ALC_CTL ALC_BA+0x00 ALC Control Register 0x0E01_6320 ALC_STS ALC_BA+0x04 ALC statusregister...
Page 437: Register Description
ISD91300 Series Technical Reference Manual 8.5.6 Register Description ALC Control Register (ALC_CTL) Register Offset Description Reset Value ALC_CTL ALC_BA+0x00 ALC Control Register 0x0E01_6320 PKLIMEN PKSEL NGPKSEL ALCEN MAXGAIN MINGAIN[2] MINGAIN[1:0] ZCEN HOLDTIME TARGETLV[3] TARGETLV[2:0] MODESEL DECAYSEL ATKSEL NGEN NGTHBST Bits...
Page 438 ISD91300 Series Technical Reference Manual 3 = 6dB. 4 = 12 dB. 5 = 18 dB. 6 = 24 dB. 7 = 30dB. ALC Zero Crossing [21] ZCEN 0 = zero crossing disabled. 1 = zero crossing enabled. ALC Hold Time...
Page 439 ISD91300 Series Technical Reference Manual ALC Status Register (ALC_STS) Register Offset Description Reset Value ALC_STS ALC_BA+0x04 ALC statusregister 0x0000_0000 Reserved Reserved PEAKVAL[8:5] PEAKVAL[4:0] P2PVAL[8:6] P2PVAL[5:0] NOISEF CLIPFLAG Bits Description [31:19] Reserved Reserved. Peak Value [18:11] PEAKVAL 9 MSBs of measured absolute peak value...
Page 440 ISD91300 Series Technical Reference Manual ALC Interrupt Register (ALC_INTSTS) Register Offset Description Reset Value ALC_INTSTS ALC_BA+0x08 ALC interrupt register 0x0000_0000 Reserved Reserved Reserved Reserved INTFLAG Bits Description [31:1] Reserved Reserved. ALC Interrupt This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated,...
Page 441 ISD91300 Series Technical Reference Manual ALC Interrupt Enable Register(ALC_INTCTL) Register Offset Description Reset Value ALC_INTCTL ALC_BA+0x0C ALC interrupt enable register 0x0000_0000 Reserved Reserved Reserved Reserved INTEN Bits Description [31:1] Reserved Reserved. ALC Interrupt Enable INTEN 0 = INTEN disabled. 1 = INTEN enabled.
Page 442: Biquad Filter (Biq)
ISD91300 Series Technical Reference Manual 8.6 Biquad Filter (BIQ) 8.6.1 Overview A coefficient programmable 3-stage Biquad filter (6 -Order IIR filter) is available which can be used on either ADC path or DPWM path to further reduce unwanted noise or filter the signal.
Page 443 ISD91300 Series Technical Reference Manual  Decide the ADC or DPWM path to be used for the BIQ by programming PATHSEL, and turn off PRGCOEFF bit (if it was turned on in step #2).  Turn on BIQ_CTL.EN. BIQ will start filter function.
Page 444: Register Map
ISD91300 Series Technical Reference Manual 8.6.4 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value BIQ Base Address: BIQ_BA = 0x400B_0000 Coefficient b0 In H(z) Transfer Function BIQ_COEFF0 BIQ_BA + 0x00 0x0000_d010 (3.16 format) - 1...
Page 445: Register Description
ISD91300 Series Technical Reference Manual 8.6.5 Register Description BIQ Control Register (BIQ_CTL) Register Offset Description Reset Value BIQ_CTL BIQ_BA+0x040 BIQ Control Register 0x0BFF_0030 Reserved SRDIV[12:8] SRDIV[7:0] Reserved Reserved DPWMPUSR DLCOEFF PRGCOEFF PATHSEL BIQEN Bits Description [31:29] Reserved Reserved. Sample Rate Divider This register is used to program the operating sampling rate of the biquad filter.
Page 446 ISD91300 Series Technical Reference Manual 1 = BIQ filter is on. Sep 9, 2019 Page 446 of 466 Revision 1.13...
Page 447 ISD91300 Series Technical Reference Manual BIQ Coefficient (BIQ_COEFFn) Register Offset Description Reset Value Coefficient b0 In H(z) Transfer Function BIQ_COEFF0 BIQ_BA + 0x00 0x0000_d010 (3.16 format) - 1 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function BIQ_COEFF1 BIQ_BA+0x004 0x0001_c020 (3.16 format) - 1...
Page 448 ISD91300 Series Technical Reference Manual COEFFDAT[7:0] Bits Description [31:0] COEFFDAT Coefficient Data Sep 9, 2019 Page 448 of 466 Revision 1.13...
Page 449: Application Diagram
ISD91300 Series Technical Reference Manual APPLICATION DIAGRAM VCCD 48 VCCFS VCCD 0.1uF VSSD PB.13/MOSI1/PWM5/PWM4B PA.3/MISO0/I2C_SDA VCCD PA.2/SSB0 VCC_PWM 44 VDD33 VCC_PWM VSS_PWM DO(IO1) HOLD(IO3) PB.12/MISO1/I2C_SCL PA.1/SCLK/I2C_SCL SPK+ WP(IO2) DI(IO0) PA.0/MOSI0/MCLK SPK- ISD9361 W25Q(SPI/Dual/Quad) XI32K 32.768K LQFP 64-pin XO32K 53 20pF 20pF 4.7uF...
Page 450: Electrical Characteristics
ISD91300 Series Technical Reference Manual 10 ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings SYMBOL PARAMETER UNIT -0.3 +6.0 DC Power Supply VDD−VSS Input Voltage VSS-0.3 VDD+0.3 Oscillator Frequency CLCL °C Operating Temperature °C Storage Temperature +150 Maximum Current into V Maximum Current out of V...
Page 451: Dc Electrical Characteristics
ISD91300 Series Technical Reference Manual 10.2 DC Electrical Characteristics (VDD-VSS=3.3V, TA = 25°C, F = 49.152 MHz unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Operation voltage =2.4V ~ 5.5V up to 100 MHz Power Ground -0.3...
Page 452 ISD91300 Series Technical Reference Manual SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT = 3V, SLEEP disable all IP, M0 Sleep (WFI) = 5.5V, Enable all IP. =5.5V, disable all IP Operating Current = 3V, Normal Run Mode 34.1...
Page 453: Table 10-2 Dc Electrical Characteristics
ISD91300 Series Technical Reference Manual Logic 1 to 0 Transition Current µA -650 -200 = 5.5V, V <2.0V PA~PB(Quasi-bidirectional mode) -0.3 = 4.5V Input Low Voltage PA, PB(TTL input) -0.3 = 2.5V +0.2 = 5.5V Input High Voltage PA, PB (TTL input) 1.51...
Page 454: Operating Current Curve (Test Condition: Run Nop)
ISD91300 Series Technical Reference Manual 10.2.1 Special Characteristic Isb test Conditions: VCCD = 3.3V, VCCA = 3.3V, T = +25°C, Running mode = SPD/DPD, clock source = internal 49.152 MHz oscillator OR internal low power 16KHz oscillator, RTC source = External 32KHZ crystal.
Page 455: Ac Electrical Characteristics
ISD91300 Series Technical Reference Manual 10.3 AC Electrical Characteristics 10.3.1 External 32kHz XTAL Oscillator PARAMETER CONDITION MIN. TYP. MAX. UNIT Input clock frequency External crystal 32.768 ℃ Temperature Table 10-3 External 32kHz XTAL Oscillator 10.3.2 Internal 49.152MHz Oscillator PARAMETER CONDITION MIN.
Page 456: Analog Characteristics
ISD91300 Series Technical Reference Manual 10.4 Analog Characteristics 10.4.1 Specification of ADC and Speaker Driver Conditions: VCCD = 3.3V, VCCA = 3.3V, T = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless otherwise stated. Parameter Symbol Comments/Conditions Units...
Page 457: Adc Filter Characteristics
ISD91300 Series Technical Reference Manual 10.4.2 ADC Filter Characteristics Below are responses of ADC with and without various biquaddownsample filters for 16kHz sample rate. The biquad correction filters compensate for SINC filter droop with greater passband ripple while the LPF filters are maximally flat but roll off with SINC response as can be seen in the passband figure.
Page 458: Figure 10-3 Adc Filter Characteristics Zoom In
ISD91300 Series Technical Reference Manual Audio Precision 12/17/13 15:41 -2.2 -2.4 -2.6 -2.8 -3.2 -3.4 -3.6 -3.8 -4.2 -4.4 -4.6 -4.8 -5.2 -5.4 -5.6 -5.8 Sweep Trace Color Line Style Thick Data Axis Comment Solid DSP Anlr.Level A Left SINC OSR=192...
Page 459: Specification Of Pga And Boost
ISD91300 Series Technical Reference Manual 10.4.3 Specification of PGA and BOOST Conditions: VCCD = 3.3V, VCCA = 3.3V, T = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless otherwise stated. Parameter Symbol Comments/Conditions Units Microphone Inputs (MICP, MICN) and Programmable Gain Amplifier (PGA)
Page 460: Specification Of Alc An Micbias
ISD91300 Series Technical Reference Manual 10.4.4 Specification of ALC an MICBIAS Conditions: VCCD = 3.3V, VCCA = 3.3V, T = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless otherwise stated. Parameter Symbol Comments/Conditions Units Automatic Level Control (ALC) & Limiter: Target record level -22.5...
Page 461: Specification Of Ldo & Power Management
ISD91300 Series Technical Reference Manual 10.4.5 Specification of LDO & Power management PARAMETER UNIT NOTE Input Voltage input voltage Output Voltage -10% +10% > 1.8 Notes It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VCCD and the VSSD pin of the device.
Page 462: Specification Of Power-On Reset (Vccd)
ISD91300 Series Technical Reference Manual BOV_VL [2:0]=110 BOV_VL [2:0]=111 Hysteresis Table 10-10 Specification of Brownout Detector 10.4.7 Specification of Power-On Reset (VCCD) PARAMETER CONDITION MIN. TYP. MAX. UNIT ℃ Temperature Reset voltage VCC ramping down Reset Release voltage VCC ramping up Quiescent current Vin>reset voltage...
Page 463: Table 10-13 Specification Of Comparator
ISD91300 Series Technical Reference Manual Input offset voltage 15mV Input common mode range VDD-1.2 DC gain 70dB Propagation delay 200ns @VCM=1.2V & VDIFF=0.1V 20mV@VCM=1V 50mV@VCM=0.1V Comparison voltage 10mV 20mV 50mV@VCM=VDD-1.2 @10mV for non-hysteresis One bit control Hysteresis ±10mV W/O & W. hysteresis @VCM=0.4V ~ VDD-1.2V...
Page 464: Package Dimensions
ISD91300 Series Technical Reference Manual 11 PACKAGE DIMENSIONS 11.1 64L LQFP (7x7x1.4mm footprint 2.0mm) Sep 9, 2019 Page 464 of 466 Revision 1.13...
Page 465 ISD91300 Series Technical Reference Manual 12 ORDERING INFORMATION 1 3 x x x x x Temperature ISD Audio Product Family I: -40°C ~ +85°C Product Series 1: Cortex-M0 Package R: LQFP-64 Family ID 3: Family Series ID SW Feature Blank: Standard...
Page 466: Revision History
Change cover title. Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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