Texas Instruments DAC63202W Manual

Texas Instruments DAC63202W Manual

12-bit, dual, voltage and current output smart dacs with auto‑detected i2c, spi, or pmbus™ interface in dsbga

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DAC63202W 12-Bit, Dual, Voltage and Current Output Smart DACs
With Auto‑Detected I
1 Features
Programmable voltage or current outputs with
flexible configuration:
– Voltage outputs:
1 LSB DNL
Gains of 1 ×, 1.5 ×, 2 ×, 3 ×, and 4 ×
– Current outputs:
1 LSB INL and DNL (8-bit)
±25 μA, ±50 μA, ±125 μA, ±250 μA output-
range options
Programmable comparator mode for all channels
High-impedance output when VDD is off
High-impedance and resistive pulldown power-
down modes
50-MHz SPI-compatible interface
Automatically detects I
interface
– 1.62-V V
with V
IH
DD
General-purpose input/output (GPIO) configurable
as multiple functions
Predefined waveform generation: sine, cosine,
triangular, sawtooth
User-programmable nonvolatile memory (NVM)
Internal, external, or power-supply as reference
Wide operating range:
– Power supply: 1.8 V to 5.5 V
– Temperature: –40˚C to +125˚C
Tiny package:
– 16-pin DSBGA: 1.72 mm × 1.72 mm, nominal
V
IN
PH
IN
BOOT
SMPS / LDO
SENSE
GND
Power-supply: 0
Power-supply: 1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
2
C, SPI, or PMBus™ Interface in DSBGA
2
C, SPI, or PMBus
= 5.5 V
L
R
1
C
L
C
B
V
R
Voltage Margining and Scaling Using the DAC63202W
2 Applications
Optical module
High performance computing
Standard notebook PC
3 Description
The DAC63202W is a 12-bit, dual-channel, buffered,
voltage-output and current-output smart digital-to-
analog converter (DAC). The DAC63202W devices
support Hi-Z power-down mode and Hi-Z output
during power-off conditions. The DAC outputs provide
a force-sense option for use as a programmable
comparator and current sink. The multifunction GPIO,
function generation, and programmable nonvolatile
memory (NVM) enable these smart DACs for
processor-less applications and design reuse. This
device automatically detects I
interfaces, and contain an internal reference.
The feature set combined with the tiny package
and low power make this smart DAC an excellent
choice for applications such as voltage margining and
scaling, dc set-point for biasing and calibration, and
waveform generation.
Package Information
PART NUMBER
DAC63202W
YBH (DSBGA, 16)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
0.1 μ
VREF
V
OUT
R
3
VOUT/
FB
IOUT
R
3
2
VOUT/
IOUT
Output Configuration
DAC63202W
SLASF73 – APRIL 2023
2
C, SPI and PMBus
(1)
PACKAGE
BODY SIZE (NOM)
1.72 mm × 1.72 mm
VDD
10 kΩ
CAP
LDO
Internal
NVM
Reference
DAC
DAC
REG
BUF
DAC
DAC
REG
BUF
Logic
DAC63202W
AGND
1.5 μ p
SCL/SYNC
SDA/SCLK
A0/SDI
PROTECT

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  • Page 1 DAC63202W SLASF73 – APRIL 2023 DAC63202W 12-Bit, Dual, Voltage and Current Output Smart DACs With Auto‑Detected I C, SPI, or PMBus™ Interface in DSBGA 1 Features 2 Applications • Programmable voltage or current outputs with • Optical module flexible configuration: •...
  • Page 2: Table Of Contents

    6.17 Typical Characteristics: Voltage Output....4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES April 2023 Initial Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 3: Description

    C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external SDA/SCLK Input/Output pullup resistor in the I C mode. This pin can ramp up before VDD. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 4: Absolute Maximum Ratings

    Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 18.8 °C/W For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 5 , gain = 3 × or 4 × Power supply rejection ratio Internal V , gain = 2 ×, DAC at midscale, 0.25 mV/V (dc) = 5 V ±10% Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 6: Electrical Characteristics: Voltage

    × (total number of channels powered on) + (sleep-mode current). When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show parametric drift. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 7: Electrical Characteristics: Current

    OUTx pins. The V pin is connected to The total power consumption is calculated by I × (total number of channels powered on) + (sleep-mode current). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 8: Electrical Characteristics: Comparator

    DAC output is 25 pF Specified by design and characterization, not production tested. This specification does not include the total unadjusted error (TUE) of the DAC. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 9 10 kΩ at OUT pin Specified by design and characterization, not production tested. Measured at –40°C and +125°C and calculated the slope. Impedances for the DAC channels are connected in parallel. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 10 = 10 pF 0.45 µs VDDAT trace probe Data valid acknowledge time, R = 360 Ω, C = 23 pF, C = 10 pF 0.45 µs VDACK trace probe Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 11 SCLK falling edge to SYNC rising edge SYNC high time µs CSHIGH SCLK rising edge to SDO falling edge, I ≤ 5 mA, C = 20 pF. SDODLY Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 12 Figure 6-1. I C Timing Diagram CSHIGH SYNC SCLKLOW SCLK SCLKHIGH SDIS SDIH Bit 23 Bit 1 Bit 0 GPIO/ LDAC CS2LDAC LDACW Figure 6-2. SPI Write Timing Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 13 SDODZ DATA FROM FIRST READ COMMAND Bit 23 Bit 1 Bit 0 FSDO = 1 SDODLY DATA FROM FIRST READ COMMAND Figure 6-3. SPI Read Timing Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 14 3616 4064 Code Code Internal reference, gain = 4x Figure 6-8. Voltage Output DNL vs Digital Input Code Figure 6-9. Voltage Output DNL vs Digital Input Code Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 15 Temperature (C) Supply Voltage (V) DAC channels at midscale DAC channels at midscale Figure 6-14. Voltage Output TUE vs Temperature Figure 6-15. Voltage Output TUE vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 16 LDAC (1 V/div) (1 LSB/div) (1 LSB/div) Time (s) Time (s) Figure 6-20. Voltage Output Code-to-Code Glitch - Rising Edge Figure 6-21. Voltage Output Code-to-Code Glitch - Falling Edge Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 17 10 2030 50 100 200 500 1000 10000 100000 Frequency (Hz) Frequency (Hz) Internal reference, gain = 4x Figure 6-26. Voltage Output Noise Density Figure 6-27. Voltage Output Noise Density Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 18 Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz f = 0.1 Hz to 10 Hz Figure 6-28. Voltage Output Flicker Noise Figure 6-29. Voltage Output Flicker Noise Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 19: Typical Characteristics: Current Output

    CH0 MIN 110 125 2.725 3.65 4.575 Temperature (C) Supply Voltage (V) Figure 6-34. Current Output DNL vs Temperature Figure 6-35. Current Output DNL vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 20 CH0, DAC Code = 255 Channel 0 -1000 -1.5 110 125 Load Voltage (V) Temperature (C) Figure 6-41. Current Output vs Load Voltage Figure 6-40. Current Output Gain Error vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 21 500 1000 10000 100000 Frequency (Hz) Time (s) f = 0.1 Hz to 10 Hz Figure 6-46. Current Output Noise Density Figure 6-47. Current Output Flicker Noise Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 22 = 5.5 V, output range: ±250 μA (unless otherwise noted) 20 30 50 100 200 500 1000 2000 10000 30000 30000 Frequency (Hz) Figure 6-48. Current Output AC PSRR vs Frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 23: Typical Characteristics: Comparator

    Figure 6-49. Comparator Response Time: Figure 6-50. Comparator Response Time: Low‑to‑High Transition High‑to‑Low Transition Channel 1 Channel 0 110 125 Temperature (C) Figure 6-51. Comparator Offset Error vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 24: Typical Characteristics: General

    Temperature (C) External Capacitance on CAP Pin (F) Sleep mode, internal reference disabled Figure 6-54. Power-Down Current vs Temperature Figure 6-55. Boot-Up Time vs Capacitance on CAP pin Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 25: Overview

    NVM. These features enable the DAC63202W to go beyond the limitations of a conventional DAC that depends on a processor to function. As a result of processor-less operation and the smart feature set, the DAC63202W is called a smart DAC.
  • Page 26 SLASF73 – APRIL 2023 7.3 Feature Description 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture The DAC63202W devices consist of a string architecture with a voltage-output amplifier, as well as an external FB pin and voltage-to-current converter for each channel. Section 7.2 shows the DAC architecture within the block diagram that operates from a 1.8-V to 5.5-V power supply.
  • Page 27: Device Functional Modes

    Figure 7-2. Voltage Reference Selection and Power-Down Logic 7.4.1.1.1 Internal Reference The DAC63202W contains an internal reference that is disabled by default. To enable the internal reference, write 1 to bit EN-INT-REF in the COMMON-CONFIG register. The internal reference generates a fixed 1.21-V voltage (typical).
  • Page 28 SLASF73 – APRIL 2023 7.4.1.1.2 External Reference By default, the DAC63202W operates from an external reference input. The external reference option can also be selected by configuring the VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register appropriately. Write 1 to the DIS-MODE-IN bit in the DEVICE-MODE-CONFIG register to minimize I .
  • Page 29 (0 V to V /3 or 0 V to V (0 V to V /3 or 0 V to V AGND 10 k Figure 7-3. Comparator Interface Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 30 Normal comparator mode. No hysteresis or window operation. Hysteresis comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the hysteresis. Window comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the window bounds. Invalid setting Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 31 CMP-X-INV-EN = 0 RST-CMP-FLAG-X Figure 7-6. Latching Comparator With Active Low Output DAC-X-MARGIN-HIGH (FULL-CODE) FBx/AINx DAC-X-MARGIN-LOW OUT-X CMP-X-INV-EN = 0 RST-CMP-FLAG-X Figure 7-7. Latching Comparator With Active High Output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 32 CONFIG register to get the best response time from the window comparator. • The CMP-X-OUT-EN bit in the DAC-X-VOUT-CMP-CONFIG register can be set to 0b to eliminate undesired toggling of the OUT pin. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 33 SLASF73 – APRIL 2023 7.4.4 Fault-Dump Mode The DAC63202W provides a feature to save a few registers into the NVM when the FAULT-DUMP bit is triggered or when the GPIO mapped to fault-dump is triggered (see also Table 7-18). This feature is useful in system-level fault management to capture the state of the device or system just before a fault is triggered, and to allow diagnosis after the fault has occurred.
  • Page 34 This section provides the details of application-specific functional modes available in the DAC63202W. 7.4.5.1 Voltage Margining and Scaling Voltage margining or scaling is a primary application for the DAC63202W. This section provides specific features available for this application such as Hi-Z output, slew-rate control, PROTECT input, and PMBus compatibility.
  • Page 35 MARGIN_HIGH is the decimal value of the DAC-X-MAGIN-HIGH bits in the DAC-X-MARGIN-HIGH register. • MARGIN_LOW is the decimal value of the DAC-X-MAGIN-LOW bits in the DAC-X-MARGIN-LOW register. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 36 12 µs 18 µs 27 µs 40.5 µs 60.75 µs DAC-X-FUNC-CONFIG 91.13 µs 136.69 µs 239.2 µs 418.61 µs 732.56 µs 1281.98 µs 2563.96 µs 5127.92 µs Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 37 The PMBus protocol is an I C-based communication standard for power-supply management. PMBus contains standard command codes tailored to power supply applications. The DAC63202W implement some PMBus commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well as PMBUS revision.
  • Page 38 Margin low Margin high The DAC63202W also implement PMBus features such as group command protocol and communication timeout failure. The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is reset by writing 1.
  • Page 39 SLASF73 – APRIL 2023 7.4.5.2 Function Generation The DAC63202W implement a continuous function or waveform generation feature. These devices can generate a triangular wave, sawtooth wave, and sine wave independently for every channel. 7.4.5.2.1 Triangular Waveform Generation Figure 7-12 shows that the triangular waveform uses the DAC-X-MARGIN-LOW (FUNCTION-MIN) and DAC- X-MARGIN-HIGH (FUNCTION-MAX) registers for minimum and maximum levels, respectively.
  • Page 40 FUNCTION_MAX is the decimal value of the DAC-X-MAGIN-HIGH bits in the DAC-X-MARGIN-HIGH register. • FUNCTION_MIN is the decimal value of the DAC-X-MAGIN-LOW bits in the DAC-X-MARGIN-LOW register. FUNCTION-MAX TIME-STEP CODE-STEP FUNCTION-MIN Figure 7-13. Sawtooth Waveform Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 41 6 (90° phase start) 0xE66 0x19A 0xE2F 0x1D1 8 (120° phase start) 0xD8B 0x275 0xC87 0x379 0xB33 0x4CD 0x9A8 0x658 TIME PERIOD Figure 7-14. Sine Wave Generation Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 42 POR (boot-up) delay. The default value for all the registers in the DAC63202W is loaded from NVM as soon as the POR event is issued.
  • Page 43 7.4.6.4 NVM Cyclic Redundancy Check (CRC) The DAC63202W implement a cyclic redundancy check (CRC) feature for the NVM to make sure that the data stored in the NVM is uncorrupted. There are two types of CRC alarm bits implemented in DAC63202W: •...
  • Page 44 DAC63202W www.ti.com SLASF73 – APRIL 2023 7.4.7 Power-Down Mode The DAC63202W output amplifier and internal reference can be independently powered down through the EN-INT-REF, VOUT-PDN-X, and IOUT-PDN-X bits in the COMMON-CONFIG register (see also Figure 7-2). At power up, the DAC output and the internal reference are disabled by default. In power-down mode, the DAC outputs (OUTx pins) are in a high-impedance state.
  • Page 45: Programming

    An SPI access cycle for DAC63202W is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for DAC63202W is 24 bits long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the SYNC pin is deasserted high.
  • Page 46 Device A command Device B command Device C command SDI-C D23 – D1 D23 – D1 SDO-C Device A command Device B command Figure 7-19. SPI Daisy-Chain Write Cycle Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 47 7.5.2 I C Programming Mode The DAC63202W devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0); see also the pin diagram in the Pin Configuration and Functions section. The I C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures.
  • Page 48 Stop Change of data condition condition Data line stable allowed Data valid Figure 7-21. Start and Stop Conditions Figure 7-22. Bit Transfer on the I C Bus Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 49 Figure 7-23. I C Bus Protocol The command byte sets the operating mode of the selected DAC63202W device. For a data update to occur when the operating mode is selected by this byte, the DAC63202W device must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB).
  • Page 50 A0 PIN AGND The DAC63202W supports broadcast addressing, which is used for synchronously updating or powering down multiple DAC63202W devices. When the broadcast address is used, the DAC63202W responds regardless of the address pin state. Broadcast is supported only in write mode.
  • Page 51 7.5.3 General-Purpose Input/Output (GPIO) Modes Together with I C and SPI, the DAC63202W also support a GPIO that can be configured in the NVM for multiple functions. This pin allows for updating the DAC output channels and reading status bits without using the programming interface, thus enabling processor-less operation.
  • Page 52 Table 7-19. General-Purpose Output (STATUS) Function Map REGISTER BIT FIELD VALUE FUNCTION 0001 NVM-BUSY 0100 DAC-1-BUSY 0111 DAC-0-BUSY GPIO-CONFIG GPO-CONFIG 1000 WIN-CMP-1 1011 WIN-CMP-0 Others Not applicable Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 53 PMBUS-CML Not applicable PMBUS-VERSION PMBUS-VERSON Not applicable The highlighted gray cells indicate the register bits or fields that are stored in the NVM. X = Don't care. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC63202W...
  • Page 54 All pages PMBUS-PAGE Section 7.6.20 PMBIS-OP-CMD-0 Section 7.6.21 PMBUS-OP-CMD-1 Section 7.6.21 PMBUS-OP-CMD-2 Section 7.6.21 PMBUS-OP-CMD-3 Section 7.6.21 All pages PMBUS-CML Section 7.6.22 All pages PMBUS-VERSION Section 7.6.23 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 55 Table 7-22. Access Type Codes Access Type Code Description Don't care Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC63202W...
  • Page 56 Data are in straight-binary format. MSB left aligned. Use the following bit alignment: VOUT: {DAC-X-MARGIN-LOW[11:0] IOUT: {DAC-X-MARGIN-LOW[7:0], X, X, X, X} X = Don't care bits. Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 57 0: Don't invert the comparator output 1: Invert the comparator output CMP-X-EN 0: Disable comparator mode 1: Enable comparator mode. Current-output must be in power- down. Voltage-output mode must be enabled. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 58 00: No hysteresis or window function 01: Hysteresis provided using DAC-X-MARGIN-HIGH and DAC- X-MARGIN-LOW registers 10: Window comparator mode with DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers setting window bounds 11: Invalid 000h Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 59 0111: 60.72 µs/step 1000: 91.12 µs/step 1001: 136.72 µs/step 1010: 239.2 µs/step 1011: 418.64 µs/step 1100: 732.56 µs/step 1101: 1282 µs/step 1110: 2563.96 µs/step 1111: 5127.92 µs/step Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 60 DAC-X-MARGIN-LOW): 000: 4 µs/step 001: 12 µs/step 010: 27.04 µs/step 011: 60.72 µs/step 100: 136.72 µs/step 101: 418.64 µs/step 110: 1282 µs/step 111: 5127.92 µs/step Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 61 01: Power-down VOUT-X with 10 kΩ to AGND 10: Power-down VOUT-X with 100 kΩ to AGND 11: Power-down VOUT-X with Hi-Z to AGND 9, 0 IOUT-PDN-X 0: Power-up IOUT-X 1: Power-down IOUT-X Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 62 0: NVM write not triggered 1: NVM write triggered. This bit self-resets. NVM-RELOAD 0: NVM reload not triggered 1: Reload data from NVM to register map. This bit self-resets. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 63 1: Trigger margin-high command. This bit self-resets. 12, 0 START-FUNC-X 0: Stop function generation 1: Start function generation as per FUNC-GEN-CONFIG-X in the DAC-X-FUNC-CONFIG register. 11-4 Don't care Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 64 1: DAC-0 channel does not accept commands 11-10 Don't care DAC-1-BUSY 0: DAC-1 channel can accept commands 1: DAC-1 channel does not accept commands Don't care DEVICE-ID Device identifier. VERSION-ID Version identifier. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 65 Two bits correspond to two DAC channels. 0b is disabled and 1b is enabled. GPI-CH-SEL[0]: Channel 1 GPI-CH-SEL[3]: Channel 0 Example: when GPI-CH-SEL is 1001, both channel 0 and channel 1 are enabled. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 66 DEV-UNLOCK field through I or SPI and to the RESET field through I Others: Invalid GPI-EN 0: Disable input mode for GPIO pin. 1: Enable input mode for GPIO pin. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 67 0: PMBus disabled 1: Enable PMBus Don't care FSDO-EN 0: Fast SDO disabled 1: Fast SDO enabled Don't care SDO-EN 0: SDO disabled 1: SDO enabled on GPIO pin Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 68 IOUT: {BROADCAST-DATA[7:0], X, X, X, X} X = Don't care bits. The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register must be enabled for the respective channels. Don't care. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 69 1: PMBus communication fault for write with incorrect number of clocks, read before write command, invalid command address, and invalid or unsupported data value; reset this bit by writing 1. Don't care Not applicable Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 70 PMBus page address = X, PMBus register address =98h Figure 7-46. PMBUS-VERSION Register PMBUS-VERSION R-22h X-00h Table 7-47. PMBUS-VERSION Register Field Descriptions Field Type Reset Description 15-8 PMBUS-VERSION PMBus version Not applicable Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 71: Application And Implementation

    DAC is the best choice for controlling the power-supply output linearly. Figure 8-1 shows a control circuit for a switch-mode power supply (SMPS) using the DAC63202W. Typical applications of power-supply margining are communications equipment, enterprise servers, test and measurement, and general-purpose power-supply modules.
  • Page 72 100 µA 8.2.2 Detailed Design Procedure The DAC63202W features a Hi-Z power-down mode that is set by default at power-up, unless the device is programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R is zero and the SMPS is set at the nominal output voltage of 3.3 V.
  • Page 73: Power Supply Recommendations

    8.4 Layout 8.4.1 Layout Guidelines The DAC63202W pin configuration separates the analog, digital, and power pins for an optimized layout. For signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins. Submit Document Feedback Copyright ©...
  • Page 74 LDO Bypass Capacitor DAC63202W SDA/SCLK OUT1 Figure 8-4. Layout Example Note: The ground and power planes have been omitted for clarity. Connect the thermal pad to ground. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC63202W...
  • Page 75: Glossary

    All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 76 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) DAC63202YBHR ACTIVE DSBGA 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Samples...
  • Page 77 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2023 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS B0 W Reel Diameter Cavity Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE...
  • Page 78 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) DAC63202YBHR DSBGA 3000 182.0 182.0 20.0 Pack Materials-Page 2...
  • Page 79 PACKAGE OUTLINE YBH0016 DSBGA - 0.4 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY BALL A1 CORNER 0.4 MAX SEATING PLANE BALL TYP 0.05 C 0.16 0.10 1.2 TYP SYMM SYMM D: Max = 1.748 mm, Min = 1.687 mm E: Max = 1.748 mm, Min =...
  • Page 80 OPENING SOLDER MASK NON-SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4225022/A 06/2019 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com...
  • Page 81 EXAMPLE STENCIL DESIGN YBH0016 DSBGA - 0.4 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 16X ( 0.21) (0.4) TYP SYMM METAL SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 40X 4225022/A 06/2019 NOTES: (continued) 4.
  • Page 82 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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