Texas Instruments DAC 300 Series Manual

Texas Instruments DAC 300 Series Manual

12-bit and 10-bit ultra-low power dual and single voltage and current output smart dacs with auto-detected i2c, pmbus, or spi interface

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DACx300x 12-Bit and 10-Bit Ultra-Low Power Dual and Single Voltage and Current
Output Smart DACs With Auto-Detected I
1 Features
Programmable voltage or current outputs with
flexible configuration:
– Voltage outputs:
1 LSB INL and DNL (10-bit)
Gains of 1x, 1.5x, 2x, 3x, and 4x
– Current outputs:
1 LSB INL and DNL (8-bit)
Unipolar and bipolar output range options
from 25 μA to 250 μA
35-μA/channel I
in voltage-output mode
DD
Programmable comparator mode for all channels
High-impedance output when VDD is off
High-impedance and resistive pulldown power-
down modes
50-MHz SPI-compatible interface
Automatically detected I
interface
– 1.62-V V
with V
IH
DD
General-purpose input/output (GPIO) configurable
as multiple functions
Predefined waveform generation: sine, cosine,
triangular, sawtooth
User-programmable nonvolatile memory (NVM)
Internal, external, or power-supply as reference
Wide operating range:
– Power supply: 1.8 V to 5.5 V
– Temperature: –40˚C to +125˚C
Tiny package: 16-pin WQFN (3 mm × 3 mm)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
2
C, PMBus
, or SPI
= 5.5 V
CAP
LDO
INT
REF
NVM
A0/SDI
SCL/SYNC
DAC
SDA/SCLK
Register
GPIO/SDO
Function
AGND
Simplified Block Diagram
DAC53001, DAC53002, DAC63001, DAC63002
2
C, PMBus™, or SPI Interface
2 Applications
Land mobile radio
Pulse oximeter
Optical module
Standard notebook PC
3 Description
The 12-bit DAC63001 and DAC63002, and the 10‑bit
DAC53001 and DAC53002 (collectively referred to as
the DACx300x) are a pin-compatible family of ultra-
low-power, single-channel and dual-channel, buffered
voltage-output and current-output smart digital-to-
analog converters (DACs). The DACx300x devices
support Hi-Z power-down mode and Hi-Z output
during power-off conditions. The DAC outputs provide
a force-sense option for use as a programmable
comparator and current sink. The multifunction GPIO,
function generation, and NVM enable these smart
DACs for processor-less applications and design
reuse. These devices automatically detect I
PMBus, and SPI interfaces and contain an internal
reference.
The feature set combined with the tiny package and
ultra-low power make these smart DACs an excellent
choice for applications such as land mobile radios,
pulse oximeters, notebook PCs, and other battery-
operated applications for biasing, calibration, and
waveform generation.
Device Information
PART NUMBER
PACKAGE
DACx3001
WQFN (16)
DACx3002
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VREF
VDD
MUX
DAC
+
BUF
-
R2
R1
Channel 0
Channel 1
SLASF48 – MAY 2022
(1)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
OUT0-1
FB0-1
2
C,

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Summary of Contents for Texas Instruments DAC 300 Series

  • Page 1 DAC53001, DAC53002, DAC63001, DAC63002 SLASF48 – MAY 2022 DACx300x 12-Bit and 10-Bit Ultra-Low Power Dual and Single Voltage and Current Output Smart DACs With Auto-Detected I C, PMBus™, or SPI Interface 1 Features 2 Applications • Programmable voltage or current outputs with •...
  • Page 2: Table Of Contents

    4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2022 Initial Release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 3: Description

    Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case an external reference is used, make sure the reference ramps up after VDD. Thermal Thermal Pad Ground Connect the thermal pad to AGND. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 4: Absolute Maximum Ratings

    Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 5 , gain = 3x or 4x Power supply rejection ratio (dc) Internal V , gain = 2x, DAC at midscale, V = 5 V ±10% 0.25 mV/V Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 6: Electrical Characteristics: Voltage

    When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show parametric drift. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 7 = 5.5 V, ±250-µA output range ±250-µA output range, 200-mV 50-Hz or 60-Hz sine Power supply rejection ratio wave superimposed on power-supply voltage, DAC at 0.65 LSB/V (ac) midscale Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 8 DAC output is 25 pF Specified by design and characterization, not production tested. This specification does not include the total unadjusted error (TUE) of the DAC. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 9 Specified by design and characterization, not production tested. Measured at –40°C and +125°C and calculated the slope. Impedances for the DAC channels are connected in parallel. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 10 HIGH Clock and data fall time Clock and data rise time Data valid time 0.45 µs VD_DAT Data valid acknowledge time 0.45 µs VD_ACK Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 11 SCLK falling edge to SYNC rising edge SYNC hight time µs CSHIGH SCLK rising edge to SDO falling edge, I ≤ 5 mA, C = 20 pF. SDODLY Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 12 C Timing Diagram CSHIGH SYNC SCLKLOW SCLK SCLKHIGH SDIS SDIH Bit 23 Bit 1 Bit 0 GPIO/ LDAC CS2LDAC LDACW Figure 6-2. SPI Write Timing Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 13 DATA FROM FIRST READ COMMAND Bit 23 Bit 1 Bit 0 FSDO = 1 SDODLY DATA FROM FIRST READ COMMAND Figure 6-3. SPI Read Timing Diagram Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 14 Code Internal reference, gain = 4x Figure 6-8. Voltage Output DNL vs Digital Input Code Figure 6-9. Voltage Output DNL vs Digital Input Code Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 15 Supply Voltage (V) DAC channels at midscale DAC channels at midscale Figure 6-14. Voltage Output TUE vs Temperature Figure 6-15. Voltage Output TUE vs Supply Voltage Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 16 (1 LSB/div) Time (s) Time (s) Figure 6-20. Voltage Output Code-to-Code Glitch - Rising Edge Figure 6-21. Voltage Output Code-to-Code Glitch - Falling Edge Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 17 500 1000 10000 100000 Frequency (Hz) Frequency (Hz) Internal reference, gain = 4x Figure 6-26. Voltage Output Noise Density Figure 6-27. Voltage Output Noise Density Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 18 Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz f = 0.1 Hz to 10 Hz Figure 6-28. Voltage Output Flicker Noise Figure 6-29. Voltage Output Flicker Noise Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 19: Typical Characteristics: Current Output

    2.725 3.65 4.575 Code Supply Voltage (V) Figure 6-35. Current Output DNL vs Digital Input Code Figure 6-34. Current Output INL vs Supply Voltage Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 20 Output range: 0 μA to 250 μA Figure 6-40. Current Output TUE vs Digital Input Code Figure 6-41. Current Output TUE vs Digital Input Code Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 21 -1000 -1.5 110 125 Load Voltage (V) Temperature (C) Figure 6-47. Current Output vs Load Voltage Figure 6-46. Current Output Gain Error vs Temperature Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 22 100000 Frequency (Hz) Frequency (Hz) Output range: 0 μA to 250 μA Figure 6-52. Current Output Noise Density Figure 6-53. Current Output Noise Density Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 23 Figure 6-54. Current Output Flicker Noise 20 30 50 100 200 500 1000 2000 10000 30000 30000 Frequency (Hz) Figure 6-56. Current Output AC PSRR vs Frequency Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 24: Typical Characteristics: Comparator

    Figure 6-58. Comparator Response Time: Low‑to‑High Transition High‑to‑Low Transition Channel 1 Channel 0 110 125 Temperature (C) Figure 6-59. Comparator Offset Error vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 25: Typical Characteristics: General

    Figure 6-63. Power-Down Current vs Temperature Figure 6-62. Power-Down Current vs Temperature 12.5 External Capacitance on CAP Pin (F) Figure 6-64. Boot-Up Time vs Capacitance on CAP pin Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 26: Detailed Description

    GPIO/SDO Buffer Register FB0-1 Power On Reset Output Function Generation Power Down Logic Configuration Channel 0 Channel 1 AGND Figure 7-1. Functional Block Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 27: Feature Description

    FAULT-DUMP, and RESET. All the digital pins are open-drain when used as outputs. Therefore, all the output pins must be pulled up to the desired IO voltage using external resistors. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 28 When an external reference is used, the current is calculated mainly as the current sourced from the external reference, which is equal to the reference voltage divided by the input impedance of the VREF pin. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 29: Device Functional

    – 1. • is the internal reference voltage = 1.21 V (typical). • GAIN = 1.5x, 2x, 3x, or 4x, based on VOUT-X-GAIN bits. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 30 IOUT-RANGE-X setting specified in Section 7.6.5. • is the signed minimum current in the IOUT-RANGE-X setting specified in Section 7.6.5. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 31 (0 V to V /3 or 0 V to V (0 V to V /3 or 0 V to V AGND 10 k Figure 7-3. Comparator Interface Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 32 Normal comparator mode. No hysteresis or window operation. Hysteresis comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the hysteresis. Window comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the window bounds. Invalid setting Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 33 Figure 7-6. Latching Comparator With Active Low Output DAC-X-MARGIN-HIGH (FULL-CODE) FBx/AINx DAC-X-MARGIN-LOW OUT-X CMP-X-INV-EN = 0 RST-CMP-FLAG-X Figure 7-7. Latching Comparator With Active High Output Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 34 CONFIG register to get the best response time from the window comparator. • The CMP-X-OUT-EN bit in the DAC-X-VOUT-CMP-CONFIG register can be set to 0b to eliminate undesired toggling of the OUT pin. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 35 Read the data from the SRAM-DATA register again to get the MSB bits. 4. Set the EE-READ-ADDR bit to 1b in the COMMON-CONFIG register, to select row2 of the NVM. Repeat steps 2 and 3. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 36 Switch to DAC code stored in NVM (no slew) and then switch to Hi-Z power-down. Slew to margin-low code and then switch to Hi-Z power-down. Slew to margin-high code and then switch to Hi-Z power-down. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 37 CODE_STEP is the CODE-STEP-X setting specified in Table 7-5. • MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in Section 7.6.2. • MARGIN_LOW is the DAC-X-MAGIN-LOW specified in Section 7.6.3. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 38 18 µs 27 µs 40.5 µs 60.75 µs DAC-X-FUNC-CONFIG 91.13 µs 136.69 µs 239.2 µs 418.61 µs 732.56 µs 1281.98 µs 2563.96 µs 5127.92 µs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 39 PMBus-compatible device #2 ALERT Control signal CONTROL Data DATA Clock CLOCK Optional Required PMBus-compatible device #3 ALERT CONTROL DATA CLOCK Figure 7-11. PMBus Connections Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 40 The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is reset by writing 1. To get the PMBus version, read the PMBUS-VERSION register. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 41 CODE_STEP is the CODE-STEP-X setting specified in Table 7-5. • MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in Section 7.6.2. • MARGIN_LOW is the DAC-X-MAGIN-LOW specified in Section 7.6.3. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 42 0x379 0xD8B 0x275 0xE2F 0x1D1 0xE66 0x19A 0xE2F 0x1D1 0xD8B 0x275 0xC87 0x379 0xB33 0x4CD 0x9A8 0x658 TIME PERIOD Figure 7-12. Sine Wave Generation Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 43 1. However, the software reset function through the COMMON-TRIGGER register is not blocked when using the I C interface. To bypass the DEV-LOCK setting, write 0101 to the DEV-UNLOCK bits in the COMMON-TRIGGER register. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 44 In case of a temporary failure, to reset the alarm bits to 0, issue a software reset command (see also Section 7.4.6.2) or cycle power to the DAC. A permanent failure in the NVM makes the device unusable. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 45 7. To bring the device out of the deep-sleep mode, pull the GPIO pin high. The digital circuitry and the LDO take approximately 550 μs to switch on. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 46: Programming

    Echo R/W from previous access cycle 22-16 A[6:0] Echo register address from previous access cycle 15-0 DI[15:0] Readback data requested on previous access cycle Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 47 Device B command Device C command SDI-C D23 – D1 D23 – D1 SDO-C Device A command Device B command Figure 7-17. SPI Daisy-Chain Write Cycle Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 48 Data output by receiver Acknowledge SCL from controller Clock pulse for acknowledgement Start condition Figure 7-18. Acknowledge and Not Acknowledge on the I C Bus Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 49 Change of data Data line stable allowed Data valid Figure 7-19. Start and Stop Conditions Figure 7-20. Bit Transfer on the I C Bus Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 50 (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received, the DACx300x device releases the I C bus and awaits a new start condition. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 51 DACx300x devices. When the broadcast address is used, the DACx300x responds regardless of the address pin state. Broadcast is supported only in write mode. 7.5.2.2.2 Command Byte Table 7-21 lists the command byte in the ADDRESS column. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 52 Pull the GPIO pin high or low when not used. When the GPIO pin is used as RESET, the configuration must be programmed into the NVM. Otherwise, the setting is cleared after the device resets. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 53 Table 7-19. General-Purpose Output (STATUS) Function Map REGISTER BIT FIELD VALUE FUNCTION 0001 NVM-BUSY 0100 DAC-1-BUSY 0111 DAC-0-BUSY GPIO-CONFIG GPO-CONFIG 1000 WIN-CMP-1 1011 WIN-CMP-0 Others Not applicable Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 54: Register Map

    PMBUS-VERSION PMBUS-VERSON Not applicable The highlighted gray cells indicate the register bits or fields that are stored in the NVM. X = Don't care. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 55 Section 7.6.20 PMBIS-OP-CMD-0 Section 7.6.21 PMBUS-OP-CMD-1 Section 7.6.21 PMBUS-OP-CMD-2 Section 7.6.21 PMBUS-OP-CMD-3 Section 7.6.21 All pages PMBUS-CML Section 7.6.22 All pages PMBUS-VERSION Section 7.6.23 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 56 Table 7-22. Access Type Codes Access Type Code Description Don't care Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 57 Use the following bit alignment: DAC63001: {DAC-X-MARGIN-HIGH[11:0]} DAC63002: {DAC-X-MARGIN-HIGH[11:0]} DAC53001: {DAC-X-MARGIN-HIGH[9:0], X, X} DAC53002: {DAC-X-MARGIN-HIGH[9:0], X, X} X = Don't care bits. Don't care Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 58 1: Invert the comparator output CMP-X-EN 0: Disable comparator mode 1: Enable comparator mode. Current-output must be in power- down. Voltage-output mode must be enabled. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 59 01: Hysteresis provided using DAC-X-MARGIN-HIGH and DAC- X-MARGIN-LOW registers 10: Window comparator mode with DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers setting window bounds 11: Invalid 000h Don't care Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 60 1000: 91.12 µs/step 1001: 136.72 µs/step 1010: 239.2 µs/step 1011: 418.64 µs/step 1100: 732.56 µs/step 1101: 1282 µs/step 1110: 2563.96 µs/step 1111: 5127.92 µs/step Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 61 000: 4 µs/step 001: 12 µs/step 010: 27.04 µs/step 011: 60.72 µs/step 100: 136.72 µs/step 101: 418.64 µs/step 110: 1282 µs/step 111: 5127.92 µs/step Don't care Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 62 10: Power-down VOUT-X with 100 kΩ to AGND 11: Power-down VOUT-X with Hi-Z to AGND 9, 0 IOUT-PDN-X 0: Power-up IOUT-X 1: Power-down IOUT-X Don't care Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 63 1: NVM write triggered. This bit self-resets. NVM-RELOAD 0: NVM reload not triggered 1: Reload data from NVM to register map. This bit self-resets. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 64 1: Trigger margin-high command. This bit self-resets. 12, 0 START-FUNC-X 0: Stop function generation 1: Start function generation as per FUNC-GEN-CONFIG-X in the DAC-X-FUNC-CONFIG register. 11-4 Don't care Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 65 0: DAC-1 channel can accept commands 1: DAC-1 channel does not accept commands Don't care DEVICE-ID DAC63002: 08h Device identifier DAC63001: 09h DAC53002: 0Ah DAC53001: 0Bh VERSION-ID Version identifier Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 66 Two bits correspond to two DAC channels. 0b is disabled and 1b is enabled. GPI-CH-SEL[0]: Channel 1 GPI-CH-SEL[3]: Channel 0 Example: when GPI-CH-SEL is 1001, both channel-0 and channel-1 are enabled. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 67 SPI and to the RESET field through I Others: Invalid GPI-EN 0: Disable input mode for GPIO pin. 1: Enable input mode for GPIO pin. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 68 1: Enable PMBus Don't care FSDO-EN 0: Fast SDO disabled 1: Fast SDO enabled Don't care SDO-EN 0: SDO disabled 1: SDO enabled on GPIO pin Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 69 DAC53002: {DAC-X-MARGIN-HIGH[9:0], X, X} X = Don't care bits. The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register must be enabled for the respective channels. Don't care. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 70 1. Don't care Not applicable Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 71 PMBus page address = X, PMBus register address =98h Figure 7-44. PMBUS-VERSION Register PMBUS-VERSION R-22h X-00h Table 7-47. PMBUS-VERSION Register Field Descriptions Field Type Reset Description 15-8 PMBUS-VERSION PMBus version Not applicable Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 72: Application And Implementation

    SMPS / LDO SDA/SCLK VOUT/ SENSE IOUT A0/SDI VOUT/ PROTECT IOUT Output Configuration Power-supply: 0 Logic DACx300x Power-supply: 1 AGND Figure 8-1. Voltage Margining and Scaling Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 73 The DAC-X-MARGIN-HIGH register value in DACx300x results in the margin-low value at the power supply output. Similarly, the DAC-X-MARGIN-LOW register value in DACx300x results in the margin- high value at the power-supply output. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 74 WRITE DAC-0-MARGIN-LOW(0x14), 0x05, 0x00 //Save settings to NVM WRITE COMMON-TRIGGER(0x20), 0x00, 0x02 8.2.3 Application Curves Figure 8-3. Power-Supply Margin Low Figure 8-2. Power-Supply Margin High Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 75: Power Supply Recommendations

    DACx3001 OUT0 OUT1 Figure 10-1. Layout Example Note: The ground and power planes have been omitted for clarity. Connect the thermal pad to ground. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002...
  • Page 76 All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 77 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2022 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) DAC53002RTER ACTIVE WQFN 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 D53002...
  • Page 78 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2022 Addendum-Page 2...
  • Page 79 GENERIC PACKAGE VIEW RTE 16 WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 3 x 3, 0.5 mm pitch This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225944/A www.ti.com...
  • Page 80 PACKAGE OUTLINE RTE0016C WQFN - 0.8 mm max height SCALE 3.600 PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.8 MAX SEATING PLANE 0.05 0.08 0.00 1.68 0.07 (DIM A) TYP EXPOSED THERMAL PAD...
  • Page 81 4219117/B 04/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 82 EXAMPLE STENCIL DESIGN RTE0016C WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.55) 16X (0.6) 16X (0.24) SYMM (2.8) 12X (0.5) METAL ALL AROUND SYMM (R0.05) TYP (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X...
  • Page 83 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...

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