Quick Reference - Supermicro SuperServer SYS-611C-TN4R User Manual

Quick Reference

Jumper Description
JBT1 CMOS Clear
JRU1 Front Power Signal/Front UID Select
Connector
Battery (BT1)
COM1 (JCOM1)
FAN1-6
IPMI_LAN (JUSBRJ45)
JF1
JFP1
JIPMB1
JL1
JNCSI1
JPWR1/JPWR2
JPWR3
JRK1 (VROC RAID Key)
JSTBY1
JTPM1
JUIDB1
M.2-C1/M.2-C2 (JM2_1/JM2_2) M.2 slots for NVMe use only (with support of M-Key 2280)
MH10/MH11
P1-AIOM PCIe 5.0 x16
(JAIOM1)
P2-AIOM PCIe 5.0 x16
(JAIOM2)
P1_PE2 0-15 (JLUIO1/JLUIO2)
P2_PE2 0-15 (JRUIO1/
JRUIO2)
P1_PE1 0-7 (JPCIE1)
P1_PE1 8-15(JPCIE2)
P2_PE3 7-0 (JPCIE3)
P2_PE3 15-8 (JPCIE4)
P1_PE4 0-3 (JNVME1)
P1_PE4 4-7 (JNVME2)
P1_PE4 8-11 (JNVME3)
P1_PE4 12-15 (JNVME4)
P2_PE5 0-3 (JNVME5)
P2_PE5 4-7 (JNVME6)
P2_PE5 8-11 (JNVME7)
P2_PE5 12-15 (JNVME8)
PWR I2C (JPI2C1)
Description
Onboard battery
COM Port 1 on the rear IO panel
4-pin cooling fan headers (FAN1 - FAN 6)
BMC LAN connector on the rear I/O panel
Front Control Panel header
Front Control Panel header (not used in this system)
4-pin BMC SMbus header
Chassis Intrusion header
NC-SI (Network Controller Sideband Interface) connector (See the note below)
8-pin power connectors
24-pin power connector
Intel VROC RAID key header for NVMe RAID support
5V Standby power header
Trusted Platform Module/Port 80 connector
Unit Identifier (UID) switch/button
Mounting holes for M.2 SSDs (MH10: for M.2-C1, MH11 for M.2-C2)
Supermicro Advanced Input/Output Module (AIOM) PCIe 5.0 x 16 rear I/O
connector supported by CPU1
Supermicro Advanced Input/Output Module (AIOM) PCIe 5.0 x 16 rear I/O
connector supported by CPU2
PCIe 5.0 x16 left add-on card slot supported by CPU1
PCIe 5.0 x16 right add-on card slot supported by CPU2
PCIe 5.0 x8 MCIO connector supported by CPU1
PCIe 5.0 x8 MCIO connector supported by CPU1
PCIe 5.0 x8 MCIO connector supported by CPU2
PCIe 5.0 x8 MCIO connector supported by CPU2
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU1
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU1
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU1
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU1
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU2
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU2
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU2
PCIe 5.0 x4 MCIO connector used for NVMe devices supported by CPU2
Power I²C SMBus (System Management Bus) header
16
Chapter 1: Introduction
Default Setting
Open (Normal)
Pins 2-3 (Front UID Use)