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EVGA Z370 Classified K User Manual page 18

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EVGA Z370 Classified K (134-KS-E379)
secondary video cards, such as the 2
card.
* Please see the description for Physical (length) vs Electrical (lanes) on Page 21.
14. PCIe Slot x16 (x4/x2 Electrical)
PCIe x16/(x4/x2) Electrical is pulled from the PCH, rather than the CPU. This
slot would be used for PhysX in a SLI setup (at x4 speed), or any other card
that will work on a single or x4 PCIe lane. If x4 is disabled in the BIOS, this
slot should be used for cards that will work on x1 or x2 slots.
Conflict: PCIe slot 6 (PE6) shares two PCIe lanes with SATA ports 4/5. If x4
speed is disabled in the BIOS, SATA ports 4/5 will become enabled and PE6
will run at x2 speeds.
* Please see the description for Physical (length) vs Electrical (lanes) on Page 21.
15. PCIe Slot x1
PCIe x1 is the smallest form-factor PCIe card slot. They are all one lane and
are used for low-bandwidth products.
16. RGB LED Controller Header
The RBG header is a 4 pin header that allows a software based control within
windows for RGB devices via ELEET-X. Please see Page 41 for control
specifics.
17. Power Button
This is an onboard power button, and may be used in place of, or in
conjunction with, a front panel power button wired to the board.
Benching systems, or test benches before final assembly, are best served by
using the onboard power because it removes the need to wire a Power/Reset
button or cross posts with a screwdriver, which is a semi-common practice.
This button provides a safer and easier option than jumpering the Power posts.
18. Reset Button
This is an onboard system reset button, and may be used in place of, or in
conjunction with, a front panel system reset button wired to the board.
Benching systems, or test benches before final assembly, are best served by
using the onboard power because it removes the need to wire a Power/Reset
button or cross posts with a screwdriver, which is a semi-common practice.
This button provides a safer and easier option than jumpering the Power posts.
card in an SLI
configuration, or a PhysX
nd
®
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