Layout - Wolfspeed SPEEDVAL KIT HALF-BRIDGE MOD-MB-HB-0900V-40A User Manual

6. LAYOUT

Best practice when designing power converters with SiC is to keep the gate drivers as close to the
MOSFETs as possible and minimize the parasitic inductance between the MOSFETs and DC bus
capacitors. This limits parasitic inductance in the power loop and gate loop, which is detrimental to
switching performance. The SpeedVal Kit platform features a novel card edge system that creates a
flexible modularity that does not sacrifice switching performance. The SpeedVal Kit platform's novel
card edge approach utilizes these features:
1. Thirty-three pins for each bus connection to the daughter card
2. Wide copper areas on top and bottom of daughter card to mimic a laminated bus structure with
small loop area
3. Four-layer design on the motherboard and power daughter
card allowing for interleaved bus connections to minimize
inductance
F 40: C
IGURE ROSS
PRD-06829 REV. 1, December 2022
© 2022 Wolfspeed, Inc. All rights reserved. Wolfspeed® and the Wolfstreak logo are registered trademarks and the
SpeedVal Kit™ and Wolfspeed logo is a trademark of Wolfspeed, Inc. Other trademarks, product and company names
are the property of their respective owners and do not imply specific product and/or vendor endorsement,
sponsorship or association.
Cross-section view
- V S
SECTIONAL IEW OF PEED
SpeedVal Kit™ Half-Bridge User Guide
at dashed line
V K ™ M C
AL IT AIN ONNECTOR AND
DC B C
US ONNECTIONS
42