Analog Devices ADM1063 Manual page 6

ADM1063
Parameter
Standard (Digital Output) Mode
(PDO1 to PDO10)
V
OH
V
OL
3
I
OL
3
I
SINK
R
PULL-UP
3
I (VPn)
SOURCE
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance
Programmable Pull-Down Current,
I
PULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
IH
Input Low Voltage, V
IL
3
Output Low Voltage, V
OL
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
Input Low Current, I
IL
SEQUENCING ENGINE TIMING
State Change Time
1
At least one of the VH, VP1 to VP4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3 Specification is not production tested, but is supported by characterization data at initial product release.
Min Typ Max
2.4
4.5
V − 0.3
PU
0 0.50
20
60
20
2
10
90 100 110
2.0
0.8
−1
1
5
20
2.0
0.8
0.4
400
4.7
4.7
4
4.7
4
1000
300
250
5
1
10
Rev. 0 | Page 6 of 36
Unit Test Conditions/Comments
V V (pull-up to VDDCAP or VPn) = 2.7 V, I
PU
V V to VPn = 6.0 V, I
PU
V V ≤ 2.7 V, I = 0.5 mA
PU OH
V I = 20 mA
OL
mA Maximum sink current per PDO pin
mA Maximum total sink for all PDO pins
kΩ Internal pull-up
mA Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
µA V = 14.4 V
PDO
kHz All on-chip time delays derived from this clock
V Maximum V = 5.5 V
IN
V Maximum V = 5.5 V
IN
µA V = 5.5 V
IN
µA V = 0
IN
pF
µA VDDCAP = 4.75, T
A
required
V
V
V I = −3.0 mA
OUT
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µA V = 0
IN
µs
= 0.5 mA
OH
= 0 mA
OH
= 25°C if known logic state is