Outputs; Supply Sequencing Through Configurable Output Drivers - Analog Devices ADM1063 Manual

ADM1063

OUTPUTS

SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1063 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is taken with the
PDOs based on the condition of the inputs of the ADM1063.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc-to-dc converters, which generate supplies locally on
a board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
•
Open-drain (allowing the user to connect an external
pull-up resistor)
•
Open-drain with weak pull-up to V
•
Push/pull to V
DD
•
Open-drain with weak pull-up to VPn
•
Push/pull to VPn
•
Strong pull-down to GND
•
Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only)
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
SE DATA
SMBus DATA
CLK DATA
DD
SEL VP1
CFG4 CFG5 CFG6
Figure 25. Programmable Driver Output
Rev. 0 | Page 16 of 36
external N-channel FET, which is used to isolate, for example, a
card-side voltage from a backplane supply (a PDO can sustain
greater than 10.5 V into a 1 µA load). The pull-down switches
can also be used to drive status LEDs directly.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOnCFG con-
figuration register (see the AN-698
The data sources are as follows:
•
Output from the SE.
•
Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
•
On-Chip Clock. A 100 kHz clock is generated on the
device. This clock can be made available on any of the
PDOs. It can be used, for example, to clock an external
device such as an LED.
By default, the PDOs are pulled to GND by a weak (20 kΩ) on-
chip, pull-down resistor. This is the case upon power-up until
the configuration is downloaded from EEPROM and the
programmed setup is latched. The outputs are actively pulled
low once a supply of 1 V or greater is on VPn or VH. The outputs
remain high impedance prior to 1 V appearing on VPn or VH.
This provides a known condition for the PDOs during power-
up. The internal pull-down can be overdriven with an external
pull-up of suitable value tied from the PDO pin to the required
pull-up voltage. The 20 kΩ resistor must be accounted for in
calculating a suitable value. For example, if PDOn must be pulled
up to 3.3 V and 5 V is available as an external supply, the pull-up
resistor value is given by
3.3 V = 5 V × 20 kΩ/(R
Therefore,
R = (100 kΩ − 66 kΩ)/3.3 = 10 kΩ
UP
VFET (PDO1 TO PDO6 ONLY)
V
DD
VP4
application note for details).
+ 20 kΩ)
UP
PDO