NXP Semiconductors P5040 User Manual

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Freescale Semiconductor

User Guide

P5040/P5020 Reference Design Board

User Guide

This document describes the functionality of the P5040

(quad-core)/P5021 (dual core) and P5020 (dual core)/P5010

(single core) processors as the reference design board (RDB)

for customers.

The P5040/P5020 reference board is a lead-free,

RoHS-compliant board that is also known as

P5040/P5020RDB.

Figure 1

both processors implemented in this reference board.

The processors currently supported and the orderable part

number for each kit are as follows:

P5040/P5021

P5040-RDB

P5020/P5010

P5020-RDB

Before you begin

This table lists useful documentation references.

Contact your local Freescale

field applications engineer to

access documents that are not

available on freescale.com.

shows the block diagram for

NOTE

Document Number: P5040RDBUG

Rev. 0, 05/2013

Contents

1. Before you begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4. Evaluation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7. Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 48

8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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Summary of Contents for NXP Semiconductors P5040

Page 1: Table Of Contents
P5040/P5020 Reference Design Board User Guide This document describes the functionality of the P5040 Contents 1. Before you begin ......1 (quad-core)/P5021 (dual core) and P5020 (dual core)/P5010 2.
Page 2: Features
SystemID format The SystemID Format for Power Architecture® Development Systems AN3638 The initial version of the Software Development Kit (version 1.3) is shipped with the P5040/P5020 reference design board. The customer should check for new patch releases, which generally are updated on Freescale.com two times a year.
Page 3 — Power is supplied to the reference board via a standard 1U 450W power supply — Power is supplied via +12 V pins, VCC_RTC=3.3 V, and VCC_5V_stby = 5 V on the COM Express connectors — 2.5-V power for RMII Ethernet PHY P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 4: Block Diagram
Block Diagram Block Diagram This figure depicts the general features and connectivity of the P5040/P5020 reference board. Figure 1. P5040/P5020 Reference Board Block Diagram P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 5: Evaluation Support
The P5040/P5020 reference board can also be used as reference for many features of the P5040/P5020. This table summarizes the processor hardware interfaces that can be evaluated by using the reference board.
Page 6 Power 1U power supply to P5040/P5020 connector VCC_12, VCC_5_STBY, VCC_RTC_BAT Reference Design Board Use In the absence of a special hardware or software configuration, the P5040/P5020 reference design board operates identically to a development/evaluation system. Embedded Use Section 6.1, “Configuration Options,”...
Page 7: Architecture
SW3 power-on button SW1 local reset FPGA programming header Figure 3. Difficult-to-Find Connections—P5040/P5020 reference board Top View Architecture Processor This table lists the major pin groupings of the P5040/P5020. Table 3. P5040/P5020 Pin Groupings Summary Signal Group Details Memory Controllers Section 5.1.1, “DDR”...
Page 8 Memory interface includes all necessary termination and IO power and is routed in order to achieve maximum performance on the memory bus. • As noted in the table below, P5040/P5020 has a dual DDR controller connected to dual DDR3 SODIMM slots. Table 4. DDR Features...
Page 9 Dual-phase controller for up to 20 A at a default at 1.35 v adjustable to 1.5 V output. • Supplies GVDD, VREF, and VTT for SODIMM DRAM DDR3 and P5040/P5020 DDR controller. P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 10 SerDes x20/x18 Interface The SerDes block on the P5040/P5020 provides high-speed serial communications interfaces for several internal devices. The SerDes block provides 20 or 18 serial lanes for the P5040 or P5020, respectively. They may be partitioned as shown in Table 5(a) or (b), respectively.
Page 11 Architecture Table 5. P5040/P5020 SerDes Lane Multiplexing Configurations on P5040/P5020 (continued) Bank Bank 1 Bank 2 Bank 3 A B C D — — Aurora Conn on SATA SATA SLOT 1 SLOT 2 SLOT 3 — — — — Port1...
Page 12 SD_TX/RX[4:7](p,n) x1 PCIe card TX/RX[4:7](p,n) x4 SGMII PHY Aurora Debug Aurora Conn Connector SD_TX/RX[8:9](p,n) TX/RX[1:0](p,n) REFCLK_SD1(p,n) 100 MHz Figure 6. P5040/P5020 SerDes Bank1 to Reference Board Cards/ Debug Connector Configuration P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 13 Ethernet Controller (EC) Interfaces The two TSEC—with twisted pair 10/100/1000-Base-T interface—are IEEE 802.3-compliant. Vitesse VSC8244 PHY supports four integrated PHYs though only two are in use. The P5040/P5020RDB only uses the RGMII protocol. This table shows the general organization of the ETH system.
Page 14 – ngPIXIS registers PX_BRDCFG1 and PX_BRDCFG2 PHY Reset VSC8244 • Input is driven by the P5040/P5020 HRESET signal via FPGA, and reset after PHY RESET each P5040/P5020 HRESET sequence. • Input can be driven by register PX_RST P5040/P5020RDB FPGA Bit 7.
Page 15 GTXCLK CLKBUF 125 MHz Figure 8. P5040/P5020 Ethernet Connections to the Reference Board This table summarizes the reference board EC connections and routing when the board is populated with a P5040 or P5020 processor. Table 7. P5040/P5020 Ethernet Port Locations on P5040/P5020...
Page 16 ™ 5.1.4 Support for IEEE Std 1588 Protocol The reference board supports the P5040/P5020 IEEE® 1588 precision time protocol (PTP) as shown in Figure 9. This facility works in tandem with an Ethernet controller to timestamp incoming packets. P5040/P5020 1588 TX >...
Page 17 Architecture Figure 10. Serial Interfaces 5.1.6 enhanced Serial Peripheral Interface (eSPI) The P5040/P5020 has an eSPI Master Controller used to communicate with various peripherals. • Two SPI FLASH support 24-bit address and SPI Modes 0, 3. • Use Chip Select 0 or 1 with S25FL129P0XNFI001 FLASH if CVDD=3.3 V.
Page 18 Secure Digital Host Controller (eSDHC) & embedded Multi Media Controller (eMMC) The P5040/P5020 processor has an eSDHC and an eMMC controller, which the P5040/P5020 connects to an SD media card slot. The I C3_SDA signal uses write protect (WP). The I C3_SCL signal uses card detect (CD).
Page 19 P5040/P5020 internal PHY. The 24MHz USB block reference clock provides additional control to the P5040/P5020 in conjunction with the USB power sequence. GPIO 4,6 control the VBUS Drive. GPIO 5,7 get Power Fault indications via the FPGA.
Page 20 The reference board does not incorporate any specific devices that make use of the external pin-controlled DMA controllers. The P5040/P5020 DMA ports are connected to test points on the reference board to allow external hardware control, as needed. P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 21 EM1 management bus mux control GPIO[4:7] Spares connected to test points 5.1.13 Control Group P5040/P5020 control group signals, for the most part, stop or restart execution. Figure 12 gives a connections overview and shows the POR flow while Table 12 outlines the POR sequence.
Page 22 • Legacy COP SRST is mapped to the P5040/P5020 HRESET. • P5040/P5020 HRST is a bi-directional open drain signal; it is not monitored by ngPIXIS FPGA. NOTE Reset configuration input signals are ONLY sampled at the negation of POR. Reset Configuration input pins—CFG_RCW_SRC[4...0], CFG_SVR[1...0], CFG_GPINPUT[15...0], CFG_ENG_USE[3...0],...
Page 23 Table 12. PORESET Sequence Step Sequence Stage Description PORESET: After Negation 1. P5040/P5020 begins the configuration process and starts loading reset configuration. 2. Host debugger controls PORESET processor signal (which sets a chosen configuration). Configuration Input Reset configuration inputs are sampled to determine the following: •...
Page 24 5.1.14 The reference design board uses three of the four I C buses on the P5040/P5020. • C1 is electrically isolated before P5040/P5020 power-up to allow external or FPGA I C masters to program Zilker power devices. • C2 and I C4 can function independently, or together with I C2 as the controller.
Page 25 For current/power measurements on P5040/P5020 VDD_CA. 0x45 INA220 Current/Power Monitor For current/power measurements on P5040/P5020 VDD_CB. 0x4C ADT7461A or equivalent: Processor For measuring P5040/P5020 Thermal Monitor temperature. 0x68 DS3232: RTC Used by software. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 26 I C Port For bus reset, monitoring, and master-only data collection. Map addresses do not include the position of a transmitted address LSB (R/W bit). Figure 13. I C Scheme P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 27 XAUI PHY management Because one set of buses must span across multiple devices on the reference board, multiplexers are used to route from the P5040/P5020 to each SGMII and RGMII PHYs while EMI2_MDIO bus is routed to XAUI PHY. See Section 7, “Programming...
Page 28 Architecture This figure shows the eLBC block diagram. Figure 14. eLBC Interface P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 29 TI device SN74ALVTH32373ZKER provides address latch while the On Semiconductor device MC74LCX16245DTG provides dual data transceivers. A transceiver latch enable (LE) input signal is driven by a P5040/P3041/P5020 LALE output signal. • When LE is taken low, transceiver Q outputs are latched at input-set levels.
Page 30 5.1.19 Temperature Anode and Cathode The P5040/P5020 has two pins, Temp_Anode and Temp_Cathode, connected to a thermal body diode on the die that allow direct temperature measurement. The pins are connected to an ADT7461 thermal monitor that allows direct die temperature readings with an accuracy of ±1 °C.
Page 31 Handles, in a transparent manner, the merging of COP header resets with onboard resets. LOCALBUS Local Bus Interface between processor and REGFILE. REGISTERS Register Files Multi-ported register file containing status and configuration data. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 32 It is critical that COP_ HRST input reset the entire system EXCEPT for the COP JTAG controller; for example, TRST must not be asserted. • If COP JTAG is not connected to P5040/P5020RDB, then it is critical that reset assert TRST. The COP core manages these modal operations. 5.2.3 LOCALBUS LOCALBUS is the interface between processor and REGFILE;...
Page 33 The 12-V, 5-V, and 3.3-V power requirements for the reference board are met by the attached 1U-12V compatible power supply unit (PSU) of the P5040/P5020RDB. The 5 V and 3.3 V are connected to individual power planes in the P5040/P5020RDB PCB stackup. The 12-V power from the standard 1U header is treated as separate from the 1U-12V power, which supplies a large amount of current and is referred to as VCC_12V_BULK.
Page 34 5.3.1 Power Supplies An 1U power supply SPI4601UG (460 W) is provided in the system to support the P5040/P5020 devices, the reference board and all its I/O cards. VCC_12, VCC_12V_BULK, VCC_5V_STBY, and VCC_RTC_BAT are provided from the reference board. In addition, the P5040/P5020RDB PS provides all the voltages necessary for correct operation x2 DDR3 SODIMMs, GETH, FPGA, and all onboard peripherals.
Page 35 DUT types (depends on PROC_SEL switches: SW7[6:7], SW15[5]) as well as a lot of other optional power combinations which could be used for testing purposes. Power options supported are for P5040/P5021 and P5020/P5010 as shown highlighted in pink in the table below.
Page 36 SW1[6] "DRAM TYPE" following power on: SW1[6] = “1” (DDR3 regular) • DDR3 default GVDD = 1.5V • M_VTT = 0.75V • M_VREF = 0.75V P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 37 VDD_CORE VDD_CB voltage has the following characteristics: • Powers both cores A and B of P5040/P5020 Rev 1.0 and 2.0 devices. • Set SW6[7] to “0” to turn off voltage. The voltage connected/disconnected from corresponding power plane in conjunction with selected PDN options (see Table 5.3.1.8...
Page 38 Table 19 lists the requirements of the reference board clock signals when the reference board is populated with a P5040 or P5020 processor. This board uses a custom IDT 6T49278BNLGI8 clock to meet the requirements listed in the table below.
Page 39 This figure shows the principal clock connections for the P5040/P5020. Conversely, the reference board provides a battery to the RTC clock to keep time while the system is turned off. This table summarizes P5040/P5020 clock distribution. NOTE DDR clocks are provided by the P5040/P5020.
Page 40 33.33 MHz FPGA Clock Oscillator 5.4.1 SYSCLK A significant amount of P5040/P5020 timing is derived from SYSCLK input. The P5040/P5020 reference design board has the following features: • SYSCLK pin is controlled by an IDT ICS307M-02 frequency synthesizer. • IDT device, as part of the reset/power-up sequence, is serially configured by 24 data bits via ngPIXIS.
Page 41 0x310601 System Reset Figure 19 shows P5040/P5020RDB reset connections from which the following can be inferred: • ngPIXIS registers are reset by every reset input as well as GO. — GO is a VELA-controller output that is, in turn, controlled by ngPIXIS registers.
Page 42 External HOT power stable Restarts all FPGA internal state machines and registers PWRGD External 1U power stable Causes full system reset unless the system is in S3 (power down) state P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 43 Signal Type Description Action SYS_HRST_B External COP tool reset request Upon power good, sys_rst_b is sent to P5040/P5020 and all peripheral functional blocks RESET_REQ_B External CPU requests reset Full reset 5.5.2 Reset Terms All reset operations are conducted within various portions of the ngPIXIS. See Section 5.2.6,...
Page 44: Configuration
HRESET_B assertion interval. • Software running on the P5040/P5020 can initialize internal registers (SWx, ENx) that allow a board to configure itself for the next restart; this is called self-SHMOO or self-characterization. •...
Page 45 Expected to be easily or often changed by the end-user or developer When used with a P5040/P5020, the reference board switches and their default settings are shown in Appendix A, “Reference board Switch Assignments and Defaults When Used with P5040/P5020.” Switch names exactly match the name on the schematics and on the printed-circuit board in most cases, except where a spare has been newly assigned and only the FPGA has changed.
Page 46 Configuration Switch names exactly match those found in the schematics and on the printed circuit board. See the P5040/P5020RDB Configuration Sheet for help setting the system to a default configuration and for more information about switch functionality. • Dynamic (processor-only) configuration pins are only asserted during HRESET_B.
Page 47 SW_FLASH_WP SW_ID_WP AURORA_CLK_EN SW_VDD_POVDD_CNTL SW_RESET_REQ_MODE SW_LEGACY_POD_B 10G_P2_PHYAD[0-2] Static (see Switch 9 (SW9) 10G_P2_PHYAD0 description) XAUI_MDIO_SEL Spare SW11 SDREFCLK1_QB_FSEL0 — (see Switch 11 (SW11) SDREFCLK1_QB_FSEL1 Static description) SDREFCLK1_QB_FSEL1 — Spare P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 48: Programming Model
Base Address Offset Name ngPIXIS (PX) Register Access Reset 0x00 PX_ID System ID 0x20 0x01 PX_ARCH System Architecture Board revision-dependant 0x02 PX_SCVER System Control Version FPGA version-dependant 0x03 PX_CSR General Control/Status 0x00 P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 49 FPGA GPIO Out 0x1D PX_GPIO_IN FPGA GPIO IN 0x00 0x1F PX_WATCH WATCH 0x7F 0x20, 0x22,..., 0x30 PX_SW(1:8), Switches (1:8), 11 Variable PX_SW11 0x21, 0x23,..., 0x31 PX_EN(1:8), PX_EN11 Enable Switches (1:8), 0x00 P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 50 “backup” device. NOTE Changing a FLASH manufacturer is not considered an architectural change as CFI-compliant FLASH programmers are meant to be adaptable. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 51 Reset 0x02 Offset 0x02 Figure 24. Version Register (PX_SCVER) Table 29. PX_SCVER Field Descriptions Bits Name Description 0–7 • %00000001: Version 1 • %00000010: Version 2, etc. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 52 VELA sequencer. The setting of bits during a VELA configuration cycle can have unpredictable results. Figure 26. Reset Control Register (PX_RST) — — — — SXSLOT Reset Offset 0x04 P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 53 SDREFCLK3_ SDREFCLK4_ SERCLK_EN USBCLK_EN Reset Offset 0x05 The Default depends on chip: For P5040 =’1’, otherwise ‘0’; Table 32. PX_SERCLK Field Descriptions Bits Name Description Enables/disables the SerDes Reference Clock to Bank 1 and Slot 1 SDREFCLK1_QA_EN • 0 - disabled •...
Page 54 RX-AUX preserves its value between Aurora-, COP- or watchdog-initiated resets. Figure 28. Auxiliary Register (PX_AUX) USER Reset Offset 0x06 Table 33. PX_AUX Field Descriptions Bits Name Description 0–7 USER User defined P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 55 1 0 1 150.000 MHz 150 MHz 0 ppm 0x310501 1 1 0 160.000 MHz 160 MHz 0 ppm 0x310C03 1 1 1 166.666 MHz 167 MHz 2 ppm 0x310601 P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 56 SPI CS_B pins are pulled high. SD8X • 1 - Uses SPI_CS(0:3)_B pins with the SPI controller. SDHC data bits 4:7 are pulled high. Only uses SDHC-4bit mode. Bit [1]: used for P5040/P5020. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 57 Reserved Controls selection of 1588 riser card interface: SPI or I C4 bus interface. SPI_I C_SEL • 0 - I • 1 - SPI See reg_BRDCFG2[1:2] for extra control signals. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 58 Figure 33. Board Configuration Register 2 (PX_BRDCFG2) — REG/GPIO PS_PL_CNTR PS_CA_CNTR LANE_SATA_ MGN_DISABLE GPIO_TEST THERM_SHTN_ON _SEL _SEL Reset — Offset 0x0B The Default depends on chip: For P5040 = ‘1’, otherwise ‘0’. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 59 • 0- SATA Connectors signals are routed to P5020 BANK 3 Lanes 16, 17. • 1- XAUI signals are routed to P5040 BANK 3 Lanes 16, 17 In order to work with P5040 GPIO2, it is needed to program MGN_DISABLE = ‘1’ and GPIO_TEST = ‘1’. GPIO0 drives EMI1_SEL0; GPIO1 drives EMI1_SEL1;...
Page 60 Programming Model NOTE The direction of P5040/P5020 GPIO[0:7] must be configured. Figure 34. GPIO Direction (PX_GPIO_DIR) R/W GPIO(0) R/W GPIO1) R/W GPIO(2) R/W GPIO(3) R/W GPIO(4) R/W GPIO(5) R/W GPIO(6) R/W GPIO(7) Reset Offset 0x0C Table 42. PX_GPIO_DIR Field Descriptions...
Page 61 Figure 37. TAG Register (PX_TAG) Reset Offset 0x0F 7.1.17 VELA Control Register (PX_VCTL) The VELA control register can start and control the configuration reset sequencer as well as other configuration/test-related features. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 62 PWROFF = ‘1’ overrides any user- or APM-initiated power switch event. 7.1.18 VELA Status Register (PX_VSTAT) The VELA status register can be used to monitor configuration sequencer activity. NOTE Not supported for P5040/P5020RDB. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 63 • 0 - VELA sequencer is idle. BUSY • 1 - VELA sequencer is busy. 7.1.19 P5040/P5020RDB Status Register (PX_HSTAT) The P5040/P5020RDB status register can be used to monitor optional connectivity. Figure 40. P5040/P5020RDBP5040/P5020RDB Status Register (PX_HSTAT) PRESENT — —...
Page 64 Software sets the values. Use different software in the GMSA processor to redefine the values. 7.1.21 OCM Message Register (PX_OCMMSG) The OCM message register is a general-purpose R/W register used to communicate between P5040/P5020 and the FPGA GMSA processor. NOTE Not applicable for P5040/P5020RDB.
Page 65 CFG_SYSCLK(0:2) is used. 7.1.23 Watchdog Register (PX_WATCH) The watchdog register selects a watchdog timer event for the VELA-controlled sequencer. The selected watchdog works independently of other watchdog timers; for example, those within P5040/P5020. Figure 44. Watchdog Register (PX_WATCH) WVAL Reset...
Page 66 The switch register defines configuration switch overrides. Each SWx register and its bits correspond to a similarly named board switch. If a matching ENx bit is set then the value written to the corresponding register bit is selected, not the corresponding DIP-switch. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 67 0–7 ENx #b • 1 - Internal register SWx #b controls a corresponding configuration pin; the value is unaffected by the external switches. P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 68 When testing processor GPIO signals: reg_BRDCFG2[1] = ‘1’, reg_BRDCFG2[2] = ‘1’, and the corresponding PX_GPIO_DIR bit = ‘1’. EEPROM Data SystemID EEPROM stores important P5040/P5020RDB system data such as the board ID, errata (as shipped), manufacturing date, and Ethernet MAC address. P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 69: Revision History
Revision History This table provides a revision history for this document. Table 57. Document Revision History Rev. Date Substantive Change(s) Number 05/2013 Initial public release P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 70 Reference board Switch Assignments and Defaults When Used with P5040/P5020 Appendix A Reference board Switch Assignments and Defaults When Used with P5040/P5020 NOTE For the default settings listed in the tables below, ON = 1 and OFF = 0. The following tables describe the default settings for the devices listed.
Page 71 Reference board Switch Assignments and Defaults When Used with P5040/P5020 Figure 50. Switch 2 (SW2) description This figure describes switch 3 (SW3). Figure 51. Switch 3 (SW3) description P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 72 Reference board Switch Assignments and Defaults When Used with P5040/P5020 This figure describes switch 5 (SW5). Figure 52. Switch 5 (SW5) description This figure describes switch 6 (SW6). Figure 53. Switch 6 (SW6) description P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 73 Reference board Switch Assignments and Defaults When Used with P5040/P5020 This figure describes switch 7 (SW7). Figure 54. Switch 7 (SW7) description P5040/P5020 Reference Design Board User Guide, Rev. 0 Freescale Semiconductor...
Page 74 Reference board Switch Assignments and Defaults When Used with P5040/P5020 This figure describes switch 8 (SW8). Figure 55. Switch 8 (SW8) description This figure describes switch 9 (SW9). Figure 56. Switch 9 (SW9) description P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 75 Reference board Switch Assignments and Defaults When Used with P5040/P5020 This figure describes switch 11 (SW11). Figure 57. Switch 11 (SW11) description This figure describes switch 12 (SW12). Figure 58. Switch 12 (SW12) description P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 76 Reference board Switch Assignments and Defaults When Used with P5040/P5020 This figure describes switch 15 (SW15). Figure 59. Switch 15 (SW15) description This table describes SW17. Figure 60. Switch 17 (SW17) description P5040/P5020 Reference Design Board User Guide, Rev. 0...
Page 77 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based on the freescale.com information in this document.

This manual is also suitable for:

P5021 P5010 P5020