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4.2.21. PORT Y
Reset status
PORT
Function
PY0
After reset
Input Port
X1
EHCLKIN
PY1
After reset
Input Port
X2
PY2
After reset
Input Port
XT1
ELCLKIN
PY3
After reset
Input Port
XT2
During reset
PY4
(BOOT_N)
After reset
Output Port
ISDCOUT
EEXBCLK
USBA_SOF_TGL
Note: [PYPUP] is enabled during reset by the reset pin (RESET_N) or POR, Therefore, BOOT_N signal can be
input.
Table 4.22 Port Y registers setting
PORT
Input/Output
Type
[PYDATA]
Input
0/1
Input
FTU10
0/1
Input
FTU10
0/1
Input
0/1
Output
FTU10
0/1
Input
0/1
Input
FTU10
0/1
Input
FTU10
0/1
Input
0/1
Output
FTU10
0/1
Input
FTU6
Output
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Control register
[PYCR]
[PYFRn]
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
0
1
0
1
[PYFR1]
1
[PYFR4]
1
[PYFR6]
67 / 82
TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
[PYOD]
[PYPUP]
[PYPDN]
N/A
0
0
N/A
0/1
0/1
N/A
0
0
N/A
0
0
N/A
0
0
N/A
0/1
0/1
N/A
0
0
N/A
0
0
N/A
0/1
0/1
N/A
0
0
N/A
0
0
N/A
0
0
N/A
0/1
0/1
N/A
0
0
0
1 (Note)
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
[PYIE]
0
1
0
1
0
1
0
0
1
0
1
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
2021-01-18
Rev. 1.0
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