Table of Contents
Advertisement
4.2.7. PORT F
Reset status
PORT
Function
PF0
After reset
Input Port
Output Port
INT04b
ERD_N
PF1
After reset
Input Port
Output Port
EWR_N
PF2
After reset
Input Port
Output Port
EI2C1SDA
I2C1SDA
PF3
After reset
Input Port
Output Port
EI2C1SCL
I2C1SCL
PF4
After reset
Input Port
Output Port
ECS2_N
PF5
After reset
Input Port
Output Port
ECS3_N
USBB_SOF_TGL
PF6
After reset
Input Port
Output Port
EBELL_N
CANATX
PF7
After reset
Input Port
Output Port
INT05b
EBELH_N
TSPI2CSIN
TSPI2CS0
CANARX
Table 4.8 Port F registers setting
PORT
Input/Output
Type
[PFDATA]
Input
0/1
Output
0/1
Input
FTU4
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
I/O
FTU1
0/1
I/O
FTU1
0/1
Input
0/1
Output
0/1
I/O
FTU1
0/1
I/O
FTU1
0/1
Input
0/1
Output
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
Input
FTU4
0/1
Output
FTU1
0/1
Input
FTU1
0/1
Output
FTU1
0/1
Input
FTU1
0/1
Control register
[PFCR]
[PFFRn]
0
0
0
0
0
1
0
0
0
1
[PFFR1]
0
0
0
0
0
1
0
1
[PFFR1]
0
0
0
0
0
1
0
1
[PFFR6]
1
[PFFR7]
0
0
0
0
0
1
0
1
[PFFR6]
1
[PFFR7]
0
0
0
0
0
1
0
1
[PFFR1]
0
0
0
0
0
1
0
1
[PFFR1]
1
[PFFR6]
0
0
0
0
0
1
0
1
[PFFR1]
1
[PFFR6]
0
0
0
0
0
1
0
0
0
1
[PFFR1]
0
[PFFR4]
1
[PFFR5]
0
[PFFR6]
46 / 82
TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
[PFOD]
[PFPUP]
[PFPDN]
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
1
0/1
0
1
0/1
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
1
0/1
0
1
0/1
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
[PFIE]
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
2021-01-18
Rev. 1.0
Advertisement
Table of Contents
