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TXZ Plus Series
Reference manual
Port L; Table 4.13 Port L Registers Setting - Toshiba TXZ Plus Series Reference Manual
32-bit risc microcontroller
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4.2.12. PORT L
Reset status
PORT
Function
PL0
After reset
Input Port
Output Port
INT01a
T32A02INA0
T32A02INC0
SMI0D4
TSPI1CSIN
TSPI1CS0
EMATXD0/
EMA_R_TXD0
PL1
After reset
Input Port
Output Port
SMI0D5
TSPI1SCK
EMARXCLK/
EMA_R_REFCLK
PL2
After reset
Input Port
Output Port
SMI0D6
TSPI1RXD
EMARXD0/
EMA_R_RXD0
PL3
After reset
Input Port
Output Port
T32A02INB0
T32A02INC1
SMI0D7
TSPI3CS1
TSPI1TXD
EMARXD1/
EMA_R_RXD1
PL4
After reset
Input Port
Output Port
INT12b
T32A08OUTA
T32A08OUTC
PL5
After reset
Input Port
Output Port
INT13b
T32A08OUTB
Table 4.13 Port L registers setting
PORT
Input/Output
Type
[PLDATA]
Input
0/1
Output
0/1
Input
FTU4
0/1
Input
FTU1
0/1
Input
FTU1
0/1
I/O
FTU2
0/1
Input
FTU1
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
I/O
FTU2
0/1
Input
0/1
FTU1
Output
0/1
Input
FTU1
0/1
Input
0/1
Output
0/1
I/O
FTU2
0/1
Input
FTU1
0/1
Input
FTU1
0/1
Input
0/1
Output
0/1
Input
FTU1
0/1
Input
FTU1
0/1
I/O
FTU2
0/1
Output
FTU1
0/1
Output
FTU2
0/1
Input
FTU1
0/1
Input
0/1
Output
0/1
Input
FTU4
0/1
Output
FTU1
0/1
Output
FTU1
0/1
Input
0/1
Output
0/1
Input
FTU4
0/1
Output
FTU1
0/1
Control register
[PLCR]
[PLFRn]
0
0
0
0
0
1
0
0
0
0
[PLFR2]
0
[PLFR3]
1
[PLFR5]
0
[PLFR6]
1
[PLFR7]
1
[PLFR8]
0
0
0
0
0
1
0
1
[PLFR5]
0
[PLFR7]
1
[PLFR7]
0
[PLFR8]
0
0
0
0
0
1
0
1
[PLFR5]
0
[PLFR7]
0
[PLFR8]
0
0
0
0
0
1
0
0
[PLFR2]
0
[PLFR3]
1
[PLFR5]
1
[PLFR6]
1
[PLFR7]
0
[PLFR8]
0
0
0
0
0
1
0
0
0
1
[PLFR2]
1
[PLFR3]
0
0
0
0
0
1
0
0
0
1
[PLFR2]
53 / 82
TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
[PLOD]
[PLPUP]
[PLPDN]
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
[PLIE]
0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
2021-01-18
Rev. 1.0
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