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Address
Name
0x0F
RF(ISR)
0x0A
IOCA
0x0B
IOCB
0x0C
IOCC
0x0D
IOCD
0x0E
IOCE
0x0F
IOCF
0x10~0x2F R10~R2F
** To jump address 0x08, or to execute the instruction which is next to the "SLEP" instruction.
X: Not used. U: Unknown or don't care. P: Previous value before reset. t: Check Table 6
2. The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
This specification is subject to change without prior notice.
Reset Type
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit 7
Bit 6
Bit 5
P
P
P
X
X
X
U
U
U
U
U
U
U
U
U
-
-
-
1
1
1
1
1
1
P
P
P
/PD7
/PD6
/PD5
1
1
1
1
1
1
P
P
P
OD7
OD6
OD5
0
0
0
0
0
0
P
P
P
/PH7
/PH6
/PH5
1
1
1
1
1
1
P
P
P
WDTE
EIS
X
1
0
U
1
0
U
1
P
U
X
X
X
U
U
U
U
U
U
U
U
U
-
-
-
U
U
U
P
P
P
P
P
P
22
EM78P156EL
OTP ROM
Bit 4
Bit 3
Bit 2
P
P
P
X
X
EXIF
U
U
0
U
U
0
U
U
P
-
-
-
1
1
1
1
1
1
P
P
P
/PD4
X
/PD2
1
U
1
1
U
1
P
U
P
OD4
OD3
OD2
0
0
0
0
0
0
P
P
P
/PH4
/PH3
/PH2
1
1
1
1
1
1
P
P
P
ROC
X
X
0
U
U
0
U
U
P
U
U
X
X
EXIE
U
U
0
U
U
0
U
U
P
-
-
-
U
U
U
P
P
P
P
P
P
Bit 1
Bit 0
P
P
ICIF
TCIF
0
0
0
0
P
P
-
-
1
1
1
1
P
P
/PD1
/PD0
1
1
1
1
P
P
OD1
OD0
0
0
0
0
P
P
/PH1
/PH0
1
1
1
1
P
P
X
X
U
U
U
U
U
U
ICIE
TCIE
0
0
0
0
P
P
-
-
U
U
P
P
P
P
2002/04/19
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