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Acromag IP1K100 Series User Manual

Industrial i/o pack reconfigurable digital i/o board
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Series IP1K100 Industrial I/O Pack
Reconfigurable Digital I/O Board
r e t i r e d
USER'S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
P.O. BOX 437
Wixom, MI 48393-7037 U.S.A.
Tel: (248) 624-1541
Fax: (248) 624-9234
Copyright 2001, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8500-681-B02H012

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  • Page 1 USER’S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P.O. BOX 437 Wixom, MI 48393-7037 U.S.A. Tel: (248) 624-1541 Fax: (248) 624-9234 Copyright 2001, Acromag, Inc., Printed in the USA. Data and specifications are subject to change without notice. 8500-681-B02H012...

  • Page 2: Table Of Contents

    TTL TRANSCEIVERS……………………………………… The information contained in this manual is subject to change INDUSTRIAL I/O PACK COMPLIANCE..…....without notice. Acromag, Inc. makes no warranty of any kind with APPENDIX............…....regard to this material, including, but not limited to, the implied CABLE: MODEL 5025-551......…...…...

  • Page 3: Key Ip1K100 Features

    APC8610 ISA bus, APC8620/21 PCI bus, and ACPC8625/30/35 low cost. Compact PCI bus non-intelligent carrier boards). A wide range of other Acromag IP modules are also available to serve your signal conditioning and interface needs. KEY IP1K100 FEATURES •...

  • Page 4: Ip Module Vxworks Software

    Acromag personal computer carrier and consist of an ActiveX environment and the board is exposed to environmental air, careful Carrier Control, and an ActiveX control for each Acromag IP module, consideration should be given to air-filtering. as well as, a generic control for non-Acromag IP modules.

  • Page 5: I/O Noise And Grounding Considerations

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ node n. The bus must form a single continuous path, and the nodes Table 2.1: IP1K100 Field I/O Pin Connections (P2) in the middle of the bus must not be at the ends of long branches, Pin Description Pin Description spokes, or stubs.

  • Page 6: 3.0 Programming Information

    IP1K100 is in user mode and the Altera FPGA has control of the IP bus interface. When Pin 168 (Config_Enable) is An example program written in C is available from Acromag driven high the IP1K100 is in configuration mode. (ActiveX Control, or VxWorks software) implements configuration of...

  • Page 7: Ip Identification Space

    IP bus data lines, and c) and disable IP bus write cycles on the Altera FPGA. The following VHDL code serves as an example of these requirements. Acromag ID Code IP Model Code Process (ACK, Config_Enable) 40 = Config. Mode...

  • Page 8: Control Register

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ Notes (Table 3.3): The I/O space address map for this example design is given in 1. The IP will respond to addresses that are "Not Used" with an Table 3.3. The differential or TTL I/O, clock generator chip, and active IP module acknowledge ACK∗.

  • Page 9: Input/Output Registers

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ The register bits not listed will not be used. See the memory map to Input/Output Registers (Read/Write) - (Base + 02H to 07H) identify the addresses required to control I/O registers. Fourty-eight possible input/output channels numbered 0 through Table 3.4: Input/Output Registers 47 may be individually accessed via these registers.

  • Page 10: Interrupt Status Register

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ specified by the Interrupt Polarity Register occurs (i.e. Low or High Interrupt Polarity Registers (Read/Write) - (Base + 11H) level transition interrupt). A “1” bit means the interrupt will occur when a Change-Of-State (COS) occurs at the corresponding input The Interrupt Polarity Register determines the level that will channel (i.e.

  • Page 11: Memory Address Register

    Shift High register at Base Address + 18H. Note that the value calculated by the Acromag program Clock Generator Length Register (Write Only) - (Base + 1DH) BitCalc2K1 can be used as generated.

  • Page 12: Ip1K100 Programming Considerations

    Acromag personal computer carrier and consist of an ActiveX corresponding to the IP interrupt request to be enabled. Carrier Control, and an ActiveX control for each Acromag IP module, 6. Enable interrupts from the carrier board by writing a “1” to bit 3 as well as, a generic control for non-Acromag IP modules.

  • Page 13: 4.0 Theory Of Operation

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ 5. Clear pending interrupts by writing a “1” to each channel’s transceivers. RS485 signals received are converted from the respective bit in the Interrupt Status Register. required EIA RS485/RS422 voltages signals to the TTL levels required by the FPGA.

  • Page 14: Eia-Rs485 And Rs422 Serial Interface

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ nBS0, and nBS1. Table 4.1 lists the FPGA pins corresponding to Fail-Safe Operation these signals. The IP bus 8MHz clock signal is present on pin IP The IP1K100 operation is considered ‘Fail-safe’. That is, the CLK.
  • Page 15 SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ Signal Signal Init_Done Output (To CPLD) DIO12 Bi-Dir VCCINT 2.5Volts VCCIO 3.3Volts VCCIO 3.3Volts DIO13 Bi-Dir DIO14 Bi-Dir RAMa11 Output DIO15 Bi-Dir RAMa12 Output DIO16 Bi-Dir RAMa13 Output DIO17 Bi-Dir RAMa14 Output DIO18...

  • Page 16: 5.0 Service And Repair

    (Pulled High) difficult to repair. It is highly recommended that a non-functioning Input (Tied Low) board be returned to Acromag for repair. The board can be easily DCLK Input (Pulled High) damaged unless special SMT repair and service tools are used.

  • Page 17: Environmental

    Altera software and is used to program the Altera FPGA over the TTL TRANSCEIVERS IP bus interface. Channel Configuration……..…. Up to 48, non-isolated TTL NineK453a.vhd…..….…..……… Acromag provided VHDL signals. Selected in blocks of 8 (hardware design language) channels when ordered. source file supports IP bus interface to ID, IO, and INT space.

  • Page 18: Appendix

    Compiler, Simulator, and Timing Connections to AVME9630/9660, APC8610, or APC8620/1: P1, Analyzer for an entire project. 50-pin male header with strain relief ejectors. Use Acromag 5025-551-x cable to connect panel to VME board. Keep cable Clock Generator Clock Generator IC…………….. Cypress ICD2053B as short as possible to reduce noise and power loss.

  • Page 24: 4501-464 Termination Panel 5025-552

    SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE ___________________________________________________________________________________________ 4 5 0 1 -4 6 4 A - 24 -...

This manual is also suitable for:

Ip1k100-0024Ip1k100-2412Ip1k100-4800

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