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Summary of Contents for Acromag IP-EP201 Series
- Page 1 (217) 352-9330 | Click HERE Find the Acromag IP-EP201 at our website:...
- Page 2 Digital I/O Modules USER’S MANUAL ACROMAG INCORPORATED Tel: (248) 295-0310 30765 South Wixom Road Fax: (248) 624-9234 P.O. BOX 437 Wixom, MI 48393-7037 U.S.A. Copyright 2011, Acromag, Inc., Printed in the USA. 8500-797-C12A021 Data and specifications are subject to change without notice.
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Page 3: Table Of Contents
Interrupt Enable Register........Interrupt Type Configuration Register..... Interrupt Status Register........Interrupt Polarity Register......... Interrupt Vector Register........Memory Data Register........Memory Address Register........ Clock Control Registers........Clock Trigger Register........Clock Programming Procedure......Programming Interrupts........__________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... - Page 4 IP-EP2 Series board. PUBLICATIONS IP-EP2 FPGA Programming Guide Acromag IP-EP2-EDK 71V016SA SRAM Specifications http://www.idt.com Cyclone II Data Book http://www.altera.com CY22150 Specification http://www.cypress.com IP Specification http://www.vita.com ANSI/VITA 4-1995 Trademarks are the property of their respective owners. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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Page 5: General Information
4 channels. Long Distance Data Transmission – Data transmission with RS485/RS422 Transceivers allow up to 32 nodes and up to 4000 feet of transmission cable. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 6: Industrial I/O Pack Interface Features
High Speed - Access times for all data transfer cycles are described in terms of "wait" states. For the supplied IP module example, wait states are minimized for all read and write operations (see specifications for detailed information). __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 7: Signal Interface Products
(including Acromag’s AVME9668 VMEbus, APC8620A/21A PCI bus, and ACPC8625/30/35 Compact PCI bus non-intelligent carrier boards). A wide range of other Acromag IP modules are also available to serve your signal conditioning and interface needs. Refer to the Appendix for more... -
Page 8: Ip-Ep2 Engineering Design Kit
Acromag IP modules and Carriers, PCI I/O Cards, and CompactPCI I/O Cards. The software is implemented as a library of “C” functions which link with existing user code to make possible simple control of all Acromag PCI boards. IP MODULE QNX... -
Page 9: Preparation For Use
For repairs to a product damaged in shipment, refer to the Acromag Service Policy to obtain return instructions. It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped. -
Page 10: Ip Field I/O Connector
I/O21+ I/O42 MAY DAMAGE THE I/O09+ I/O18 I/O21- I/O43 BOARD. I/O09- I/O19 I/O22+ I/O44 I/O10+ I/O20 I/O22- I/O45 I/O10- I/O21 I/O23+ I/O46 I/O11+ I/O22 I/O23- I/O47 I/O11- I/O23 External Clock Input I/O12+ I/O24 __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 11: Ip Logic Interface Connector
P1 are standard for all IP modules according to the Industrial I/O Pack Specification (see Table 2.4). However some logic signals not used for the IP interface are reserved for factory programming. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 12: Non-Isolation Considerations
I/O grounds. As such, the field I/O connections are not Considerations isolated from the system. Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 13: Programming Information
As such, use of this module on a PC carrier board will require the use of the even address locations to access the 8-bit data, while a VMEbus carrier requires the use of odd address locations. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 14: Configuration Registers
Altera JTAG download cable such as the ByteBlaster 2 . This cable is NOT provided by Acromag. Once again all programming is lost at power-down using the direct JTAG configuration approach. - Page 15 Cyclone II Based FPGA IP Module __________________________________________________________________ An example program written in C and available from Acromag, implements configuration of the IP-EP2 Series module over the IP bus. The program requires the configuration file to be in the Intel Hex format. For information on generating hex files refer to the documentation supplied with the EDK.
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Page 16: Ip Identification Space
In user mode, the ID space must be defined in the internal logic of the FPGA. In order for Acromag software to properly identify the model, this ID space must remain as defined in Table 3.2. Note that the base-address for the IP module ID space (see your carrier board instructions) must be added to the addresses shown to properly access the ID information. -
Page 17: User Mode
Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention. The Intel x86 family of microprocessors uses “Little Endian” byte ordering. In Little Endian, the lower-order byte is stored at even-byte addresses. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 18: Base Addr
Not Used Interrupt Vector Register Memory Data Register Memory Address Register Clock Control Register 1 Clock Control Register 2 Not Used Clock Control Register 3 Clock Generator Trigger Not Used Register Not Used __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 19: Control Register
Direction Control register. Note: if you select as an output port before setting this Input/Output register, the output port will be logic low as this is the power-up/reset state of the output register bits. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 20: Direction Control Registers
All not used bits will read low logic. See Table 2.1 for field I/O pin assignments corresponding to each of the Differential and TTL channels listed below. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 21: Interrupt Enable Register
A “0” bit selects interrupt on level. An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs (i.e. Low or High level transition interrupt). A “1” bit means __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 22: Interrupt Status Register
A “0” bit specifies that an interrupt will occur when the corresponding input channel is low (i.e. a “0” in the digital input channel data __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 23: Interrupt Vector Register
Memory Address register need not be manually updated by software. Read or write accesses to this register require four wait states. A software or hardware reset has no affect on this register. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 24: Memory Address Register
Cypress CY22150 Programmable Clock. The register contains the following control bits as specified in the Cypress CY22150 spec sheet. Data Data PB(0) PB(8) PB(1) PB(9) PB(2) Pump(0) PB(3) Pump(1) PB(4) Pump(2) PB(5) CLKSRC0 PB(6) CLKSRC1 PB(7) CLKSRC2 __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 25: Clock Trigger Register
The program words required for Clock Control Register 1, 2, and 3 can be calculated using a program provided by Acromag (BitCalc2K1 Version 2) supplied with the EDK. Alternately, using the Clock Control Registers Data Maps and the CY22150 specification sheet the necessary values can be calculated. -
Page 26: Programming Interrupts
The Interrupt Input Response Time is specified in section 6. The following programming examples assume that the IP-EP2 Series module is installed onto an Acromag AVME9630/9660/9668 carrier board (consult your carrier board documentation for compatibility details). __________________________________________________________________________... - Page 27 5. Clear pending interrupts by writing a “1” to each channel’s respective bit in the Interrupt Status Register. Interrupts can now be generated by matching the input level with the selected polarity for programmed interrupt channels. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
- Page 28 If the stimulus cannot be removed, the IP-EP2 should be disabled or reconfigured. B. If other IP modules have interrupts pending, then the interrupt request (IRQx ) will remain asserted. This will start a new interrupt cycle. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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Page 29: Theory Of Operation
(polarity) match conditions at enabled inputs. An 8-bit interrupt service routine vector is provided during interrupt acknowledge cycles on data lines D0...D7. The interrupt release mechanism employed is RORA (Release On Register Access). __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 30: Field I/O
RS485/RS422 voltages to the LVTTL levels required by the FPGA. Likewise, LVTTL signals are converted to the EIA RS485/RS422 voltages for data output transmission. The direction control of the differential channels is controlled in groups of four. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 31: Jtag Interface
CLK8MZ. The function and timing requirements of all IP bus signals are specified in the ANSI/VITA 4 1995 specification. Copies of the ANSI/VITA 4 1995 specification are available from VITA (www.vita.com). __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 32: Fpga Initialization
FLASH at power-up if the programming jumper is set to the “FLASH” position. Refer to the Configuring Chapter of the Cyclone II Device Handbook from Altera for further information. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 33: Service And Repair
REPAIR repair. It is highly recommended that a non-functioning board be returned to Acromag for repair. The board can be easily damaged unless special SMT repair and service tools are used. Further, Acromag has automated test equipment that thoroughly checks the performance of each board. When a board is first produced and when any repair is made, it is tested, placed in a burn-in room at elevated temperature, and retested before shipment. -
Page 34: 6.0 Specifications
150KHz to 80MHz) and European Norm EN50082-1 with no register upsets. Electromagnetic Interference Immunity (EMI): No register upsets occur under the influence of EMI from switching solenoids, commutator motors, and drill motors. Surge Immunity: Not required for signal I/O per European Norm EN50082-1. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 35: Board Components
Interrupts: Generates INTREQ0* interrupt request as configured in the example program. An INT select cycle will return the Interrupt Vector Register. INTREQ1* is available but not implemented in the example design. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 36: Differential Input/Output
Driver Input to Output Delay = 27ns Typical, 40ns Maximum Receiver Input to Output Delay = 33ns Typical, 60ns Maximum Termination Resistors Termination Resistors: Termination resistors are not provided. External 120 Ohm termination resistors for EIA RS485/422 differential receivers are recommended. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 37: Digital Input/Output
Receiver Output Signal Transition Time = 1.5ns Maximum Maximum Data Rate Maximum Data Rate: 100MHz @ 1m Termination Resistors: Non-removable 100 termination resistors are in Termination Resistors place for each of the LVDS channels. __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 38: External Clock Input
FPGA from FLASH. During this time the board will act as if it is not configured until the download to the FPGA is complete. It is good practice to reset the board (using either an IP bus or software reset) subsequent to power-up. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 39: Appendix
Headers (Both Ends): 50-pin female header with strain relief. Header - Acromag Part 1004-512 (3M Type 3425-6600 or equivalent). Strain Relief - Acromag Part 1004-534 (3M Type 3448-3050 or equivalent). Keying: Headers at both ends have polarizing key to prevent improper installation. -
Page 40: Transition Model Trans-Gp
Field Wiring: 100-pin header (male) connectors (3M 3433-D303 or equivalent) employing long ejector latches and 30 micron gold in the mating area (per MIL-G-45204, Type II, Grade C). Connects to Acromag termination panel 5025-552 from the rear of the card cage via flat 50-pin ribbon cable (cable Model 5025-551-X). -
Page 41: Ip-Ep2 Block Diagram
IP-EP2 Series User’s Manual Cyclone II Based FPGA IP Module __________________________________________________________________ __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 42: Rs485 I/O Connections
4. INSERT PAN HEAD SCREWS (ITEM C) THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS (ITEM B) AND TIGHTEN (4 PLACES). THE RECOMMENDED TORQUE IS 0.226 NEWTON METER OR 2 INCH POUNDS. OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD. __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 43: 4501-463 Cable 5025-551 (Shielded)
IP-EP2 Series User’s Manual Cyclone II Based FPGA IP Module __________________________________________________________________ 4501-463 4 5 0 1 -4 6 4 A __________________________________________________________________________ Acromag, Inc. Tel: 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com... -
Page 44: 4501-465 Transition Module Trans-Gp
IP-EP2 Series User’s Manual Cyclone II Based FPGA IP Module ___________________________________________________________________ __________________________________________________________________________ Acromag, Inc. 248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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