Related Manuals for HOLT ADK-25850FMC
Summary of Contents for HOLT ADK-25850FMC
- Page 1 ADK-25850FMC Quick Start Guide – Dual HI-25850 Transceiver FMC Demonstration Board February 2023 QSG-25850FMC Rev. B Holt Integrated Circuits...
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Page 2: Revision History
REVISION HISTORY Revision Date Description of Change QSG-25850FMC Rev. New 09/08/2020 Initial Release. Update BOM for both boards. Minor update to Rev. A 05/30/2021 schematic. Rev. B 02/10/2023 Update for new board with pinout changes. QSG-25850FMC Rev. B Holt Integrated Circuits... - Page 3 The Holt ADK-25850FMC is a dual channel MIL-STD-1553 transceiver FPGA Mezzanine Card (FMC) populated with one or two Holt HI-25850 121 BGA dual redundant transceivers. The FMC card uses the standard IAW VITA 57.1 form factor. The user has the choice to use the FMC connectors or two PMOD connector headers for interfacing to a host or FPGA.
- Page 4 QSG-25850FMC Figure 2 - ADK-25850FMC MIL-STD-1553 cable assembly (only one shown, -2 includes two sets). Features: • One or two channel HI-25850 dual redundant MIL-STD-1553 transceivers • FPGA Mezzanine Card; VITA 57.1 • FMC or PMOD connectivity • DIP switches and jumpers configuration options •...
- Page 5 CAUTION: ENSURE THE PROPER VOLTAGE IS SELECTED FOR THE TARGET FPGA. IF THE HOLT CARD VOLTAGE DOES NOT MATCH THE HOST/FPGA, DAMAGE TO THE FPGA OR HOLT CARD MAY OCCUR.
- Page 6 RXENA and RXENB inputs. The RX and nRX receive outputs have an option to stretch minimum output pulse width. When receiving differential signals near the MIL-STD-1553 minimum amplitude specification (860 mVpp or less when QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 7 Crossover should occur mid-way between ground and the VDDIO supply rail to assure acceptable “output symmetry” or “tail-off” occurring at the end of long transmit messages. This effect is discussed at length in Holt application note AN-550. Transmit Signal Sync Option To accurately synchronize TX and nTX inputs, the HI-25850 offers the option to simultaneously clock transmit input signals for each bus with a clock pulse input pin.
- Page 8 A transformer-coupled 1553 bus interface is the predominant configuration used for terminal connection. This diagram shows a network comprised of three transformer-coupled terminals: a Bus Controller (BC) and two Remote Terminals (RTs). Stub cables must be < 20 feet (6.1 meters). QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 9 The bus couplers have a bus connection jack at each end for serial connection into the 1553 bus structure. Each end of the bus has a 78Ω terminator. Holt application note AN-550 provides additional information about the direct- and transformer-coupled configurations.
- Page 10 Note: For this Table 3, Channel 0 refers to BusA and BusB on U1, Channel 1 refers to BusA and BusB on U2. For other power supply related jumpers see Table 1 and Table 2 the beginning of this document. QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 11 HK18,19,20 Grounds HK10 3.3V regulator output for U1 HI11 3.3V regulator output for U2 HK15 VDDIO Voltage going to U1 andU2 (sets the rail voltage for the host interface. HK14 1.8V regulator HK16 2.5V regulator QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 12 QSG-25850FMC Table 6 - FMC VITA 57.1 FPGA Low-Pin Connector QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 13 Note 1 – For proper encoder/decoder designs both the normal and semi-complimented signal pairs are required. The signal pairs are not exactly inverted from each other. See data sheet page 10 for example waveforms or refer to the diagrams below. Figure 6 - Transmit Waveform Example QSG-25850FMC Rev. B Holt Integrated Circuits...
- Page 14 QSG-25850FMC Figure 6 - Receive Waveform Example Board Files and Schematic Links BOM and Schematic Files: EV-25850FMC-1 BOM and Schematic Files: EV-25850FMC-2 QSG-25850FMC Rev. B Holt Integrated Circuits...