Related Manuals for HOLT ADK-5200
Summary of Contents for HOLT ADK-5200
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Page 1: Quick Start Guide
ADK-5200 Quick Start Guide: HI-5200 10Base-T/100Base-TX Physical Layer Transceiver April 2018 QSG-5200 Rev. A Holt Integrated Circuits... - Page 2 QSG-5200 REVISION HISTORY Revision Date Description of Change QSG-5200, Rev. New 02-09-18 Initial Release Rev. A 04-23-18 Remove HI-5201 option Holt Integrated Circuits...
- Page 3 QSG-5200 Introduction The Holt HI-5200 is a 10Base-T/100Base-TX physical layer transceiver with both MII and RMII MAC interfaces. It utilizes a unique mixed-signal design to extend signaling distance while reducing power consumption, and offers HP Auto MDI/MDI-X for reliable detection of and correction for crossover and straight-through cables.
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Page 4: Hardware Design Overview
Magnetic Signals Module RMII Mode Only (From MAC) HI-5200PC RMII 50 MHz REF_CLK TX / RX 10Base-T Pairs 100Base-TX RJ45 Jack 25 MHz Crystal Oscillator Reset Button MII Mode Only Figure 2. ADK-5200 Evaluation Board Block Diagram Holt Integrated Circuits... - Page 5 The HI-5200 PHY board has a bottom-side 50-pin connector J1 for MII connection. Table 1 lists the pin- outs for the MII interface on connector J1. Table 1. Connector J1 Fast Ethernet Port MII Pin Definition. J1 Pin # Signal J1 Pin # Signal MDIO RXD3 RXS2 RXD1 RXD0 RXDV RXCLK RXER TXER TXCLK Holt Integrated Circuits...
- Page 6 RMII MACs. Like MII mode, the HI-5200 ADK PHY evaluation board, ADK-5200, receives power and accesses RMII data and management information via connector J1 in RMII mode. In RMII mode, the 50MHz clock (from the MAC) is connected to the XI pin.
- Page 7 Table 2. Connector J1 Fast Ethernet Port RMII Pin Definition. J1 Pin # Signal J1 Pin # Signal MDIO not used not used RXD1 RXD0 RXDV not used RXER not used REFCLK TXEN TXD0 TXD1 not used not used not used not used Holt Integrated Circuits...
- Page 8 QSG-5200 J1 Pin # Signal J1 Pin # Signal Holt Integrated Circuits...
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Page 9: Jumper Setting & Definition
[close, open, open] PCS Loopback All other CONFIG[2:0] combinations are reserved, not used. Jumper Definition Open (default) Closed Isolate Mode Disabled Enabled Auto Negotiation Enabled Disabled Forced Speed 100Base-TX 10Base-T JP10 Forced Duplex Half Duplex Full Duplex Holt Integrated Circuits... - Page 10 0 bit 8 as the Duplex Mode. Nway Auto-Negotiation Enable Pull-Up = Enable Auto-Negotiation (default) NWAYEN Pull-Down = Disable Auto-Negotiation At power-up / reset, the state of this pin is latched into register 0 bit 12. Holt Integrated Circuits...
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Page 11: Test Point Definition
+1.8VDC core logic PLL voltage check TP22 +3.3VDC IC supply voltage check RJ-45 Ethernet Connector The RJ-45 Connector (J2) connects to standard CAT-5 Ethernet cable to interface with 10Base- T/100Base-TX Ethernet devices. J2 also supports Auto-MDIX and Auto-Negotiation / Forced Modes. Holt Integrated Circuits... -
Page 12: Led Indicators
Blinking U1 Pin 31 U1 Pin 30 Activity LED State Link LED State State State No Activity No Link Activity Link Reserved – Not Used Reserved – Not Used Reserved – Not Used Reserved – Not Used Holt Integrated Circuits... - Page 13 Crystal 25Mhz 18pF Leaded HC49/US XC1927-ND ECS-250-18-4X-DU IC Reg Linear 3.3V 500mA SOT23-5 576-2756-1-ND Micro Chip MIC5216-3.3YM5-TR 1 HI-520X PQ & PC Holt Inc. HI-520X PQ & PC 3M SJ61A11 4 Bumper Cylin 0.312" Dia, 0.210" High, Blk Place at four corners SJ5747-0-ND...
- Page 14 TX_EN Input pin 9 (XI input). NWAYEN LEDK0 JUMPER JUMPER Output TXD[1] Input 3. Select RMII mode by setting jumpers JP6:JP4 RXD[1] HOLT INTEGRATED CIRCUITS for signals CONFIG[2:0] to '001'. SPEED LEDK1 JUMPER JUMPER Output TXD[0] Input Title Title Title...