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QSG-25850FMC
50mA. See pages 11 and 12 of the data sheet for more information on current and power dissipation of
these devices.
Figure 3 - HI-25850 Block Diagram
Note: Figure 3 Transceiver Block Diagram is showing BusA only
Bus Receive Signal Path
A pair of CMOS logic-levels depending on the voltage selected by J9 (1.8V, 2.5V or 3.3V) provides bipolar
serial signals for connecting each bus to an external user-provided Manchester decoder. RXA and nRXA
are the non-inverted and inverted receiver outputs for Bus A; RXB and nRXB are the receiver outputs for
Bus B. The logic-level Bus A and Bus B receiver outputs can be enabled/disabled using the transceiver
RXENA and RXENB inputs.
The RX and nRX receive outputs have an option to stretch minimum output pulse width. When receiving
differential signals near the MIL-STD-1553 minimum amplitude specification (860 mVpp or less when
QSG-25850FMC Rev. B
Holt Integrated Circuits
6
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