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MDX-CA790X
5-1.
BLOCK DIAGRAM – SERVO Section –
48
OPTICAL PICK-UP BLOCK
(KMS-242E)
I
I
1
RF AMP
J
J
2
F
B
C
B
I
J
D
A
A
A
4
B
5
I-V
C
E
AMP
6
D
DETECTOR
7
C
D
E
E
8
I-V
F
F
AMP
9
AUTOMATIC
ILCC
APC
LD/PD
POWER CONTROL
11
AMP
Q1
PD
LD
LASER DIODE
MON
PD
10
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC2
16
PSB
SPFD
OUT4F
6
IN4R
3
M901
M M
SPRD
(SPINDLE)
8
OUT4R
IN4F
4
27
OUT2F
IN2F
29
M902
M
(SLED)
IN2R
25
OUT2R
30
2-AXIS
DEVICE
FCS+
21
OUT1F
IN1F
19
23
OUT1R
IN1R
18
FCS–
TRK+
12
OUT3F
IN3F
14
TRK–
10
OUT3R
IN3R
15
47
RF AMP,
FOCUS/TRACKING ERROR AMP
IC1
RFO
AGCI
RF
RF AGC
46
40
38
& EQ
EQ
WBL
B.P.F.
AUX
AUX
33
3T
PEAK
PEAK
37
TEMP
PEAK &
BOTM
BOTM
BOTTOM
36
WBL
AT
ADFM
ADIN
ADFG
B.P.F.
29
30
32
AMP
ABCD
ABCD
ABCD
35
AMP
FE
FE
FOCUS
34
ERROR AMP
TE
TE
26
TRACKING
SE
SE
ERROR AMP
28
COMMAND
SERIAL/PARALLEL
CONVERTER,
F0CNT
V-I
20
DECODER
CONVERTER
12
16
17
18
PEAK HOLD
Q2
MD DSP
IC4 (2/2)
74
83 92 91 80 81 84 82
SFDR
ANALOG MUX
112
SRDR
111
A/D CONVERTER
DIGITAL SERVO
SIGNAL
FFDR
PROCESS
FROM CPU
64
FRDR
INTERFACE
65
XLRF
XLRF
71
CKRF
CKRF
AUTO
72
SEQUENCER
DTRF
DTRF
73
TFDR
77
TRDR
76
FOK/FCS
120
MD DSP
IC4 (1/2)
FILI
105
PCO
104
PLL
CLTV
107
FILO
106
ASYO
98
ASYI
99
COMPA-
RFI
RATOR
102
SUBCODE
PROCESSOR
ADFG
ADIP
67
DECODER
CPU
F0CNT
SPINDLE
INTERFACE
70
SERVO
114 113
16
35
15
14
13
9 10 11
SERVO
3.3V
52
46
94
95
16
17
REF_
41
LEVEL
MD MECHANISM CONTROLLER
IC7 (1/2)
100
84
85
(LIMIT)
5
4
LOADING
MOTOR DRIVE
IC6
REFERENCE VOLTAGE
VREF
6
REGULATOR
Q3
1
7
M
M903
(LOADING)
20
20
• R-ch is omitted due to same as L-ch.
• SIGNAL PATH
DADT
36
: MD PLAY
XBCK
38
LRCK
37
FS256
39
AOUTL
25
D/A
LPF
CONVERTER
AOUTR
28
R-CH
OSCI
20
X1
OSC
OSCO
22.57MHz
21
4Mbit
D-RAM
XWE
XRAS
XCAS
XOE
53
XWE
57
XRAS
56
XCAS
MONITOR
54
CONTROL
5 6 7 8
X2
18.43MHz
18
19
98
81
80
ATT
7
87
88
53
CHUCKING
LOADING
DETECT
DETECT
ON : When completion
ON : When a disc loading start
of a disc loading
and a disc eject completion
LO_6V
L-CH
A
(PAGE 21)
MECH_ATT
B
(PAGE 21)
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