Pioneer DBR-TF100 Service Manual page 57

5
Transport stream 1 pins
Pin Name Location
a
TSIN1BYTECLK P23
a P26
TSIN1BYTECLKVALID
a
TSIN1ERROR P25
a
TSIN1PACKETCLK P24
a
TSIN1DATA[7:0] b, c
a : 5 V tolerant
b : M26, M25, M24, M23, N26, N25, N24 and N23.
c : TSIN1DATA7 is used for data input in serial mode.
Programmable I/O pins
Pin Name Location
a
PIO0[0:7] b
a
PIO1[0:7] c
PIO2[0:7] a d
a
PIO3[0:7] e
a
PIO4[0:7] f
a
PIO5[0:7] g
a : 5 V tolerant
b : U2, U3, U1, V4, V3, V2, V1 and W4
c : W3, W2, W1, Y3, Y2, Y1, AA4 and AE1
d : AF1, AD2, AE2, AF2, AF3, AD3, AE3 and AD4
e : AE5, AE4, AF5, AF4, AD6, AD15, AD5 and AE15
f : AF15, AD16, AE16, AF16, AC17, AD17, AF18 and AE17
g : AF17, AD18, AE18, AC19, AD19, AE19, AF19 and AD20
a
Digital audio pins
Pin Name Location
b
SCLK AD13
b AE14
PCMDATA[1]
b
PCMCLK AE13
b
LRCLK AF13
b
SPDIF AC15
a : Note: Digital audio input pins PCMI_SCLK, PCMI_DATA and PCMI_LRCLK are alternate functions for NOT_CD_REQ[1],
I1284HOSTLOGICHIGH, and NOT_CD_REQ[0], on PIO port 3 bits [6:4]
b : 5 V tolerant
AVSDRAM pins (SMI)
Pin Name Location
SMIADDR[13:0] a
SMIDATA[15:0] b
NOTSMICS0 V25
NOTSMICS1 V26
NOTSMICAS U23
NOTSMIRAS U24
NOTSMIWE U25
SMIMEMCLKIN T23
SMIMEMCLKOUT U26
SMIDATAML T24
SMIDATAMU T25
a : AC24, AC23, AD26, AD25, AD24, AD23, AE26, AE25, AE24, AE23, AF26, AF25, AF24 and AF23.
b : V24, W26, W25, W24, W23, Y26, Y25, Y24, AA26, AA25, AA24, AB26, AB25, AB24, AC26 and AC25.
5
6
I/O
I Transport stream bit/byte clock
I Transport stream bit/byte clock valid edge
I Transport stream packet error
I Transport stream packet strobe
I Transport stream data in
I/O
I/O
I/O
I/O
Parallel input/output pin or alternative function
I/O
I/O
I/O
I/O
O Serial clock
O PCM data out
I/O External PCM clock input or internal PCM clock output
O Left/right clock
O Digital audio output
I/O
O Audio/video core SDRAM address bus
I/O Audio/video core SDRAM data bus
O Audio/video core SDRAM chip select for 1st SDRAM
O Audio/video core SDRAM chip select for 2nd 16 Mbit SDRAM
O Audio/video core SDRAM column address strobe
O Audio/video core SDRAM row address strobe
O Audio/video core SDRAM write enable
I Audio/video core SDRAM memory clock input
O Audio/video core SDRAM memory clock output
O Audio/video core SDRAM data bus lower byte enable
O Audio/video core SDRAM data bus upper byte enable
DBR-TF100
6
7
Function
Function
Function
Function
7
8
A
B
C
D
E
F
57
8