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JTAG pins
Pin Name
Location
A
a
TDI
AC7
a
TMS
AD7
a
TCK
AF7
a
NOTTRST
AE6
a
TDO
AF6
a : 5 V tolerant
DCU pins
Pin Name
Location
a
DCUTRIGGERIN
P1
a
DCUTRIGGEROUT
R3
B
a : 5 V tolerant
a
EMI pins
Pin Name
Location
b
NOTEMIRAS or NOTCI_IORD
J2
b
NOTEMICAS or NOTCI_IOW
J1
NOTEMICSA
K4
NOTEMICSB
K3
NOTEMICSC
K2
NOTEMICSD
K1
NOTEMICSE
L4
C
NOTEMICSF
L3
NOTEMIBE[1:0]
L1, L2
M1
NOTEMIOE or NOTCI_OE
NOTEMILBA or NOTCI_WEA
N3
EMIWAITNOTTREADY
c
N4
EMIRDNOTWR
N2
EMIDATA[15:0]
d
e
EMIADDR[25:2]
f
NOTEMIREQGNT
J3
c
NOTEMIACKREQ
H1
c
EMIBOOTMODE0
H3
EMISDRAMCLK
A1
D
EMIFLASHCLK
A2
a : The EMI interface has controllable pull-ups, with two independent controls in CONFIG_CONTOL_E[30:29] (EMI_PULLUP_ENABLE_A and
EMI_PULLUP_ENABLE_B)
b : Or equivalent ATA HDD interface signal.
c : 5 V tolerant
d : B3, A3, A4, B4, C4, A5, B5, C5, A6, B6, C6, D6, A7, B7, C7 and A8.
e : EMIADDR[19:20] are used as ATA HDD interface function: ATA CS0 and CS1. There is no interconnect configuration control register bit to
select this function. The addresses are just reused as chip selects.
f : B8, C8, A9, B9, C9, D9, A10, B10, C10, A11, B11, C11, A12, B12, C12, D12, A13, B13, C13, D13, A14, B14, C14 and D14.
Transport stream 2 pins
Pin Name
Location
E
a
TSIN2LBYTECLK
L24
a
L26
TSIN2LBYTECLKVALID
a
TSIN2LERROR
L25
TSIN2LPACKETCLK
a
J25
TSIN2LDATA[7:0]
a
d e
a : 5 V tolerant
b : Input for TSIN2L and TSIN3 (1394).
c : Output as TSIN1 byte clock signal.
d : H25, H24, H23, J26, J24, K26, K25 and K24
e : TSIN2LDATA7 is used for data input in serial mode.
F
56
1
2
I/O
I
Boundary scan test data input
I
Boundary scan test mode select
I
Boundary scan test clock
I
Boundary scan test logic reset
O
Boundary scan test data output
I/O
I
External trigger input to DCU
O
Signal to trigger external debug circuitry
I/O
O
Row address strobe for SDRAM
O
Column address strobe for SDRAM
O
Peripheral chip select A
O
Peripheral chip select B
O
Peripheral chip select C
O
Peripheral chip select D
O
Peripheral chip select E
O
Peripheral chip select F
O
External device data bus byte enable. 1 bit per byte of the data bus.
O
External device output enable.
O
Flash device load burst address.
I
External memory device target ready indicator
O
External read/write access indicator. Common to all devices.
I/O External common data bus.
O
External common address bus
O
Bus request/grant indicator
I
Bus grant/request indicator
I
External power-up port size indicator
O
SDRAM clock
O
Peripheral clock
I/O
I
Transport stream clockb
I/O Transport stream clock valid edge
I/O Transport stream packet errorc
I/O Transport stream packet strobe
I/O Transport stream data
DBR-TF100
2
3
Function
Function
Function
Function
3
4
4
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