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ROM Subsystem
The ROM subsystem has a 32K or 64K by 16-bit arrangement consist-
ing of two 32K by 8-bit ROM/EPROM modules. The odd and even
address codes reside in separate modules. The top of the first
megabyte and the bottom of the last megabyte address space is
assigned to ROM (hex 0F 0000 and hex FF0000). Parity checking is
not done on ROM.
Note: the EPROM speed should be under 200ns.
RAM Subsystem
The RAM subsystem is a 32-bit memory subsystem that starts at
address hex 000000 of the 16M address space. It is a RAM Module
installed on CONl, CON2, CON3 and CON4 plus the optional PEI-366
which is installed on the motherboard. The onboard 32-bit memory and
the 32-bit memory on the PEI-306 allow for the configuration of ex-
tended memory from one to sixteen megabytes. For more information,
refer to the PEI-306 user's manual. Memory refresh forces one
memory cycle every 15 microseconds through channel 1 of the
timer/counter. The following functions are performed by the RAM-in-
itialization program:
• Write operation to any memory location.
• Initialization of channel 1 of the timer/counter to the rate
generation mode (15 microseconds).
Note:
Memory can be used only after being accessed or refreshed eight
times.
Chapter 6: Appendix
23
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