Motherboard Controller; Motherboards And The Cpusets - Sun Microsystems Netra ft 1800 Hardware Reference Manual

2.7

Motherboard Controller

The motherboard controller provides the following registers:
Determination of which CPUset is the primary (including during recovery from
EState)
Recording of most recent reason for reset:
remote, requested by the RCP
OSdog
synchronization
clock
Mailbox interruptor
Power status
PLL lock status
PCI slot IRQ concentrator.
2.8

Motherboards and the CPUsets

Each PCI bridge on the motherboard takes in one PCI bus from each of the two
CPUsets. These are compared and buffered in the PCI bridge, and produce a single
output PCI bus which serves the four I/O slots of the hotPCI bus. The PCI
comparator tolerates input from the CPUset on the other side when the comparator
power is off, and never drives current into a CPUset which is switched off.
There are two bridges on each motherboard, comparing four (two from each side)
CPUset buses and producing two hotPCI buses on each side.
Each hotPCI slot is isolated by FETs from the motherboard bus. This allows cold PCI
cards to be used in the hotPCI slot with an adapter. Power is also switched to the
PCI cards under software control. At power on, the hotPCI slots are all switched off,
and software enables them.
The PCI bridge logic allows CPUsets to access each others' address space. A mailbox
facility is provided to allow one side to generate interrupts to the other side.
Both CPUsets are 'active' when running in fault tolerant configuration. All signals
are compared on the bridges when appropriate.
Chapter 2 Motherboards 2-13