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2-1. IC PIN DESCRIPTIONS
• IC801 µPC78074 (SYSTEM CONTROL)
Pin No.
Pin Name
1
KEY-REQ
2 – 4
—
5
LCD-ON
6
LCD1-CE
7
LCD1-DATA
8
LCD1-CLK
9
IC
10
X2
11
X1
12
VDD
13
XT2
14
XT1
15
RESET
16
S-REMOTE
17
B/U-DOWN
18
S-CONTACT
19
KLINE/TEL
20
ON-KEY
21
TIM/EJ-IN
22
LCD2-ENI
23
AVDD
24
AVREF0
25
+B-AD
26
AD-ILL-DUTY
27
AD-SP-FL-OPEN
28
AD-SP-FR-OPEN
29
AD-SP-RL-OPEN
30
AD-SP-RR-OPEN
31
VDD-P-ON
32
P-ON
33
AVSS
34
BEEP DA
35
DSP-PD
36
AVREF1
37
K-LINE (RX)
38
K-LINE (TX)
39
TEL-MUTE
40
VSS
41
LCD2-ENO
42
LCD2-DATA-OUT
43
LCD2-CLK
44
DSP-CS
45
DSP-WRDY
46
DSP-DATA-IN
47
DSP-DATA-OUT
48
DSP-SCLK
49
DSP-DRDY
50
DSP-WRQ
51
DSP-RST
52
EV-DATA-R
53
EV-CLK
SECTION 2
DIAGRAMS
I/O
I
Key request input (L: Key request)
O
Not used in this set.
O
LCD control output (H: LCD display ON)
O
LCD chip enable output (L: Chip enable ON)
I/O
LCD data input/output (Input: When key data read)
O
LCD clock output
—
Ground
—
Main clock (X' tal 4.9152 MHz)
I
Main clock input (X' tal 4.9152 MHz)
—
Not used in this set.
—
Sub clock (Open)
I
Sub clock (Pulled-up to VDD.)
I
System reset input (L: When back-up 5 V fail)
I
Steering remote commander interrupt input
I
+B check interrupt input (L: +B normal, H: +B low or high)
I
S-contact interrupt input (L: Interrupt request)
I
TEL/K-line interrupt input (L: Interrupt request)
I
"ON" key interrupt input (L: Interrupt request)
I
"TIM/EJECT" key interrupt input (L: Interrupt request)
I
2nd display chip enable interrupt input (L: Interrupt request)
—
Analog power supply pin (+5 V)
—
Analog reference voltage 0
I
+B voltage sense AD input (Low V: > 0.6 V, High V: > 2.2 V)
I
Illumi., dimmer voltage AD input (Converted PWM to voltage.)
I
Front Ieft speaker open detect input (AD)
I
Front right speaker open detect input (AD)
I
Rear left speaker open detect input (AD)
I
Rear right speaker open detect input (AD)
O
Switched 5 V power control output (L: Under sleep mode)
O
Main power control output (H: Power on)
—
Analog ground
O
Beep wave DA output
O
DSP power down control output (L: Power down)
—
Analog reference voltage 1
I
K-line receive data input (9600 bps)
O
K-line transmit data output (9600 bps)
I
Telephone mute input (L: Telephone mute request)
—
Ground
O
2nd display chip enable line control output (H: Chip enable line activate)
O
2nd display data output
O
2nd display clock output
O
DSP chip select output
I
DSP write ready input
I
DSP data input (SI)
O
DSP data output (SO)
O
DSP data clock output
I
DSP data ready input
O
DSP write request output
O
DSP reset output (L: Reset & power down)
O
Electric volume data output (Rear)
O
Electric volume clock output
– 6 –
Pin Description
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