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82563EB/82564EB LAN on Motherboard Design Guide
For Intel® Ethernet controllers, it is acceptable to overdrive the internal inverter by connecting a
25 MHz external oscillator to the XTAL1 lead, leaving the XTAL2 lead unconnected. The
oscillator should be specified to drive CMOS logic levels, and the clock trace to the device should
be as short as possible. Device specifications typically call for a 40% (minimum) to 60%
(maximum) duty cycle and a ±50 ppm frequency tolerance.
Note: Please contact your Intel Customer Representative to obtain the most current device documentation
prior to implementing this solution.
4.4
Programmable Crystal Oscillators
A programmable oscillator can be configured to operate at many frequencies. The device contains
a crystal frequency reference and a phase lock loop (PLL) clock generator. The frequency
multipliers and divisors are controlled by programmable fuses.
A programmable oscillator's accuracy depends heavily on the Ethernet device's differential
transmit lines. The Physical Layer (PHY) uses the clock input from the device to drive a
differential Manchester (for 10 Mbps operation), an MLT-3 (for 100 Mbps operation) or a PAM-5
(for 1000 Mbps operation) encoded analog signal across the twisted pair cable. These signals are
referred to as self-clocking, which means the clock must be recovered at the receiving link partner.
Clock recovery is performed with another PLL that locks onto the signal at the other end.
PLLs are prone to exhibit frequency jitter. The transmitted signal can also have considerable jitter
even with the programmable oscillator working within its specified frequency tolerance. PLLs
must be designed carefully to lock onto signals over a reasonable frequency range. If the
transmitted signal has high jitter and the receiver's PLL loses its lock, then bit errors or link loss
can occur.
PHY devices are deployed for many different communication applications. Some PHYs contain
PLLs with marginal lock range and cannot tolerate the jitter inherent in data transmission clocked
with a programmable oscillator. The American National Standards Institute (ANSI) X3.263-1995
standard test method for transmit jitter is not stringent enough to predict PLL-to-PLL lock failures,
therefore, the use of programmable oscillators is generally not recommended.
4.5
Ceramic Resonator
Similar to a quartz crystal, a ceramic resonator is a piezoelectric device. A ceramic resonator
typically carries a frequency tolerance of ±0.5%, – inadequate for use with Intel® Ethernet
controllers, and therefore, should not be utilized.
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