Board Layout And Placement Checklist - Intel 82563EB Design Manual

82563EB/82564EB LAN on Motherboard Design Guide
10.2

Board Layout and Placement Checklist

SECTION
General Have up-to-date product documentation and
spec updates.
Route the Kumeran and MDI differential traces
before routing the digital traces.
Ethernet Device Place the silicon at least 1 inch from the edge of
the board.
Place PHY_REF compensation resistor less
than 1 inch from the silicon.
Place the PHY_CLK_OUT series resistor within
2 inches of the 82563EB/82564EB.
Route the serial clock as a 50 Ω single-ended
impedance (± 20%).
Clock Source Place crystal and load capacitors less than 0.75
inches from Ethernet device.
Keep clock lines 15 mils away from other
signals.
Crystal traces are 12 mil width.
Design traces for 100 Ω differential impedance
MDI Differential
Pairs (± 20%).
Place the silicon at least 1 inch from the
integrated magnetics module but less than 4
inches.
50
CHECK ITEMS REMARKS
Documents are subject to frequent change.
Layout of differential traces is critical.
With closer spacing, the strongest fields do not
have path to GND and may cause EMI problems.
Use PHY_CLK_OUT only if the routed length
between the 82563EB/82564EB and the 631xESB/
632xESB is less than 15 inches. The 40 Ω series
resistor is required for signal integrity.
If the routed length between 82563EB/82564EB
and the 631xESB/632xESB is greater than 15
inches, then PHY_CLK_OUT must be a no
connect. Instead, use an oscillator clock source at
the 631xESB/632xESB.
Controlled impedance is required to reduce ringing
and improve signal quality at the 50 Ω input to the
631xESB/632xESB.
Keep 15 mil spacing to digital traces, I/O ports, and
board edge. More spacing may be required to
other high speed traces or clocks.
The Ethernet clock plays a key role in EMI.
This includes spacing to other digital traces, I/O
ports, board edge, transformers and differential
pairs.
12 mil width is the best compromise of low
inductance and low capacitance.
Primary requirement for 10/100/1000 Mb/s
Ethernet. Paired 50 Ω traces do not make 100 Ω
differential. Check impedance calculator.
With closer spacing, fields can follow the surface of
the magnetics module or wrap past edge of board,
increasing EMI. If the board does not have power
and ground planes along the edge, the problem
could be worse.
Larger spacing increases the insertion loss of the
MDI signals and decreases amplitude which may
cause IEEE failures.
Optimum location is approximately 1 inch behind
the magnetics module.