ST ST7LITEUS2 Quick Start Manual
ST ST7LITEUS2 Quick Start Manual

ST ST7LITEUS2 Quick Start Manual

8-bit mcu with single voltage flash memory, adc, timers
Table of Contents

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8-bit MCU with single voltage Flash memory, ADC, timers
Features
Memories
– 1 Kbytes single-voltage Flash Program
memory with readout protection, ICP and
IAP)
10 K write/erase cycles guaranteed
data retention: 20 years at 55 °C
– 128 bytes RAM
Clock, Reset and Supply management
– 3-level low-voltage supervisor (LVD) and
auxiliary voltage detector (AVD) for safe
power-on/off
– Clock sources: internal trimmable 8 MHz
RC oscillator, internal low power, low
frequency RC oscillator or external clock
– Five power saving modes: Halt, Auto-
wakeup from Halt, Active-halt, Wait, Slow
Interrupt management
– 11 interrupt vectors plus TRAP and RESET
– 5 external interrupt lines (on 5 vectors)
I/O ports
– 5 multifunctional bidirectional I/O lines
– 1 additional Output line
– 6 alternate function lines
– 5 high sink outputs
Table 1.
Device summary
Features
Program memory
RAM (stack)
Peripherals
ADC
Operating Supply
CPU Frequency
Operating Temperature
Packages
1. For development or tool prototyping purposes only. Not orderable in production quantities.
February 2009
Plastic DIP8
2 Timers
– One 8-bit Lite timer (LT) with prescaler
– One 12-bit auto-reload timer (AT) with
A/D Converter
– 10-bit resolution for 0 to V
– 5 input channels
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
– 17 main addressing modes
– 8x8 unsigned multiply instruction
Development Tools
– Full hardware/software development
– Debug module
ST7LITEUS2
128 (64) bytes
LT Timer w/ Wdg, AT Timer w/ 1 PWM
-
2.4 to 3.3 V @f
=4 MHz, 3.3 to 5.5 V @f
CPU
up to 8 MHz RC
-40 to +85 °C / -40 to 125 °C
SO8 150", Pastic DIP8, DFN8, Pastic DIP16
Rev 5
ST7LITEUS2
ST7LITEUS5
SO8
150"
including: watchdog, one realtime base and
one 8-bit input capture.
output compare function and PWM
detection
package
ST7LITEUS5
1 Kbytes
10-bit
=8 MHz
CPU
(1)
Plastic DIP16
DFN8
DD
1/136
www.st.com
1

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Summary of Contents for ST ST7LITEUS2

  • Page 1: Table 1. Device Summary

    ST7LITEUS2 ST7LITEUS5 8-bit MCU with single voltage Flash memory, ADC, timers Features ■ Memories – 1 Kbytes single-voltage Flash Program memory with readout protection, ICP and Plastic DIP8 Plastic DIP16 DFN8 150” IAP) 10 K write/erase cycles guaranteed ■ 2 Timers data retention: 20 years at 55 °C...
  • Page 2: Table Of Contents

    Contents ST7LITEUS2, ST7LITEUS5 Contents Introduction ..........11 Pin description .
  • Page 3 ST7LITEUS2, ST7LITEUS5 Contents Register description ......... 30 6.3.1...
  • Page 4 Contents ST7LITEUS2, ST7LITEUS5 8.5.1 Register description ........57 I/O ports .
  • Page 5 ST7LITEUS2, ST7LITEUS5 Contents Instruction set ..........84 11.1...
  • Page 6 Contents ST7LITEUS2, ST7LITEUS5 12.8.1 General characteristics ........108 12.8.2...
  • Page 7 ST7LITEUS2, ST7LITEUS5 List of tables List of tables Table 1. Device summary ............1 Table 2.
  • Page 8 List of tables ST7LITEUS2, ST7LITEUS5 Table 49. Voltage drop between AVD flag set and LVD reset generation ..... 96 Table 50.
  • Page 9 ST7LITEUS2, ST7LITEUS5 List of figures List of figures Figure 1. General block diagram ........... . 11 Figure 2.
  • Page 10 List of figures ST7LITEUS2, ST7LITEUS5 Figure 48. Two typical applications with unused I/O pin ........108 Figure 49.
  • Page 11: Introduction

    The ST7LITEUS2 and ST7LITEUS5 feature FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7LITEUS2 and ST7LITEUS5 can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.
  • Page 12: Pin Description

    Pin description ST7LITEUS2, ST7LITEUS5 Pin description Figure 2. 8-pin SO and Plastic DIP package pinout PA5 (HS) / AIN4 / CLKIN PA0 (HS) / AIN0 / ATPWM / ICCDATA PA4 (HS) / AIN3/MCO PA1 (HS) / AIN1 / ICCCLK PA3 / RESET PA2 (HS) / LTIC / AIN2 HS: High sink capability.
  • Page 13: Figure 4. 16-Pin Package Pinout

    ST7LITEUS2, ST7LITEUS5 Pin description Figure 4. 16-pin package pinout Reserved RESET PA0 (HS) / AIN0 / ATPWM ICCCLK PA1 (HS) / AIN1 PA5 (HS) / AIN4 / CLKIN ICCDATA PA4 (HS) / AIN3/MCO PA2 (HS) / LTIC / AIN2 1. Reserved pins must be tied to ground.
  • Page 14: Table 2. Device Pin Description

    Pin description ST7LITEUS2, ST7LITEUS5 Legend/abbreviations for Table 2 Type: I = input, O = output, S = supply In/Output level: C = CMOS 0.3 V /0.7 V with input trigger Output level: HS = High sink (on N-buffer only) Port and control configuration ●...
  • Page 15: Register And Memory Map

    ST7LITEUS2, ST7LITEUS5 Register and memory map Register and memory map As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory.
  • Page 16: Table 3. Hardware Register Map

    Register and memory map ST7LITEUS2, ST7LITEUS5 Table 3. Hardware register map Register Address Block Register name Reset status Remarks label 0000h PADR Port A Data register 0001h Port A PADDR Port A Data Direction register 0002h PAOR Port A Option register...
  • Page 17 ST7LITEUS2, ST7LITEUS5 Register and memory map Table 3. Hardware register map (continued) Register Address Block Register name Reset status Remarks label 0049h AWUPR AWU Prescaler register 004Ah AWUCSR AWU Control/Status register 004Bh DMCR DM Control register 004Ch DMSR DM Status register...
  • Page 18: Flash Program Memory

    Flash program memory ST7LITEUS2, ST7LITEUS5 Flash program memory Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming.
  • Page 19: In Application Programming (Iap)

    The use of Pin 7 of the I C connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.
  • Page 20: Memory Protection

    Flash program memory ST7LITEUS2, ST7LITEUS5 Pin 9 has to be connected to the CLKIN pin of the ST7 when I C mode is selected with option bytes disabled (35-pulse I C entry mode). When option bytes are enabled (38-pulse C entry mode), the internal RC clock (internal RC or AWU RC) is forced. If internal RC is selected in the option byte, the internal RC is provided.
  • Page 21: Flash Write/Erase Protection

    ST7LITEUS2, ST7LITEUS5 Flash program memory In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. Readout protection selection depends on the device type: ● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
  • Page 22: Register Description

    Flash program memory ST7LITEUS2, ST7LITEUS5 Register description 4.7.1 Flash Control/Status register (FCSR) This register controls the XFlash erasing and programming using ICP, IAP or other programming methods. 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
  • Page 23: Central Processing Unit

    ST7LITEUS2, ST7LITEUS5 Central processing unit Central processing unit Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ●...
  • Page 24: Condition Code Register (Cc)

    Central processing unit ST7LITEUS2, ST7LITEUS5 Figure 7. CPU registers ACCUMULATOR RESET VALUE = XXh X INDEX REGISTER RESET VALUE = XXh Y INDEX REGISTER RESET VALUE = XXh PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 1 1 H I...
  • Page 25 ST7LITEUS2, ST7LITEUS5 Central processing unit Bit 7:5 Set to ‘1’ Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
  • Page 26: Stack Pointer (Sp)

    Central processing unit ST7LITEUS2, ST7LITEUS5 5.3.5 Stack Pointer (SP) Reset value: 00 FFh Read/write Read/write The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented...
  • Page 27: Figure 8. Stack Manipulation Example

    ST7LITEUS2, ST7LITEUS5 Central processing unit Figure 8. Stack manipulation example CALL PUSH Y POP Y IRET Interrupt subroutine or RSP event @ 00C0h @ 00FFh 1. Stack higher address = 00FFh. 2. Stack lower address = 00C0h. 27/136...
  • Page 28: Supply, Reset And Clock Management

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.
  • Page 29 Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal. The ST7LITEUS2 and ST7LITEUS5 also contain an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter Auto-wakeup from Halt mode.
  • Page 30: Register Description

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 Figure 9. Clock switching Set RC/AWU Internal RC AWU RC Poll AWU_FLAG until set Reset RC/AWU AWU RC Internal RC Poll RC_FLAG until set Register description 6.3.1 Main Clock Control/Status register (MCCSR) Reset value: 0000 0000 (00h) Read / Write Bits 7:2 Reserved, must be kept cleared.
  • Page 31: Rc Control Register (Rccr)

    ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management 6.3.2 RC Control register (RCCR) Reset value: 1111 1111 (FFh) Read / Write Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy.
  • Page 32: Avd Threshold Selection Register (Avdthcr)

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 6.3.4 AVD Threshold Selection register (AVDTHCR) Reset value: 0000 0011 (03h) AVD1 AVD0 Read / Write Bits 7:5 CK[2:0] Internal RC Prescaler Selection These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the internal RC oscillator.
  • Page 33: Table 7. Clock Register Map And Reset Values

    ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management Bit 2 RC_FLAG RC Selection This bit is set and cleared by hardware 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared.
  • Page 34: Figure 10. Clock Management Block Diagram

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 Figure 10. Clock management block diagram RCCR SICSR Tunable internal RC Oscillator CKCNTCSR RC/AWU Clock 8MHz(f Controller RC OSC AWU CK 8 MHz Ext Clock 4 MHz Prescaler 2 MHz 1 MHz 500 kHz...
  • Page 35: Reset Sequence Manager (Rsm)

    ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management Reset sequence manager (RSM) 6.4.1 Introduction The reset sequence manager includes three reset sources as shown in Figure ● External RESET source pulse ● Internal LVD reset (low voltage detection) ● Internal WATCHDOG reset Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
  • Page 36: Asynchronous External Reset Pin

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 Figure 12. Reset block diagram INTERNAL RESET FILTER RESET WATCHDOG RESET PULSE ILLEGAL OPCODE RESET GENERATOR LVD RESET Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions 6.4.2 Asynchronous external RESET pin...
  • Page 37: Internal Watchdog Reset

    ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management 6.4.5 Internal watchdog reset The reset sequence generated by a internal watchdog counter overflow is shown in Figure Starting from the watchdog counter underflow, the device RESET pin acts as an output that...
  • Page 38: Table 8. Multiplexed Io Register Map And Reset Values

    Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
  • Page 39: Interrupts

    ST7LITEUS2, ST7LITEUS5 Interrupts Interrupts The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
  • Page 40: External Interrupts

    Interrupts ST7LITEUS2, ST7LITEUS5 External interrupts External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.
  • Page 41: External Interrupt Control Register 1 (Eicr1)

    ST7LITEUS2, ST7LITEUS5 Interrupts Table 9. Interrupt mapping Exit Register Priority Address N° Source block Description from label order vector Halt RESET Reset FFFEh-FFFFh TRAP Software interrupt FFFCh-FFFDh Auto-wakeup interrupt AWUCSR FFFAh-FFFBh External interrupt 0 FFF8h-FFF9h Highest priority External interrupt 1...
  • Page 42: External Interrupt Control Register 2 (Eicr2)

    Interrupts ST7LITEUS2, ST7LITEUS5 Note: These 8 bits can be written only when the I bit in the CC register is set. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function.
  • Page 43: System Integrity Management (Si)

    ST7LITEUS2, ST7LITEUS5 Interrupts System integrity management (SI) The System Integrity Management block contains the low voltage detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
  • Page 44: Figure 15. Low Voltage Detector Vs Reset

    Interrupts ST7LITEUS2, ST7LITEUS5 Figure 15. Low voltage detector vs reset (LVD) (LVD) RESET Figure 16. Reset and supply management block diagram WATCHDOG STATUS FLAG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE AVD Interrupt Request RESET MANAGER SICSR (RSM) LOW VOLTAGE...
  • Page 45: Auxiliary Voltage Detector (Avd)

    ST7LITEUS2, ST7LITEUS5 Interrupts 7.4.2 Auxiliary voltage detector (AVD) The voltage detector function (AVD) is based on an analog comparison between a V IT-(AVD) and V reference value and the V main supply voltage (V ). The V IT+(AVD) IT-(AVD) reference value for falling voltage is lower than the V...
  • Page 46: Low Power Modes

    Interrupts ST7LITEUS2, ST7LITEUS5 7.4.3 Low power modes Table 11. Description of low power modes Mode Description Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. Halt The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
  • Page 47: Table 13. System Integrity Register Map And Reset Values

    ST7LITEUS2, ST7LITEUS5 Interrupts Bit 2 LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared when read. See WDGRF flag description in Section 10.1.6 on page 69 for more details.
  • Page 48: Power Saving Modes

    Power saving modes ST7LITEUS2, ST7LITEUS5 Power saving modes Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): ● Slow ●...
  • Page 49: Slow Mode

    ST7LITEUS2, ST7LITEUS5 Power saving modes Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (f ) to the available supply voltage. Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode.
  • Page 50: Active-Halt And Halt Modes

    Power saving modes ST7LITEUS2, ST7LITEUS5 Figure 20. Wait mode flowchart OSCILLATOR PERIPHERALS WFI INSTRUCTION I BIT RESET INTERRUPT OSCILLATOR PERIPHERALS I BIT 64 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I BIT FETCH RESET VECTOR OR SERVICE INTERRUPT 1. 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
  • Page 51: Active-Halt Mode

    ST7LITEUS2, ST7LITEUS5 Power saving modes 8.4.1 Active-halt mode Active-halt mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled. The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a reset.
  • Page 52: Halt Mode

    Power saving modes ST7LITEUS2, ST7LITEUS5 Figure 22. Active-halt mode flowchart OSCILLATOR PERIPHERALS HALT INSTRUCTION (Active-halt enabled) I BIT RESET INTERRUPT OSCILLATOR PERIPHERALS I BIT 64 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I BITS FETCH RESET VECTOR OR SERVICE INTERRUPT 1. This delay occurs only if the MCU exits Active-halt mode by means of a reset.
  • Page 53: Figure 23. Halt Timing Overview

    ST7LITEUS2, ST7LITEUS5 Power saving modes Figure 23. Halt timing overview 64 CPU CYCLE Halt DELAY RESET INTERRUPT HALT INSTRUCTION FETCH [Active-halt disabled] VECTOR 1. A reset pulse of at least 42µs must be applied when exiting from Halt mode. Figure 24. Halt mode flowchart...
  • Page 54: Auto-Wakeup From Halt Mode

    Power saving modes ST7LITEUS2, ST7LITEUS5 Halt mode recommendations ● Make sure that an external event is available to wakeup the microcontroller from Halt mode. ● When using an external interrupt to wakeup the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction.
  • Page 55: Figure 26. Awuf Halt Timing Diagram

    ST7LITEUS2, ST7LITEUS5 Power saving modes After this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f and then calculating the right prescaler value.
  • Page 56: Figure 27. Awufh Mode Flowchart

    Power saving modes ST7LITEUS2, ST7LITEUS5 Figure 27. AWUFH mode flowchart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WATCHDOG DISABLE WDGHALT AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS I[1:0] BITS RESET INTERRUPT AWU RC OSC MAIN OSC PERIPHERALS I[1:0] BITS 64 CPU CLOCK...
  • Page 57: Register Description

    ST7LITEUS2, ST7LITEUS5 Power saving modes 8.5.1 Register description AWUFH Control/ Status register (AWUCSR) Reset value: 0000 0000 (00h) AWUM AWUEN Read/Write Bits 7:3 Reserved Bit 2 AWUF Auto-wakeup Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR.
  • Page 58: Table 15. Configuring The Dividing Factor

    Power saving modes ST7LITEUS2, ST7LITEUS5 Table 15. Configuring the dividing factor AWUPR[7:0 Dividing factor Forbidden In AWU mode, the period that the MCU stays in Halt Mode (t Figure 26) is defined by × × t AWU 64 AWUPR ------------------------- -...
  • Page 59: I/O Ports

    ST7LITEUS2, ST7LITEUS5 I/O ports I/O ports Introduction The I/O port offers different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins: ● External interrupt generation ● Alternate signal input/output for the on-chip peripherals. An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output.
  • Page 60: Output Modes

    I/O ports ST7LITEUS2, ST7LITEUS5 Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.
  • Page 61: Alternate Functions

    ST7LITEUS2, ST7LITEUS5 I/O ports 9.2.3 Alternate functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions: ● When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).
  • Page 62: Table 18. I/O Port Mode Options

    I/O ports ST7LITEUS2, ST7LITEUS5 Table 18. I/O port mode options Diodes Configuration mode Pull-up P-buffer to V to V Floating with/without Interrupt Input Pull-up with/without Interrupt Push-pull Output Open Drain (logic level) 1. NI stands for not implemented; Off for implemented not activated; On for implemented and activated.
  • Page 63: Unused I/O Pins

    ST7LITEUS2, ST7LITEUS5 I/O ports Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
  • Page 64: I/O Port Implementation

    I/O ports ST7LITEUS2, ST7LITEUS5 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects.
  • Page 65: On-Chip Peripherals

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals On-chip peripherals 10.1 Lite timer (LT) 10.1.1 Introduction The Lite Timer can be used for general-purpose timing functions. It is based on a free- running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function.
  • Page 66: Functional Description

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 Figure 30. Lite timer block diagram LTIMER To 12-bit AT TImer WATCHDOG WATCHDOG RESET Timebase 1 or 2 ms 13-bit UPCOUNTER (@ 8MHz LTIMER LTICR 8 MSB 8-bit LTIC INPUT CAPTURE REGISTER LTCSR ICIE TBIE WDGE...
  • Page 67: Figure 31. Watchdog Timing Diagram

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set.
  • Page 68: Low Power Modes

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 10.1.4 Low power modes Table 24. Description of low power modes Mode Description Wait No effect on Lite timer Active-Halt No effect on Lite timer Halt Lite timer stops counting 10.1.5 Interrupts Table 25. Interrupt events...
  • Page 69: Register Description

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals 10.1.6 Register description Lite timer control/status register (LTCSR) Reset value: 0000 0x00 (0xh) ICIE TBIE WDGR WDGE WDGD Read / Write Bit 7 ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 ICF Input Capture Flag.
  • Page 70: Table 26. Lite Timer Register Map And Reset Values

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 Bit 2 WDGRF Force Reset/ Reset Status Flag This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software.
  • Page 71: 12-Bit Auto-Reload Timer (At)

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals 10.2 12-bit auto-reload timer (AT) 10.2.1 Introduction The 12-bit auto-reload timer can be used for general-purpose timing functions. It is based on a free-running 12-bit upcounter with a PWM output channel. 10.2.2 Main features ● 12-bit upcounter with 12-bit auto-reload register (ATR) ●...
  • Page 72: Figure 34. Pwm Function

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 PWM frequency and duty cycle The PWM signal frequency (f ) is controlled by the counter period and the ATR register value. / (4096 - ATR) COUNTER Following the above formula, if f is 8 MHz, the maximum value of f is 4 MHz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
  • Page 73: Low Power Modes

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals Figure 35. PWM signal example COUNTER ATR= FFDh COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCR0=FFEh Output compare mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register.
  • Page 74: Interrupts

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 10.2.5 Interrupts Table 28. Interrupt events Enable Exit Exit Exit Event Interrupt event control from from from flag Wait Halt Active-halt Overflow event OVFIE CMP event CMPFx CMPIE 1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
  • Page 75: Table 29. Counter Clock Selection

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals Table 29. Counter clock selection Counter clock selection (1 ms timebase @ 8 MHz) LTIMER Reserved Counter register high (CNTRH) Reset value: 0000 0000 (00h) CN11 CN10 Read only Counter register low (CNTRL) This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected.
  • Page 76 On-chip peripherals ST7LITEUS2, ST7LITEUS5 Auto reload register (ATRL) This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency.
  • Page 77: Table 30. Register Map And Reset Values

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals PWM0 control/status register (PWM0CSR) Reset value: 0000 0000 (00h) CMPF0 Read/Write Bit 7:2 Reserved, must be kept cleared. Bit 1 OP0 PWM0 output polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal.
  • Page 78 On-chip peripherals ST7LITEUS2, ST7LITEUS5 Table 30. Register map and reset values (continued) Address Register label (Hex.) ATRL ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Reset value PWMCR Reset value PWM0CSR CMPF0 Reset value DCR0H DCR11 DCR10 DCR9 DCR8 Reset value...
  • Page 79: 10-Bit A/D Converter (Adc)

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals 10.3 10-bit A/D converter (ADC) 10.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources.
  • Page 80: Figure 36. Adc Block Diagram

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 Figure 36. ADC block diagram DIV 4 DIV 2 SLOW ADCCSR EOC SPEED ADON AIN0 HOLD CONTROL AIN1 ANALOG TO DIGITAL ANALOG CONVERTER AINx ADCDRH ADCDRL SLOW Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.
  • Page 81: Low Power Modes

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals cycles) and the C sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. ● The total conversion time: CONV = SAMPLE HOLD While the ADC is on, these two phases are continuously repeated.
  • Page 82: Interrupts

    On-chip peripherals ST7LITEUS2, ST7LITEUS5 10.3.5 Interrupts None. 10.3.6 Register description Control/Status register (ADCCSR) Reset value: 0000 0000 (00h) SPEED ADON Read/Write (Except bit 7 read only) Bit 7 EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register.
  • Page 83: Table 33. Configuring The Adc Clock Speed

    ST7LITEUS2, ST7LITEUS5 On-chip peripherals ADC data register high (ADCDRH) Reset value: 0000 0000 (00h) Read only Bits 7:0 D[9:2] MSB of Analog Converted value ADC control/data register Low (ADCDRL) Reset value: 0000 0000 (00h) SLOW Read/write Bits 7:4 Reserved. Forced by hardware to 0.
  • Page 84: Instruction Set

    Instruction set ST7LITEUS2, ST7LITEUS5 Instruction set 11.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Table 35. Description of addressing modes Addressing mode Example Inherent Immediate ld A,#$55 Direct...
  • Page 85: Inherent Mode

    ST7LITEUS2, ST7LITEUS5 Instruction set Table 36. ST7 addressing mode overview (continued) Destination/ Pointer Pointer Length Mode Syntax source address size (bytes) Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word Relative Direct jrne loop PC-128/PC+127 Relative Indirect jrne [$10] PC-128/PC+127 00..FF...
  • Page 86: Immediate

    Instruction set ST7LITEUS2, ST7LITEUS5 11.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Table 38. Instructions supporting inherent immediate addressing mode Immediate instruction Function Load Compare Bit compare AND, OR, XOR...
  • Page 87: Indirect Modes (Short, Long)

    ST7LITEUS2, ST7LITEUS5 Instruction set 11.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two...
  • Page 88: Relative Modes (Direct, Indirect)

    Instruction set ST7LITEUS2, ST7LITEUS5 Table 39. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Instructions Function CPL, NEG 1 or 2 complement BSET, BRES Bit operations BTJT, BTJF Bit test and jump operations SLL, SRL, SRA, RLC, RRC...
  • Page 89: Illegal Opcode Reset

    ST7LITEUS2, ST7LITEUS5 Instruction set Table 41. ST7 instruction set (continued) Shift and rotates SWAP Unconditional jump or call CALL CALLR NOP RET Conditional branch JRxx Interruption management TRAP HALT IRET Condition code flag modification Using a prebyte The instructions are described with 1 to 4 bytes.
  • Page 90 Instruction set ST7LITEUS2, ST7LITEUS5 Table 42. Illegal opcode detection (continued) Mnemo Description Function/example BRES Bit Reset bres Byte, #3 BSET Bit Set bset Byte, #3 BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 BTJT Jump if bit is true (1)
  • Page 91 ST7LITEUS2, ST7LITEUS5 Instruction set Table 42. Illegal opcode detection (continued) Mnemo Description Function/example Negate (2's compl) neg $10 reg, M No operation OR operation A = A + M Pop from the stack pop reg pop CC PUSH Push onto the stack...
  • Page 92: Electrical Characteristics

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T =25 °C and T...
  • Page 93: Pin Input Voltage

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure Figure 38. Pin input voltage ST7 PIN 12.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device.
  • Page 94: Operating Conditions

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Table 44. Current characteristics Symbol Ratings Maximum value Unit Total current into V power lines (source) Total current out of V ground lines (sink) Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin...
  • Page 95: Operating Conditions With Low Voltage Detector (Lvd)

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 39. f maximum operating frequency versus V supply voltage FUNCTIONALITY GUARANTEED [MHz] IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) FUNCTIONALITY NOT GUARANTEED IN THIS AREA SUPPLY VOLTAGE [V] 12.3.2 Operating conditions with low voltage detector (LVD) = -40 to 125 °C, unless otherwise specified...
  • Page 96: Auxiliary Voltage Detector (Avd) Thresholds

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 12.3.3 Auxiliary voltage detector (AVD) thresholds = −40 to 125°C, unless otherwise specified. Table 48. Operating characteristics with AVD Symbol Parameter Conditions Unit High threshold 1 => 0 AVDF flag toggle threshold Med. threshold (AVD) rise)
  • Page 97: Table 50. Internal Rc Oscillator Characteristics (5.0 V Calibration)

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Table 50. Internal RC oscillator characteristics (5.0 V calibration) Symbol Parameter Conditions Unit RCCR = FF (reset value), = 25 °C, V = 5 V Internal RC oscillator frequency RCCR = RCCR0 = 25 °C, V = 5 V = 25 °C, V...
  • Page 98: Figure 40. Typical Accuracy With Rccr=Rccr0 Vs Vdd= 2.4-6.0 V And Temperature

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Figure 40. Typical accuracy with RCCR=RCCR0 vs V = 2.4-6.0 V and temperature -0.2 -0.4 -0.6 -0.8 -1.0 RC5V@-45C -1.2 RC5V@25C -1.4 RC5V@90C -1.6 RC5V@130C -1.8 RC5V@0C -2.0 -2.2 Figure 41. Typical accuracy with RCCR=RCCR1 vs V = 2.4-6.0V and temperature...
  • Page 99: Supply Current Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics 12.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped).
  • Page 100: Internal Rc Oscillator Supply Current Characteristics

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 12.4.2 Internal RC oscillator supply current characteristics Table 53. Internal RC oscillator supply current Symbol Parameter Conditions Unit =25 °C, int RC = 4 MHz Supply current in Run mode =25 °C, int RC = 8 MHz =25 °C, AWU RC...
  • Page 101: Figure 42. Typical Idd In Run Mode Vs. Internal Clock Frequency And Vdd

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 42. Typical I in run mode vs. internal clock frequency and V Idd RUN m ode @ am b vs int clock freq RC 8 M Hz RC 4 M Hz 6.00 RC 2 M Hz AW U 5.00...
  • Page 102: Figure 45. Idd Vs Temp @Vdd 5 V & Int Rc = 8 Mhz

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Figure 45. I vs temp @V 5 V & int RC = 8 MHz slow slowwait acthlt Temp [°C] Figure 46. I vs temp @V 5 V & int RC = 4 MHz Figure 47. I vs temp @V 5 V &...
  • Page 103: On-Chip Peripherals

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics 12.4.3 On-chip peripherals Table 54. On-chip peripheral characteristics Symbol Parameter Conditions Unit = 3.0 V = 4 MHz V 12-bit auto-reload timer supply current DD(AT) = 5.0 V = 8 MHz V μA = 3.0 V...
  • Page 104: Memory Characteristics

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 12.6 Memory characteristics = -40 to 125 °C, unless otherwise specified; Table 57. RAM and Hardware registers Symbol Parameter Conditions Unit Data retention mode Halt mode (or Reset) Table 58. Flash Program memory Symbol Parameter Conditions...
  • Page 105: Emc Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics 12.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
  • Page 106: Electromagnetic Interference (Emi)

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 12.7.2 Electromagnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
  • Page 107: Table 62. Electrical Sensitivities

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
  • Page 108: I/O Port Pin Characteristics

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 12.8 I/O port pin characteristics 12.8.1 General characteristics Subject to general operating conditions for V , and T unless otherwise specified. Table 63. General characteristics Symbol Parameter Conditions Unit Input low level voltage 0.3V -40°C to 125°C Input high level voltage 0.7V...
  • Page 109: Output Driving Current Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 49. Typical I vs. V with V -45°C 25°C 90°C VDD [V] 12.8.2 Output driving current characteristics Subject to general operating conditions for V , and T unless otherwise specified. Table 64. Output driving current characteristics...
  • Page 110: Figure 50. Typical Vol At Vdd = 2.4 V (Standard Pins)

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Figure 50. Typical V at V = 2.4 V (standard pins) 1400 -45°C 1200 25°C 1000 90°C 130°C Iol [mA] Figure 51. Typical V at V = 3 V (standard pins) -45°C 1400 25°C 1200 90°C 1000 130°C...
  • Page 111: Figure 53. Typical Vol At Vdd = 2.4 V (Hs Pins)

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 53. Typical V at V = 2.4 V (HS pins) 1200 -45°C 1000 25°C 90°C 130°C Iol [mA] Figure 54. Typical V at V = 3 V (HS pins) 1400 -45°C 1200 25°C 1000 90°C 130°C...
  • Page 112: Figure 56. Typical Vdd-Voh At Vdd = 2.4 V (Hs Pins)

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Figure 56. Typical V at V = 2.4 V (HS pins) 1800 -45°C 1600 25°C 90°C 1400 130°C 1200 1000 Iol [mA] Figure 57. Typical V at V = 3 V (HS pins) 1800 -45°C 1600 25°C...
  • Page 113: Control Pin Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 59. Typical V vs. V (HS pins) -45°C -45°C 25°C 25°C 90°C 90°C 130°C 130°C 2.4 2.6 3.2 3.4 3.6 4.2 4.4 4.6 5.2 5.4 5.6 2.4 2.6 2.8 3.2 3.4 3.6 3.8 4.2 4.4 4.6 4.8 5.2 5.4 5.6 5.8...
  • Page 114: Table 65. Asynchronous Reset Pin Characteristics

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Refer also to Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions. Table 65. Asynchronous RESET pin characteristics Symbol Parameter Conditions Unit Input low level voltage 0.3V Input high level voltage 0.7V...
  • Page 115: Adc Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 62. RESET pin protection when LVD is disabled ST7XXX USER INTERNAL EXTERNAL RESET Filter RESET CIRCUIT 0.01μF WATCHDOG PULSE GENERATOR ILLEGAL OPCODE Required 12.10 ADC characteristics Subject to general operating condition for V , and T unless otherwise specified.
  • Page 116: Table 67. Adc Accuracy With Vdd = 3.3 To 5.5 V

    Electrical characteristics ST7LITEUS2, ST7LITEUS5 Figure 63. Typical application with ADC 0.6V AINx 10-Bit A/D Conversion 0.6V ±1μA ST7LITEUSx Table 67. ADC accuracy with V = 3.3 to 5.5 V Symbol Parameter Conditions Unit Total unadjusted error Offset error =8 MHz,...
  • Page 117: Figure 64. Adc Accuracy Characteristics

    ST7LITEUS2, ST7LITEUS5 Electrical characteristics Figure 64. ADC accuracy characteristics Digital Result ADCDR 1023 1022 – 1LSB ------------------------------- - IDEAL 1021 1024 1 LSB IDEAL (LSB IDEAL 1021 1022 1023 1024 1. Example of an actual transfer curve 2. The ideal transfer curve 3.
  • Page 118: Package Characteristics

    Package characteristics ST7LITEUS2, ST7LITEUS5 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.
  • Page 119: Table 71. 8-Pin Plastic Small Outline Package, 150-Mil Width, Package Mechanical

    ST7LITEUS2, ST7LITEUS5 Package characteristics Figure 66. 8-pin plastic small outline package, 150-mil width package outline h x 45° α Table 71. 8-pin plastic small outline package, 150-mil width, package mechanical data inches Dim. 1.35 1.75 0.0530 0.0690 0.10 0.25 0.0040 0.0100...
  • Page 120: Table 72. 8-Pin Plastic Dual In-Line Package, 300-Mil Width Package Mechanical Data

    Package characteristics ST7LITEUS2, ST7LITEUS5 Figure 67. 8-pin plastic dual in-line package, 300-mil width package outline Table 72. 8-pin plastic dual in-line package, 300-mil width package mechanical data inches Dim. 5.33 0.2100 0.38 0.0150 2.92 3.30 4.95 0.1150 0.1300 0.1950 0.36 0.46...
  • Page 121: Table 73. 16-Pin Plastic Dual In-Line Package, 300-Mil Width, Package Mechanical

    ST7LITEUS2, ST7LITEUS5 Package characteristics Figure 68. 16-pin plastic dual in-line package, 300-mil width, package outline 17_ME Table 73. 16-pin plastic dual in-line package, 300-mil width, package mechanical data inches Dim. 5.33 0.2100 0.38 0.0150 2.92 3.30 4.95 0.1150 0.1300 0.1950 0.36...
  • Page 122: Thermal Characteristics

    Package characteristics ST7LITEUS2, ST7LITEUS5 13.2 Thermal characteristics Table 74. Thermal characteristics Symbol Ratings Value Unit Plastic DIP8 Package thermal resistance °C/W DFN8 (on 4-layer thJA (junction to ambient) PCB) DFN8 (on 2-layer PCB) Maximum junction °C Jmax temperature Plastic DIP8...
  • Page 123: Device Configuration And Ordering Information

    ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information Device configuration and ordering information Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). Refer to Table 79 for the full list of supported part numbers: ●...
  • Page 124: Option Byte 0

    Device configuration and ordering information ST7LITEUS2, ST7LITEUS5 Table 75. Startup clock selection Configuration CKSEL1 CKSEL0 Internal RC as Startup Clock Reserved AWU RC as a Startup Clock Reserved External Clock on pin PA5 Table 76. LVD threshold configuration Configuration LVD1...
  • Page 125: Ordering Information

    FFh. The selected options are communicated to STMicroelectronics using the correctly completed option list appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
  • Page 126 ST7PLUSA5M3TR 10-bit -40°C +125°C Tape & Reel FASTROM ST7PLUSA5U3 10-bit DFN8 Tray ST7PLUSA5U3TR 10-bit DFN8 Tape & Reel 1. Contact ST sales office for product availability. 2. For development or tool prototyping purposes only, not orderable in production quantities. 126/136...
  • Page 127: Figure 69. Option List

    Signature:....... . . Important note: Not all configurations are available. Refer to datasheet for authorized option byte combinations. Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list 127/136...
  • Page 128: Development Tools

    RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board. ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as ST7 Socket Boards which provide all the sockets required for programming any of the devices in a specific ST7 sub-family on a platform that can be used with any tool with in- circuit programming capability for ST7.
  • Page 129: St7 Application Notes

    1. Available from ST or from Raisonance, www.raisonance.com. 2. USB connection to PC. 3. Includes connection kit for Plastic DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide for connection kit ordering information.
  • Page 130 ST7MC PMAC sine wave motor control software library General purpose AN1476 Low cost power supply for home appliances AN1526 ST7FLITE0 quick reference note AN1709 EMC design for ST Microcontrollers AN1752 ST72324 quick reference note Product evaluation AN 910 Performance benchmarking AN 990...
  • Page 131 ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information Table 81. ST7 application notes (continued) Identification Description AN1077 Overview of enhanced CAN controllers for ST7 and ST9 MCUs AN1086 U435 can-do solutions for car multiplexing AN1103 Improved B-EMF detection for low speed, low voltage with ST72141...
  • Page 132 Device configuration and ordering information ST7LITEUS2, ST7LITEUS5 Table 81. ST7 application notes (continued) Identification Description AN 987 ST7 serial test controller programming AN 988 Starting with ST7 assembly tool chain AN1039 ST7 math utility routines AN1071 Half duplex USB-to-serial bridge using the ST72611 USB microcontroller...
  • Page 133: Known Limitations

    ST7LITEUS2, ST7LITEUS5 Known limitations Known limitations External interrupt 2 (ei2) Whatever the external interrupt sensitivity configured through EICR1 register, ei2 cannot exit the MCU from Halt, Active-halt and AWUFH modes when a falling edge occurs. Workaround None 133/136...
  • Page 134: Revision History

    Revision history ST7LITEUS2, ST7LITEUS5 Revision history Table 82. Document revision history Date Revision Changes 06-Feb-06 Initial release Removed references to 3% RC Added note below Figure 4 Modified presentation of Section 4.3.1 Added notes to Section 6.2 (above Figure 9), replaced 8-bit calibration value to...
  • Page 135 Table 80 Modified Table 79 Modified option list on Figure 69: Option list Document reformatted. Replaced ST7ULTRALITE by ST7LITEUS2 and ST7LITEUS5. Removed limitations in user and in I C mode from Section 15: Known limitations, and added External interrupt 2 (ei2).
  • Page 136 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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