Cypress PSoC CY8CTMG20 Series Technical Reference Manual
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Cypress PSoC CY8CTMG20 Series Technical Reference Manual

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PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200,
CY8CTST200A TRM
®
PSoC
CY8CTMG20x, CY8CTMG20xA,
CY8CTST200, CY8CTST200A
Technical Reference Manual (TRM)
Document No. 001-53603 Rev. *C
December 11, 2009
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl.): 408.943.2600
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  • Page 1 PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A TRM ® PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A Technical Reference Manual (TRM) Document No. 001-53603 Rev. *C December 11, 2009 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl.): 408.943.2600 [+] Feedback...
  • Page 2 Cypress Source Code and derivative works for the sole purpose of creating custom soft- ware and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as speci- fied in the applicable agreement.

  • Page 3: Table Of Contents

    Contents Overview Section A: Overview Pin Information .......................... 19 Section B: PSoC Core CPU Core (M8C) ........................27 Supervisory ROM (SROM) ......................33 RAM Paging ..........................39 Interrupt Controller ........................45 General Purpose I/O (GPIO) ...................... 55 Internal Main Oscillator (IMO) ..................... 63 Internal Low Speed Oscillator (ILO) ....................
  • Page 4 Contents Overview [+] Feedback...
  • Page 5 Contents Section A: Overview Pin Information Pinouts............................19 1.1.1 CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI, CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout 19 1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout 20 1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32- Pin Part Pinout21 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC 48-Pin Part Pinout22...
  • Page 6 Contents 3.1.2.11 WriteAndVerify Function................37 3.1.2.12 HWBootReset Function................38 Register Definitions ........................ 38 RAM Paging Architectural Description......................39 4.1.1 Basic Paging......................39 4.1.2 Stack Operations ....................... 40 4.1.3 Interrupts ........................40 4.1.4 MVI Instructions......................40 4.1.5 Current Page Pointer....................40 4.1.6 Index Memory Page Pointer ..................
  • Page 7 Contents Internal Main Oscillator (IMO) Architectural Description......................63 Application Overview ......................63 7.2.1 Trimming the IMO ......................63 7.2.2 Engaging Slow IMO ....................63 Register Definitions.........................64 7.3.1 IMO_TR Register .......................64 7.3.2 IMO_TR1 Register ....................64 7.3.3 CPU_SCR1 Register ....................65 7.3.4 OSC_CR2 Register ....................65 7.3.5 Related Registers ......................66 Internal Low Speed Oscillator (ILO) Architectural Description......................67 Register Definitions.........................68...
  • Page 8 Contents 11.1.1.5 Sigma Delta....................89 11.1.2 IDAC .......................... 90 11.1.3 TrueTouch Counter ....................90 11.1.3.1 Operation ....................91 11.2 Register Definitions ....................... 92 11.2.1 CS_CR0 Register ..................... 92 11.2.2 CS_CR1 Register ..................... 93 11.2.3 CS_CR2 Register ..................... 93 11.2.4 CS_CR3 Register ..................... 94 11.2.5 CS_CNTL Register ....................
  • Page 9 Contents 15.3 Register Definitions.......................122 15.3.1 I2C_XCFG Register ....................122 15.3.2 I2C_XSTAT Register....................123 15.3.3 I2C_ADDR Register....................123 15.3.4 I2C_BP Register ......................123 15.3.5 I2C_CP Register ......................124 15.3.6 CPU_BP Register ....................124 15.3.7 CPU_CP Register....................124 15.3.8 I2C_BUF Register....................125 15.3.9 I2C_CFG Register ....................126 15.3.10 I2C_SCR Register ....................128 15.3.11 I2C_DR Register .....................129 15.4 Timing Diagrams........................130 15.4.1 Clock Generation .....................130...
  • Page 10 Contents 18.2 Register Definitions ......................147 18.2.1 SPI_TXR Register ....................147 18.2.2 SPI_RXR Register....................148 18.2.2.1 SPI Master Data Register Definitions............148 18.2.2.2 SPI Slave Data Register Definitions............148 18.2.3 SPI_CR Register .....................149 18.2.3.1 SPI Control Register Definitions..............149 18.2.4 SPI_CFG Register....................150 18.2.4.1 SPI Configuration Register Definitions ............150 18.2.5 Related Registers ....................150 18.3 Timing Diagrams ........................151 18.3.1 SPI Mode Timing .....................151...
  • Page 11 Contents 20.3.15 IMO_TR1 Register....................181 20.3.16 Related Registers ....................181 Section E: Registers 21. Register Reference 21.1 Maneuvering Around the Registers ..................187 21.2 Register Conventions ......................187 21.3 Bank 0 Registers ........................188 21.3.1 PRTxDR ........................188 21.3.2 PRTxIE ........................189 21.3.3 SPI_TXR .........................190 21.3.4 SPI_RXR ........................191 21.3.5 SPI_CR ........................192 21.3.6 USB_SOF0 ......................193 21.3.7 USB_SOF1 ......................194...
  • Page 12 Contents 21.3.46 CUR_PP .........................234 21.3.47 STK_PP ........................235 21.3.48 IDX_PP ........................236 21.3.49 MVR_PP .........................237 21.3.50 MVW_PP ........................238 21.3.51 I2C_CFG ........................239 21.3.52 I2C_SCR ........................240 21.3.53 I2C_DR ........................241 21.3.54 INT_CLR0 .......................242 21.3.55 INT_CLR1 .......................244 21.3.56 INT_CLR2 .......................246 21.3.57 INT_MSK2 ......................248 21.3.58 INT_MSK1 ......................249 21.3.59 INT_MSK0 ......................250 21.3.60 INT_SW_EN ......................251 21.3.61 INT_VC ........................252...

  • Page 13: Section A: Overview

    SRAM data memory to support various TrueTouch™ algorithms. For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the PSoC device’s data sheet. For the most current technical reference manual information and newest product documentation, go to the Cypress web site at http://www.cypress.com...
  • Page 14 Section A: Overview Top Level Architecture TrueTouch™ System The PSoC block diagram on the next page illustrates the top-level architecture CY8CTMG20x The TrueTouch System is composed of comparators, refer- CY8CTST200 devices. Each major grouping in the diagram ence drivers, I/O multiplexers, and digital logic to support is covered in this manual in its own section: PSoC Core, various capacitive sensing algorithms.
  • Page 15 Section A: Overview PSoC Core Top-Level Block Diagram 1.8/2.5/3V PWRSYS Port 4 Port 3 Port 2 Port 1 Port 0 (Regulator) CORE SYSTEM BUS 1K, 2K 8K, 16K, 32K Flash Supervisory ROM (SROM) SRAM Nonvolatile Memory Interrupt Sleep and CPU Core (M8C) Controller Watchdog 6/12/24 MHz Internal Main Oscillator (IMO)
  • Page 16 >> Documentation. Development Kits The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com under Order >> PSoC Kits. Document History This section serves as a chronicle of the PSoC®...
  • Page 17 Section A: Overview Documentation Conventions Numeric Naming Hexadecimal numbers are represented with all letters in There are only four distinguishing font types used in this uppercase with an appended lowercase ‘h’ (for example, manual, besides those found in the headings. ‘14h’...
  • Page 18 Section A: Overview Acronyms Acronyms (continued) Acronym Description This table lists the acronyms that are used in this manual. program counter high program counter low Acronyms power down Acronym Description PSoC® memory arbiter ABUS analog output bus power on reset alternating current PPOR precision power on reset...

  • Page 19: Pin Information

    CY8CTST200, and CY8CTST200A PSoC devices. For up-to-date ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet or go to http://www.cypress.com. Pinouts The CY8CTMG20x, CY8CTMG20xA, CY8CTST200, and CY8CTST200A PSoC devices are available in a variety of pack- ages.
  • Page 20 Pin Information 1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout Table 1-2. 24-Pin QFN Part Pinout ** CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, Type Name Description CY8CTST200-24LQXI, CY8CTST200-24LQXI Digital Analog PSoC Device P2[5] XTAL Out P2[3] XTAL In P2[1] IOHR P1[7] I2C SCL, SPI SS IOHR P1[5] I2C SDA, SPI MISO...
  • Page 21 Pin Information 1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32-Pin Part Pinout Table 1-3. 32-Pin QFN Part Pinout ** CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, Name Description CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC P0[1] Integrating input Devices P2[7] P2[5] XTAL Out P2[3] XTAL In P2[1] P0[1] P0[0]...
  • Page 22 Pin Information 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC 48-Pin Part Pinout Table 1-4. 48-Pin Part Pinout ** CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, Name Description CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC No connection Devices P2[7] P2[5] XTAL Out P2[3] XTAL In P2[1] P2[6] P4[3] P2[7] P2[4]...

  • Page 23: Section B: Psoc Core

    Section B: PSoC Core The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8CTMG20x or CY8CTST200 and the registers associated with those components. The core section covers the heart of the PSoC device, which includes the M8C microcontroller;...
  • Page 24 Section B: PSoC Core Core Register Summary This table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The grayed out bits are reserved bits. If you write these bits always write them with a value of ‘0’. For the core registers, the first ‘x’ in some register addresses represents either bank 0 or bank 1.
  • Page 25 Section B: PSoC Core Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access P1_LOW_ SPICLK_ON 1,DCh IO_CFG1 StrongP Range[1:0] REG_EN IOINT RW : 00 THRS _P10 INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 64)
  • Page 26 Section B: PSoC Core PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 27: Cpu Core (M8C)

    For additional information concerning the M8C instruction set, refer to the PSoC Designer Assembly Language User Guide available at the Cypress web site (http://www.cypress.com). For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187.

  • Page 28: Instruction Set Summary

    If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (refer to the http://www.cypress.com web site). Table 2-1. Instruction Set Summary Sorted Numerically by Opcode...
  • Page 29 CPU Core (M8C) Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags ADC A, expr C, Z 76 7 INC [expr] C, Z POP X ADC A, [expr] C, Z INC [X+expr] C, Z POP A ADC A, [X+expr]...

  • Page 30: Instruction Formats

    CPU Core (M8C) Instruction Formats 2.5.2 Two-Byte Instructions The majority of M8C instructions are two bytes in length. The M8C has a total of seven instruction formats that use While these instructions are divided into categories identical instruction lengths of one, two, and three bytes. All instruc- to the one-byte instructions, this does not provide a useful tion bytes are taken from the program memory (Flash), distinction between the three two-byte instruction formats...

  • Page 31: Three-Byte Instructions

    CPU Core (M8C) 2.5.3 Three-Byte Instructions The second three-byte instruction format, shown in the sec- ond row of Table 2-5, is used by the following two address- The three-byte instruction formats are the second most ing modes: prevalent instruction formats. These instructions need three Destination Direct Source Immediate (ADD [7], 5) ■...

  • Page 32: Register Definitions

    CPU Core (M8C) Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table show- ing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows.

  • Page 33: Supervisory Rom (Srom)

    3. Supervisory ROM (SROM) This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187. Architectural Description The SROM holds code that boots a PSoC device, calibrates Table 3-1.

  • Page 34: Additional Srom Feature

    Supervisory ROM (SROM) The following code example puts the correct value in KEY1 not valid, an internal reset is executed and the boot process and KEY2. The code is preceded by a HALT, to force the starts over. If this condition occurs, the internal reset status program to jump directly into the setup code and not acci- bit (IRESS) is set in the CPU_SCR1 register.

  • Page 35: Readblock Function

    Supervisory ROM (SROM) The IRAMDIS bit allows the preservation of variables even if and has two hundred fifty-six 128-byte blocks. Valid block a watchdog reset (WDR) occurs. The IRAMDIS bit is reset IDs are 0x00 to 0xFF. by all system resets except watchdog reset. Therefore, this Table 3-6.

  • Page 36: Eraseblock Function

    Supervisory ROM (SROM) An MVI A, [expr] instruction is used to move data from In this table, note that all protection is removed by EraseAll. SRAM into Flash. Therefore, use the MVI read pointer Table 3-10. Protect Block Modes (MVR_PP register) to specify which SRAM page from which data is pulled.

  • Page 37: Checksum Function

    Supervisory ROM (SROM) Table 3-14. Flash Tables with Assigned Values Table 0 Silicon ID Low Byte Reserved Silicon ID High Byte Expected Numbers = Table 0 Reserved # Bits Used to Encode = Max Values (including 0) = Bits Targeted = IMO 24 MHz IMO 6 MHz IMO 12...

  • Page 38: Hwbootreset Function

    Supervisory ROM (SROM) about 1 ms longer than WriteBlock (but still within the Twrite spec). The function performs a three-step process. In the first step, 128 bytes of data are moved from SRAM to the Flash. In the second step, Flash is programmed with the data.

  • Page 39: Ram Paging

    4. RAM Paging This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM paging registers, refer to the Summary Table of the Core Registers on page 24. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187.

  • Page 40: Stack Operations

    RAM Paging 4.1.2 Stack Operations made to the CUR_PP, IDX_PP, or STK_PP registers per- sists after the ISR returns. Therefore, have the ISR save the As mentioned previously, the paging architecture's reset current value of any paging register it modifies and restore state puts the in a mode identical to that of a 256-byte its value before the ISR returns.

  • Page 41: Index Memory

    RAM Paging ISR, the ISR is also required to restore the value before exe- After reset, the PgMode bits are set to 00b. In this mode, cuting the RETI instruction. index memory accesses are forced to SRAM Page 0, just as they are in a PSoC device with only 256 bytes of SRAM.

  • Page 42: Register Definitions

    RAM Paging Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 43: Stk_Pp Register

    RAM Paging 4.2.3 STK_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D1h STK_PP Page Bits[2:0] RW : 0 The Stack Page Pointer Register (STK_PP) is used to set Note The impact that the STK_PP register has on the stack the effective SRAM page for stack memory accesses in a is independent of the SRAM Paging bits in the CPU_F regis-...

  • Page 44: Mvw_Pp Register

    RAM Paging 4.2.6 MVW_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D5h MVW_PP Page Bits[2:0] RW : 0 The MVI Write Page Pointer Register (MVW_PP) sets the address that is written by the instruction is determined by the effective SRAM page for MVI write memory accesses in a value of the least significant bits in this register.

  • Page 45: Interrupt Controller

    5. Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a hardware resource in PSoC devices to change program execution to a new address without regard to the current task being performed by the code being executed.

  • Page 46: Posted Versus Pending Interrupts

    Interrupt Controller 5.1.1 Posted versus Pending Interrupts 4. Program execution vectors to the interrupt table. Typi- cally an LJMP instruction in the interrupt table sends exe- An interrupt is posted when its interrupt conditions occur. cution to the user's interrupt service routine for this This results in the flip-flop in Figure 5-1 clocking in a 1.
  • Page 47 Interrupt Controller The following table lists the interrupts and priorities that are available in the PSoC devices. Table 5-1. Device Interrupts Interrupt Interrupt Priority Interrupt Name Address 0 (Highest) 0000h Reset 0004h Supply voltage monitor 0008h Analog 000Ch TrueTouch 0010h Timer0 0014h GPIO...

  • Page 48: Register Definitions

    Interrupt Controller Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 49: Int_Clr1 Register

    Interrupt Controller 5.3.2 INT_CLR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DBh INT_CLR1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW : 00 This register enables the individual interrupt sources' ability Bit 4: Endpoint0.

  • Page 50: Int_Clr2 Register

    Interrupt Controller 5.3.3 INT_CLR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DCh INT_CLR2 USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00 This register enables the individual interrupt sources' ability Write 1 AND ENSWINT = 1.

  • Page 51: Int_Msk0 Register

    Interrupt Controller 5.3.4 INT_MSK0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E0h INT_MSK0 Sleep GPIO Timer0 TrueTouch Analog V Monitor RW : 00 The Interrupt Mask Register (INT_MSK0) enables the indi- Bit 6: Sleep.

  • Page 52: Int_Msk2 Register

    Interrupt Controller 5.3.6 INT_MSK2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DEh INT_MSK2 USB Wakeup Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00 This register is used to enable the individual sources' ability Bit 2: Endpoint6.

  • Page 53: Related Registers

    Interrupt Controller with any value, all pending and posted interrupts are cleared by asserting the clear line for each interrupt. For additional information, refer to the INT_VC register on page 252. 5.3.9 Related Registers CPU_F on page 254. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...
  • Page 54 Interrupt Controller PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 55: General Purpose I/O (Gpio)

    6. General Purpose I/O (GPIO) This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter- facing to the I/O pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world. They offer a large number of configurations to support several types of input/output (IO) operations for both digital and analog systems.

  • Page 56: General Description

    General Purpose I/O (GPIO) 6.1.1 General Description not affect any bits that are strongly driven low by the system the PSoC is in. However, in the second line of code, it can- The GPIO contains input buffers, output drivers, and config- not guarantee that only bit 7 is the one set to a strong 0 uration logic for connecting the PSoC device to the outside (zero).

  • Page 57: Port 0 Distinctions

    General Purpose I/O (GPIO) be greater than 2.7V, and for 1.8V output level, chip Vdd immediately assert INTO, if the Interrupt mode conditions should be greater than 2.5V. are already being met at the pin. After INTO pulls low, it continues to hold INTO low until one 6.1.5 Port 0 Distinctions of these conditions change:...

  • Page 58: Data Bypass

    General Purpose I/O (GPIO) 6.1.7 Data Bypass Interrupt High mode. If the last value read from the GPIO was ‘1’, the GPIO is in Interrupt Low mode. GPIO pins are configured to either output data through CPU writes to the PRTxDR registers or to bypass the port's data Table 6-1.

  • Page 59: Register Definitions

    General Purpose I/O (GPIO) Register Definitions The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 60: Prtxdmx Registers

    General Purpose I/O (GPIO) 6.2.3 PRTxDMx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh PRTxDM0 Drive Mode 0[7:0] RW : 00 1,xxh PRTxDM1 Drive Mode 1[7:0] RW : FF LEGEND xx An “x”...

  • Page 61: Io_Cfg1 Register

    General Purpose I/O (GPIO) 6.2.4 IO_CFG1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access P1_LOW_ SPICLK_ 1,DCh IO_CFG1 StrongP Range[1:0] REG_EN IOINT RW : 00 THRS ON_P10 The Input/Output Configuration Register 1 (IO_CFG1) con- Bit 3 P1_LOW_THRS.
  • Page 62 General Purpose I/O (GPIO) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 63: Internal Main Oscillator (Imo)

    7. Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 6, 12, and 24 MHz. For a complete table of the IMO registers, refer to the Summary Table of the Core Registers on page 24.

  • Page 64: Register Definitions

    Internal Main Oscillator (IMO) Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have associated reg- ister tables showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 65: Cpu_Scr1 Register

    Internal Main Oscillator (IMO) 7.3.3 CPU_SCR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FEh CPU_SCR1 IRESS SLIMO[1:0] IRAMDIS # : 0 LEGEND x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific.

  • Page 66: Related Registers

    Internal Main Oscillator (IMO) 7.3.5 Related Registers OSC_CR2 Register on page 115. ■ CPU_SCR1 Register on page 137. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 67: Internal Low Speed Oscillator (Ilo)

    8. Internal Low Speed Oscillator (ILO) This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed Oscillator produces a 32 kHz or 1 kHz clock. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187.

  • Page 68: Register Definitions

    Internal Low Speed Oscillator (ILO) Register Definitions The following register is associated with the Internal Low Speed Oscillator (ILO). The register description has an associated register table showing the bit structure. The bits in the table that are grayed out are reserved bits and are not detailed in the register description that follows.

  • Page 69: External Crystal Oscillator (Eco)

    9. External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crys- tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source. For a quick ref- erence of all PSoC registers in address order, refer to the Register Reference chapter on page 187.

  • Page 70: Application Overview

    External Crystal Oscillator (ECO) Figure 9-2. State Transition Between ECO and ILO This transition is allowed only if the write once "ECO Exists" register bit is set. Set OSC_CR0[7] to activate Default POR State the ECO, then on the next sleep interrupt, ECO becomes the 32.768 kHz source.

  • Page 71: Register Definitions

    External Crystal Oscillator (ECO) Register Definitions These registers are associated with the external crystal oscillator. 9.3.1 ECO_ENBUS Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,D2h ECO_ENBUS ECO_ENBUS[2:0] RW : 07 The ECO_ENBUS register is used to disable and enable the 011b –...

  • Page 72: Related Registers

    External Crystal Oscillator (ECO) 9.3.4 Related Registers OSC_CR0 Register, on page 113. ■ PRTxDR Registers register on page ■ PRTxIE Registers register on page ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 73: Sleep And Watchdog

    10. Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep and Watchdog registers, refer to the Summary Table of the Core Registers on page 24. For a quick reference of all PSoC reg- isters in address order, refer to the Register Reference chapter on page 187.

  • Page 74: Sleep Control Implementation Logic

    Sleep and Watchdog 10.1.1 Sleep Control Implementation Logic This section details the sleep mode logic implementation. Conditions for entering the sleep modes: Standby Mode: Set the SLEEP bit in the CPU_SCR0 register. This asserts the "sleep" signal for the sleep controller. ■...
  • Page 75 Sleep and Watchdog As shown in Figure 10-2, once the SLEEP bit is deasserted, the wakeup is initiated. The sequence is shown in the following timing diagram. The taps used in this wakeup sequence are generated based upon user configuration settings in the SLP_CFG3 register.”...

  • Page 76: Sleep Timer

    Sleep and Watchdog Note The T0, T1, and T2 mentioned in the SLP_CFG3 reg- Note 2 There is no need to enable the Global Interrupt ister with respect to Figure 10-2 on page 75 are defined as Enable (CPU_F register) to wake the system out of sleep follows: state.

  • Page 77: Register Definitions

    Sleep and Watchdog 10.3 Register Definitions The following registers are associated with Sleep and Watchdog operations and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions.

  • Page 78: Slp_Cfg2 Register

    Sleep and Watchdog 10.3.3 SLP_CFG2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,ECh SLP_CFG2 ALT_Buzz [1:0] I2C_ON LSO_OFF RW : 00 The Sleep Configuration Register (SLP_CFG2) holds the Bit 0: LSO_OFF: This bit disables the LSO oscillator when configuration for I2C sleep, deep sleep, and buzz.

  • Page 79: Timing Diagrams

    Sleep and Watchdog 10.4 Timing Diagrams 10.4.1 Sleep Sequence The SLEEP bit in the CPU_SCR0 register, is an input into To properly detect and recover from a VDD brown out condi- the sleep logic circuit. This circuit is designed to sequence tion, the configurable buzz rate must be frequent enough to the device into and out of the hardware sleep state.

  • Page 80: Wakeup Sequence

    Sleep and Watchdog 10.4.2 Wakeup Sequence 10.4.3 Bandgap Refresh After asleep, the only event that wakes the system is an During normal operation the bandgap circuit provides a volt- interrupt. The Global Interrupt Enable of the CPU Flag regis- age reference (VRef) to the system for use in the analog ter does not need to be set.

  • Page 81: Watchdog Timer

    Sleep and Watchdog 10.4.4 Watchdog Timer After enabled, periodically clear the WDT in firmware. Do this with a write to the RES_WDT register. This write is data On device boot up, the Watchdog Timer (WDT) is initially independent, so any write clears the watchdog timer. (Note disabled.
  • Page 82 Sleep and Watchdog PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 83: Section C: Truetouch System

    Section C: TrueTouch System The configurable TrueTouch™ System section discusses the TrueTouch and analog components of the PSoC device and the registers associated with those components. This section encompasses the following chapters: TrueTouch Module on page Comparators on page 101. ■...
  • Page 84 Section C: TrueTouch System TrueTouch Register Summary The table below lists all the PSoC registers for the TrueTouch system in address order within their system resource configura- tion. The bits that are grayed out are reserved bits. If these bits are written, always write them with a value of ‘0’. Summary Table of the TrueTouch Registers Address Name...

  • Page 85: Truetouch Module

    11. TrueTouch Module This chapter presents the TrueTouch Module and its associated registers. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187. 11.1 Architectural Description 11.1.1 Types of TrueTouch Approaches 11.1.1.1 Positive Charge Integration In the positive charge integration method, charge on a...

  • Page 86: Relaxation Oscillator

    TrueTouch Module 11.1.1.2 Relaxation Oscillator The circuit operates by alternately charging the sense capacitance to the internal voltage buffer level (first phase), The relaxation oscillator (RO) method operates by forming then on the opposite phase of the clock (second phase), the an oscillator using the sense capacitance.

  • Page 87: Successive Approximation

    TrueTouch Module Figure 11-5. Relaxation Oscillator #2 Block Diagram Figure 11-6. Successive Approximation Block Diagram Pin Enables CSCLK IDAC IDAC REF_EN Comparator Reference Closed Buffer RO Clock Refs INTERNAL 6-Bit Counter Comparator LP Filter TrueTouch Logic TrueTouch CSCLK 16-Bit Counter Clock Select TrueTouch CSCLK...

  • Page 88: Negative Charge Integration

    TrueTouch Module For typical capacitances, the IDAC current can be config- Figure 11-9. Second Phase of Successive Approximation ured so that the average voltage on the analog global does CSCLK not change. This can be done in firmware using a succes- sive approximation to find the IDAC setting that causes the global net to remain relatively stable for the load capaci- IDAC...

  • Page 89: Sigma Delta

    TrueTouch Module Figure 11-10. Negative Charge Integration Block Diagram Figure 11-12. Negative Charge Integration Second Phase: Integrating Charge onto Integration Capacitor CSCLK and Pin Enables Closed Reference REF_EN Buffer Open Closed Comparator EXTERNAL P0[1] or Reference Buffer P0[3] Refs INTERNAL Closed TrueTouch Logic Com parator...

  • Page 90: Idac

    TrueTouch Module a. If the START output from the TIMER1 is still ’1’ - rent count. Select the block interrupt from either the input counters start incrementing again. capture or the 16-bit overflow. b. If the START is ’0’ (START can become zero before In the first relaxation algorithm, the 8-bit counters operate comparator becomes ’1’...

  • Page 91: Operation

    TrueTouch Module Figure 11-13. TrueTouch Counter Block Diagram Edge Detect CMP0 CMP1 IOW or RLO_TIMER_TC BLOCK_EN TIMER RLO_TIMER_IRQ IOW or MUXBUS BLOCK_EN ‘0’ COLS COLM INSEL[2:0] COLR CS_INT IOW or BLOCK_EN COHS COHM Reset COHR Block IOW or COUNT_EN=0 Enable BLOCK_EN CLK/RLO PF_DONE=0...

  • Page 92: Register Definitions

    TrueTouch Module 11.2 Register Definitions The following registers are associated with the TrueTouch Module and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 93: Cs_Cr1 Register

    TrueTouch Module 11.2.2 CS_CR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,A1h CS_CR1 CHAIN CLKSEL[1:0] RLOCLK INSEL[2:0] RW : 00 The TrueTouch Control Register 1 (CS_CR1) contains addi- Bit 3: INV.

  • Page 94: Cs_Cr3 Register

    TrueTouch Module 11.2.4 CS_CR3 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,A3h CS_CR3 REFMUX REFMODE REF_EN LPFilt[1:0] LPF_EN[1:0] RW : 00 The TrueTouch Control Register 3 (CS_CR3) contains con- Bit 4: REF_EN.

  • Page 95: Cs_Stat Register

    TrueTouch Module 11.2.7 CS_STAT Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,A6h CS_STAT COLS COHS COLM COHM # : 00 LEGEND Access is bit specific. The TrueTouch Status Register (CS_STAT) controls True- Mask Bits 3 to 0.

  • Page 96: Cs_Slew Register

    TrueTouch Module 11.2.9 CS_SLEW Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,A8h CS_SLEW FastSlew[6:0] FS_EN RW : 00 The TrueTouch Slew Control Register (CS_SLEW) enables Bit 0: FS_EN. This bit enables the fast slewing interval on and controls a fast slewing mode for the relaxation oscillator.

  • Page 97: Idac_D Register

    TrueTouch Module 11.2.11 IDAC_D Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,FDh IDAC_D IDACDATA[7:0] RW : 00 The Current DAC Data Register (IDAC_D) specifies the 8- Bits 7 to 0: IDACDATA[7:0]. The 8-bit value in this register bit multiplying factor that determines the output DAC cur- sets the current driven onto the analog global mux bus when rent.
  • Page 98 TrueTouch Module Figure 11-18. High Byte Counter Timing (RLO Clock Selected) SYSCLK Low Byte Count Enable Low Byte Clock Low Byte Count High Byte Clock High Byte Count Enable High Byte Count Figure 11-19. 6-Bit RLO Timer Operation CS_TIMER[5:0] 03h (6-bit) RLO Clock Synchronized Count...

  • Page 99: I/O Analog Multiplexer

    12. I/O Analog Multiplexer This chapter explains the device-wide I/O Analog Multiplexer for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated registers. For a quick reference of all registers in address order, refer to the Register Reference chapter on page 187.

  • Page 100: Register Definitions

    I/O Analog Multiplexer 12.2 Register Definitions The following registers are only associated with the Analog Bus Mux in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. Each register description has an associated register table showing the bit structure for that register.

  • Page 101: Comparators

    13. Comparators This chapter explains the Comparators for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated regis- ters. For a complete table of the comparator registers, refer to the TrueTouch Register Summary on page 84. For a quick ref- erence of all registers in address order, refer to the Register Reference chapter on page 187.
  • Page 102 Comparators The comparator digital interface performs logic process- The primary output for each comparator is the LUT output or ing on one or more comparator signals, provides a latch- its latched version. These are routed to the TrueTouch logic ing capability, and routes the result to other chip and to the interrupt controller.

  • Page 103: Register Definitions

    Comparators 13.2 Register Definitions The following registers areassociated with the Comparators in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. For a complete table of the comparator registers, refer to the TrueTouch Register Summary on page 84.

  • Page 104: Cmp_Cr0 Register

    Comparators 13.2.3 CMP_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,7Ah CMP_CR0 CMP1EN CMP0EN RW : 00 The Comparator Control Register 0 (CMP_CR0) enables Bit 0: CMP0EN. This bit enables comparator 0. and configures the input range of the comparators.

  • Page 105: Section D: System Resources

    Section D: System Resources The System Resources section discusses the system resources that are available for the PSoC devices and the registers associated with those resources. This section encompasses the following chapters: Digital Clocks on page 109. SPI on page 145.
  • Page 106 Section D: System Resources System Resources Register Summary The table below lists all the registers for the system resources, in address order, within their system resource configuration. The bits that are grayed out are reserved bits. If you write these bits, always write them with a value of ‘0’. Summary Table of the System Resource Registers Address Name...
  • Page 107 Section D: System Resources Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,59h PMAx_DR Data Byte[7:0] RW : 00 0,5Ah PMAx_DR Data Byte[7:0] RW : 00 0,5Bh...
  • Page 108 Section D: System Resources Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Data Count 0,46h EPx_CNT0 Data Valid # : 0 Toggle Data Count...

  • Page 109: Digital Clocks

    14. Digital Clocks This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the sec- tion called PSoC Core on page 23.

  • Page 110: Internal Low Speed Oscillator

    Digital Clocks 14.1.2 Internal Low Speed Oscillator An external clock with a frequency between 1 MHz and 24 MHz can be supplied. The reset state of the EXTCLKEN bit The Internal Low Speed Oscillator (ILO) is available as a is ‘0’. With this setting the device always boots up under the general clock, but is also the clock source for the sleep and control of the IMO.
  • Page 111 Digital Clocks Figure 14-2. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater Extenal Clock SYSCLK CPUCLK IOW_ EXTCLK bit IMO is External clock is disabled. enabled. Figure 14-3. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One External Clock SYSCLK CPUCLK...

  • Page 112: Register Definitions

    Digital Clocks 14.2 Register Definitions The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow.

  • Page 113: Out_P0 Register

    Digital Clocks 14.2.2 OUT_P0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,D1h OUT_P0 P0P7D P0P7EN P0P4D P0P4EN RW : 00 This register enables specific internal signals to be output to Bit 6: P0P7EN.
  • Page 114 Digital Clocks view on page 70 for the proper sequence to enable the save power. The selections are shown in the table below ECO. (reset state is 001b). Bit 6: Disable Buzz. Setting this bit high causes the band- 6 MHz 12 MHz 24 MHz gap and POR/LVD systems to remain powered off continu-...

  • Page 115: Osc_Cr2 Register

    Digital Clocks 14.2.5 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E2h OSC_CR2 CLK48MEN EXTCLKEN IMODIS RW : 00 The Oscillator Control Register 2 (OSC_CR2) configures various features of internal clock sources and clock nets. Bit 4: CLK48MEN.
  • Page 116 Digital Clocks Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the Z Analog), such as drive mode 11b with the PRT1DR bit 4 external clock becomes the source for the internal clock set high. tree, SYSCLK, which drives most device clocking functions. All external and internal signals, including the low speed Bit 1: IMODIS.

  • Page 117: I2C Slave

    15. I C Slave This chapter explains the I C Slave block and its associated registers. The I C communications block is a serial processor designed to implement a complete I C slave. For a complete table of the I C registers, refer to the Summary Table of the Sys- tem Resource Registers on page...

  • Page 118: Basic I2C Data Transfer

    I2C Slave The I C block controls the data (SDA) and the clock (SCL) 15.1.1 Basic I C Data Transfer to the external I C interface through direct connections to Figure 15-2 shows the basic form of data transfers on the two dedicated GPIO pins.

  • Page 119: Ezi2C Mode

    I2C Slave Figure 15-3. Slave Operation Master may transmit another byte or STOP. M8C issues ACK/NACK M8C writes (ACK) to command with a write to ACK = OK to Slave Transmitter/Reciever An interrupt is generated on byte I2C_SCR register. the I2C_SCR register. receive more.
  • Page 120 I2C Slave by the external master through a write command and if the pointer value exceeds 1Fh, a NACK is sent. The following diagram illustrates the bus communication for a data write, a data pointer write, and a data read operation. Remember that a data write operation always rewrites the data pointer.
  • Page 121 I2C Slave The following diagram illustrates an example of how the address pointers are configured in EZI2C mode. In this example, the external master sent a Start, Slave Address, and a data byte of 2 to initialize both the base address pointer (I2C_BP register) and the current address pointer (I2C_CP register).

  • Page 122: Register Definitions

    I2C Slave 15.3 Register Definitions The registers shown here are associated with I C Slave and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are not detailed in the register descriptions that follow.

  • Page 123: I2C_Xstat Register

    I2C Slave 15.3.2 I2C_XSTAT Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,C9h I2C_XSTAT Slave Busy R : 0 Bits 0: Slave Busy. This bit is set upon a hardware The I C Extended Status Register (I2C_XSTAT) reads address compare and is reset upon the following stop sig-...

  • Page 124: I2C_Cp Register

    I2C Slave 15.3.5 I2C_CP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,CCh I2C_CP I2C Current Pointer[4:0] R : 00 The value rolls over to 0x00 when the master writes the The I C Current Address Pointer Register (I2C_CP) con- 32nd byte.

  • Page 125: I2C_Buf Register

    I2C Slave 15.3.8 I2C_BUF Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,CFh I2C_BUF Data Buffer[7:0] RW : 00 MOV A, reg[expr] The I C Data Buffer Register (I2C_BUF) is the CPU read/ MOV A, reg[X+expr] write interface to the data buffer.

  • Page 126: I2C_Cfg Register

    I2C Slave 15.3.9 I2C_CFG Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D6h I2C_CFG PSelect Stop IE Clock Rate[1:0] Enable RW : 00 Bit 4: Stop IE. Stop Interrupt Enable. When this bit is set, a The I C Configuration Register (I2C_CFG) is used to set the slave can interrupt upon Stop detection.
  • Page 127 I2C Slave C block. After enabling the I C block, wait for 3 I C sample clocks, then configure the drive modes of the I C pins to be in open drain mode. Table 15-2. Enable Operation in I2C_CFG Enable Block Operation Disabled The block is disconnected from the GPIO pins, P1[5] and P1[7].

  • Page 128: I2C_Scr Register

    I2C Slave 15.3.10 I2C_SCR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Stop Byte 0,D7h I2C_SCR Bus Error Address Transmit # : 00 Status Complete LEGEND # Access is bit specific. The selections are shown in the following table: The I C Status and Control Register (I2C_SCR) is used by...

  • Page 129: I2C_Dr Register

    I2C Slave Bit 3: Address. clock in an acknowledge bit from the receiver. Upon the sub- sequent byte complete interrupt, firmware checks the value This bit is set when an address is received. This consists of of this bit. A ‘0’ is the ACK value and a ‘1’ is a NACK value. a Start or Restart, and an address byte.

  • Page 130: Timing Diagrams

    I2C Slave 15.4 Timing Diagrams 15.4.1 Clock Generation Figure 15-6 illustrates the I C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro- vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When the Enable bit in the I2C_CFG Register is set, the reset is synchronously released and the clock generation is enabled.

  • Page 131: Status Timing

    I2C Slave 15.4.3 Status Timing Figure 15-8 illustrates the interrupt timing for byte complete, Figure 15-9 shows the timing for Stop status. This bit is set which occurs on the positive edge of the ninth clock (byte + (and the interrupt occurs) two clocks after the synchronized ACK/NACK) in transmit mode and on the positive edge of and filtered SDA line transitions to a ‘1’, when the SCL line is the eighth clock in receive mode.

  • Page 132: Slave Stall Timing

    I2C Slave 15.4.4 Slave Stall Timing When a byte complete interrupt occurs, the PSoC device firmware must respond with a write to the I2C_SCR Register to con- tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see Status Tim- ing on page 131).

  • Page 133: Compatibility Mode Configuration

    I2C Slave 15.4.6 Compatibility Mode Configuration In compatibility mode, the SCL, as usual, is pulled low until the CPU responds by setting the Transmit/Receive bit and for loading a byte in the I2C_DATA register (in case of transmit operation) even though IMO is operational. Figure 15-13 illus- trates the process of switching from direct clocking to sampled mode.
  • Page 134 I2C Slave PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 135: System Resets

    16. System Resets This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user supplied external reset, and to provide recovery from errant code operation.

  • Page 136: Powerup External Reset Behavior

    System Resets 16.2.2 Powerup External Reset Behavior 16.2.3 GPIO Behavior on External Reset The device’s core runs on chip regulated supply, so there is During External Reset (XRES=1), both P1[0] and P1[1] drive a time delay in powering up the core. A short XRES pulse at resistive low (0).

  • Page 137: Register Definitions

    System Resets 16.3 Register Definitions The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 138: Cpu_Scr0 Register

    System Resets 16.3.2 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP # : XX LEGEND Access is bit specific. Refer to register detail for additional information. XX The reset value is 10h after POR/XRES and 20h after a watchdog reset.

  • Page 139: Timing Diagrams

    System Resets 16.4 Timing Diagrams 16.4.1 Power On Reset During XRES (XRES=1), the IMO is powered off for low power during startup. After XRES deasserts, the IMO is A Power on Reset (POR) is triggered whenever the supply started (see Figure 16-4).
  • Page 140 System Resets Figure 16-4. Key Signals During POR and XRES POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+) cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8. CLK32 IPOR PPOR...

  • Page 141: Reset Details

    System Resets 16.4.4 Reset Details Timing and functionality details are summarized in Table 16-1. Figure 16-4 on page 140 shows some of the relevant signals for IPOR, PPOR, XRES, and WDR. Table 16-1. Reset Functionality Item IPOR (Part of POR) PPOR (Part of POR) XRES While PPOR=1, plus...
  • Page 142 System Resets PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 143: Por And Lvd

    17. POR and LVD This chapter briefly discusses the Power on Reset (POR) and Low Voltage Detect (LVD) circuits and their associated regis- ters. For a complete table of the POR registers, refer to the Summary Table of the System Resource Registers on page 106.

  • Page 144: Register Definitions

    POR and LVD 17.2 Register Definitions The following registers are associated with the POR and LVD, and are listed in address order. The register descriptions below have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits and are not detailed in the register descriptions that follow.

  • Page 145: Spi

    18. SPI This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI registers, refer to the Summary Table of the System Resource Registers on page 106. For a quick reference of all PSoC reg- isters in address order, refer to the Register Reference chapter on page 187.

  • Page 146: Spi Protocol Signal Definitions

    18.1.1.1 SPI Protocol Signal Definitions 18.1.2.2 Block Interrupt The SPI protocol signal definitions are located in Table 18-1. The SPIM block has a selection of two interrupt sources: The use of the SS_ signal varies according to the capability interrupt on TX Reg Empty (default) or interrupt on SPI of the slave device.

  • Page 147: Block Interrupt

    18.1.4 Input Synchronization 18.1.3.2 Block Interrupt The SPIS block has a selection of two interrupt sources: All pin inputs are double synchronized to SYSCLK by Interrupt on TX Reg Empty (default) or interrupt on SPI default. Synchronization can be bypassed by setting the Complete (same selection as the SPIM).

  • Page 148: Spi_Rxr Register

    18.2.2 SPI_RXR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,2Ah SPI_RXR Data[7:0] R : 00 The SPI Receive Data Register (SPI_RXR) is the SPI’s Bits 7 to 0: Data[7:0]. These bits encompass the SPI receive data register.

  • Page 149: Spi_Cr Register

    Control Register 18.2.3 SPI_CR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access TX Reg Clock Clock 0,2Bh SPI_CR LSb First Overrun RX Reg Full Enable # : 00 Complete Empty Phase...

  • Page 150: Spi_Cfg Register

    Configuration Register The configuration block contains 1 register. This register must not be changed while the block is enabled. Note that the SPI Configuration register is located in bank 1 of the PSoC device’s memory map. 18.2.4 SPI_CFG Register Address Name Bit 7 Bit 6...

  • Page 151: Timing Diagrams

    18.3 Timing Diagrams 18.3.1 SPI Mode Timing Figure 18-3 shows the SPI modes that are typically defined as 0, 1, 2, or 3. These mode numbers are an encoding of two control bits: Clock Phase and Clock Polarity. Clock Phase indicates the relationship of the clock to the data.

  • Page 152: Spim Timing

    18.3.2 SPIM Timing Enable/Disable Operation. As soon as the block is config- When the Enable bit in the SPI_CR register is set, the reset ured for SPIM, the primary output is the MSb or LSb of the is synchronously released and the clock generation is Shift register, depending on the LSb First configuration in bit enabled.
  • Page 153 Normal Operation. Typical timing for an SPIM transfer is After the last bit is output, if TX Buffer data is available with shown in Figure 18-5 Figure 18-6. The user initially one-half clock setup time to the next clock, a new byte trans- writes a byte to transmit when TX Reg Empty status is true.
  • Page 154 Figure 18-6. Typical SPIM Timing in Mode 2 and 3 Last bit of received Shifter is loaded Free running, data is valid on this with the next Shifter is loaded Setup time internal bit rate edge and is latched byte. with the first byte.
  • Page 155 Overrun status is set if RX Reg Full is still asserted from a mented as a latch, Overrun status is set one-half bit clock previous byte when a new byte is about to be loaded into the before RX Reg Full status. RX Buffer register.
  • Page 156 Figure 18-8. SPI Status Timing for Modes 2 and 3 MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge. User writes the next byte. SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) MOSI MISO TX REG EMPTY Last bit of byte RX REG FULL is received.

  • Page 157: Spis Timing

    18.3.3 SPIS Timing Enable/Disable Operation. As soon as the block is config- When the block is disabled, the MISO output reverts to its ured for SPI Slave and before enabling, the MISO output is idle 1 state. All internal state is reset (including CR0 status) set to idle at logic 1.
  • Page 158 Figure 18-10. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with Last bit of received data is valid Shifter is first byte (by leading on this edge and is latched into loaded with First edge of the SCLK). the RX Buffer register.
  • Page 159 Figure 18-11 illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_ to the point at which the RX Buffer register is loaded with the received byte. This means that to send a byte in the next trans- fer, it must be loaded into the TX Buffer register before the falling edge of SS_.
  • Page 160 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 161: Programmable Timer

    19. Programmable Timer This chapter presents the Programmable Timer and its associated registers. For a complete table of the programmable timer registers, refer to the Summary Table of the System Resource Registers on page 106. For a quick reference of all PSoC reg- isters in address order, refer to the Register Reference chapter on page 187.
  • Page 162 Programmable Timer Figure 19-2. Continuous Operation Example PTDATA1 0003h PTDATA0 Clock Start One Shot Count TC Period TC Period Figure 19-3. One-Shot Operation Example PTDATA1 0003h PTDATA0 Clock Start One Shot Count TC Period PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 163: Register Definitions

    Programmable Timer 19.2 Register Definitions The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 164: Pt2_Cfg Register

    Programmable Timer 19.2.3 PT2_CFG Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,B6h PT2_CFG CLKSEL One Shot START RW : 0 Programmable Timer Configuration Register tinuous mode, the timer reloads the count value each time (PT2_CFG) configures the PSoC’s programmable timer.

  • Page 165: Full-Speed Usb

    20. Full-Speed USB This chapter explains the Full-Speed USB (Universal Serial Bus) resource and its associated registers. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 187. 20.1 Architectural Description 20.2 Application Description The PSoC USB system resource adheres to the USB 2.0...

  • Page 166: Usb Sram

    Full-Speed USB Table 20-1. Mode Encoding for Control and Non-Control Endpoints Mode Encoding SETUP Comments Disable 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint. NAK IN/OUT 0001 Accept NAK IN and OUT token. Status OUT Only 0010 Accept STALL Check...
  • Page 167 Full-Speed USB The PMA's purpose is to manage the potentially conflicting The M8C may also service another channel and come back SRAM access requests from the M8C and the USB SIE. to the channel being serviced by the previous steps. To From a performance standpoint, the PMA guarantees that a determine the next address that is used when data is written continuous stream of move instructions (see ahead), are...

  • Page 168: Oscillator Lock

    Full-Speed USB 20.2.3 Oscillator Lock For a USB IN transaction, the USB SIE is reading data from the PMA and sending the data to the USB host. The follow- The PSoC device can operate without using any external ing steps must be used to set up a PMA channel for a USB components, such as a crystal, and still achieve the clock IN transaction.

  • Page 169: Using Standby I2C-Usb Sleep Mode For Usb Suspend

    Full-Speed USB (Self-powered devices do not need to go into Suspend (An alternative is to simply disconnect from the USB bus mode.) This condition is detected by monitoring the Bus before going into one of these sleep modes, and then re- Activity bit in the USB_CR1 register.
  • Page 170 Full-Speed USB Figure 20-2. Transceiver and Regulator Block Diagram VOLTAGE PS2 Pull Up REGULATOR 3.3V 1.5K TRANSMITTER RECEIVERS RSE0 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 171: Register Definitions

    Full-Speed USB 20.3 Register Definitions The following registers are related to Full-Speed USB in the PSoC device. For a complete table of the Full-Speed USB regis- ters, refer to the Registers table Summary Table of the System Resource Registers on page 106.

  • Page 172: Usbio_Cr0 Register

    Full-Speed USB 20.3.3 USBIO_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,34h USBIO_CR0 TSE0 # : 0 The USB I/O Control Register 0 (USBIO_CR0) is used for Bit 6: TSE0.

  • Page 173: Ep0_Cr Register

    Full-Speed USB 20.3.5 EP0_CR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Setup ACK’ed 0,36h EP0_CR IN Received Mode[3:0] # : 00 Received Received Transaction The Endpoint Control Register (EP0_CR) is used to config- Bit 6: IN Received.

  • Page 174: Ep0_Cnt Register

    Full-Speed USB 20.3.6 EP0_CNT Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,37h EP0_CNT Data Toggle Data Valid Byte Count[3:0] # : 00 The Endpoint 0 Count Register (EP0_CNT) is used to con- Bit 6: Data Valid.

  • Page 175: Epx_Cnt1 Register

    Full-Speed USB 20.3.8 EPx_CNT1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,41h EP1_CNT1 Data Count[7:0] RW : 00 0,43h EP2_CNT1 Data Count[7:0] RW : 00 0,45h EP3_CNT1 Data Count[7:0] RW : 00 0,47h...

  • Page 176: Epx_Cnt0 Register

    Full-Speed USB 20.3.9 EPx_CNT0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,40h EP1_CNT0 Data Toggle Data Valid Count MSB # : 0 0,42h EP2_CNT0 Data Toggle Data Valid Count MSB # : 0 0,44h...

  • Page 177: Epx_Cr0 Register

    Full-Speed USB 20.3.10 EPx_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,54h EP1_CR0 Stall NAK_INT_EN ACK’ed Tx Mode[3:0] # : 00 1,55h EP2_CR0 Stall NAK_INT_EN ACK’ed Tx Mode[3:0] # : 00 1,56h...

  • Page 178: Pmax_Wa Register

    Full-Speed USB 20.3.11 PMAx_WA Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,34h PMA0_WA Write Address[7:0] RW : 00 1,35h PMA1_WA Write Address[7:0] RW : 00 1,36h PMA2_WA Write Address[7:0] RW : 00 1,37h...

  • Page 179: Pmax_Dr Register

    Full-Speed USB 20.3.12 PMAx_DR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,58h PMA0_DR Data Byte[7:0] RW : 00 0,59h PMA1_DR Data Byte[7:0] RW : 00 0,5Ah PMA2_DR Data Byte[7:0] RW : 00 0,5Bh...

  • Page 180: Pmax_Ra Register

    Full-Speed USB 20.3.13 PMAx_RA Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,3Ch PMA0_RA Read Address[7:0] RW : 00 1,3Dh PMA1_RA Read Address[7:0] RW : 00 1,3Eh PMA2_RA Read Address[7:0] RW : 00 1,3Fh...

  • Page 181: Imo_Tr1 Register

    Full-Speed USB 20.3.15 IMO_TR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,FAh IMO_TR1 Fine Trim[2:0] RW : 00 INTERNAL Register – The Internal Main Oscillator Trim Bits 2 to 0: Fine Trim[2:0]. These bits provide a fine tuning Register 1 (IMO_TR1) fine tunes the IMO frequency.
  • Page 182 Full-Speed USB PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 183: Section E: Registers

    Section E: Registers The Registers section discusses the registers of the PSoC device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section encompasses the following chapter: Register Reference chapter on page 187.
  • Page 184 Section E: Registers Register Map Bank 0 Table: User Space PRT0DR EP1_CNT0 PRT0IE EP1_CNT1 EP2_CNT0 EP2_CNT1 PRT1DR EP3_CNT0 PRT1IE EP3_CNT1 EP4_CNT0 EP4_CNT1 PRT2DR EP5_CNT0 I2C_XCFG PRT2IE EP5_CNT1 I2C_XSTAT EP6_CNT0 I2C_ADDR EP6_CNT1 I2C_BP PRT3DR EP7_CNT0 I2C_CP PRT3IE EP7_CNT1 CPU_BP EP8_CNT0 CPU_CP EP8_CNT1 I2C_BUF PRT4DR...
  • Page 185 Section E: Registers Register Map Bank 1 Table: Configuration Space PRT0DM0 PMA4_RA PRT0DM1 PMA5_RA PMA6_RA PMA7_RA PRT1DM0 PMA8_WA PRT1DM1 PMA9_WA PMA10_WA PMA11_WA PRT2DM0 PMA12_WA PRT2DM1 PMA13_WA PMA14_WA PMA15_WA PRT3DM0 PMA8_RA PRT3DM1 PMA9_RA PMA10_RA PMA11_RA PRT4DMO PMA12_RA PRT4DM1 PMA13_RA OUT_P0 PMA14_RA ECO_ENBUS PMA15_RA ECO_TRIM...
  • Page 186 Section E: Registers PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 187: Register Reference

    21. Register Reference This chapter is a reference for all the PSoC device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the PSoC registers are in the Register Definitions section of each chapter. The registers that are in both banks are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’...

  • Page 188: Bank 0 Registers

    PRTxDR 0,00h 21.3 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi- cates that the register can be accessed in Bank 0 and Bank 1, independent of the XIO bit in the CPU_F register. Registers that are in both Bank 0 and Bank 1 are listed in address order in Bank 0.

  • Page 189: Prtxie

    PRTxIE 0,01h 21.3.2 PRTxIE Port Interrupt Enable Registers Individual Register Names and Addresses: 0,01h PRT0IE : 0,01h PRT1IE : 0,05h PRT2IE : 0,09h PRT3IE : 0,0Dh PRT4IE : 0,11h Access : POR RW : 00 Bit Name Interrupt Enables[7:0] These registers enable or disable interrupts from individual GPIO pins. The upper nibble of the PRT4IE register returns the last data bus value when read and must be masked off before using this information.

  • Page 190: Spi_Txr

    SPI_TXR 0,29h 21.3.3 SPI_TXR SPI Transmit Data Register Individual Register Names and Addresses: 0,29h SPI_TXR : 0,29h Access : POR W : 00 Bit Name Data[7:0] This register is the SPI’s transmit data register. For additional information, refer to the Register Definitions on page 147 in the SPI chapter.

  • Page 191: Spi_Rxr

    SPI_RXR 0,2Ah 21.3.4 SPI_RXR SPI Receive Data Register Individual Register Names and Addresses: 0,2Ah SPI_RXR : 0,2Ah Access : POR R : 00 Bit Name Data[7:0] This register is the SPI’s receive data register. For additional information, refer to the Register Definitions on page 147 in the SPI chapter.

  • Page 192: Spi_Cr

    SPI_CR 0,2Bh 21.3.5 SPI_CR SPI Control Register Individual Register Names and Addresses: 0,2Bh SPI_CR : 0,2Bh Access : POR RW : 0 R : 0 R : 0 R : 1 R : 0 RW : 0 RW : 0 RW : 0 Bit Name LSb First...

  • Page 193: Usb_Sof0

    USB_SOF0 0,31h 21.3.6 USB_SOF0 USB Start-of-Frame Register 0 Individual Register Names and Addresses: 0,31h USB_SOF0 : 0,31h Access : POR R : 00 Bit Name Frame Number[7:0] This register is a USB Start-of-Frame register 0. For additional information, refer to the Register Definitions on page 171 in the Full-Speed USB chapter.

  • Page 194: Usb_Sof1

    USB_SOF1 0,32h 21.3.7 USB_SOF1 USB Start-of-Frame Register 1 Individual Register Names and Addresses: 0,32h USB_SOF1 : 0,32h Access : POR R : 0 Bit Name Frame Number[10:8] This register is a USB Start-of-Frame register 1. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a value of ‘0’.

  • Page 195: Usb_Cr0

    USB_CR0 0,33h 21.3.8 USB_CR0 USB Control Register 0 Individual Register Names and Addresses: 0,33h USB_CR0 : 0,33h Access : POR RW : 0 RW : 00 Bit Name USB Enable Device Address[6:0] This register is a USB control register 0. For additional information, refer to the Register Definitions on page 171 in the Full-Speed USB chapter.

  • Page 196: Usbio_Cr0

    USBIO_CR0 0,34h 21.3.9 USBIO_CR0 USB I/O Control Register 0 Individual Register Names and Addresses: 0,34h USBIO_CR0 : 0,34h Access : POR RW : 0 RW : 0 RW : 0 R : 0 Bit Name TSE0 This register is a USBIO manual control register 0. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 197: Usbio_Cr1

    USBIO_CR1 0,35h 21.3.10 USBIO_CR1 USB I/O Control Register 1 Individual Register Names and Addresses: 0,35h USBIO_CR1 : 0,35h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 R :1 R : 1 Bit Name IOMode...

  • Page 198: Ep0_Cr

    EP0_CR 0,36h 21.3.11 EP0_CR Endpoint 0 Control Register Individual Register Names and Addresses: 0,36h EP0_CR : 0,36h Access : POR RC : 0 RC : 0 RC : 0 RC : 0 RW : 0 Bit Name Setup ACK’ed Mode[3:0] IN Received OUT Received Received...

  • Page 199: Ep0_Cnt

    EP0_CNT 0,37h 21.3.12 EP0_CNT Endpoint 0 Count Register Individual Register Names and Addresses: 0,37h EP0_CNT : 0,37h Access : POR RW : 0 RC : 0 RW : 0 Bit Name Data Toggle Data Valid Byte Count[3:0] The Endpoint 0 Count register (EP0_CNT) configures endpoint 0. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 200: Ep0_Drx

    EP0_DRx 0,38h 21.3.13 EP0_DRx Endpoint 0 Data Registers Individual Register Names and Addresses: 0,38h EP0_DR0 : 0,38h EP0_DR1 : 0,39h EP0_DR2 : 0,3Ah EP0_DR3 : 0,3Bh EP0_DR4 : 0,3Ch EP0_DR5 : 0,3Dh EP0_DR6 : 0,3Eh EP0_DR7 : 0,3Fh Access : POR RW : 00 Bit Name Data Byte[7:0]...

  • Page 201: Epx_Cnt0

    EPx_CNT0 0,40h 21.3.14 EPx_CNT0 Endpoint Count 0 Registers Individual Register Names and Addresses: 0,40h EP1_CNT0 : 0,40h EP2_CNT0 : 0,42h EP3_CNT0 : 0,44h EP4_CNT0 : 0,46h EP5_CNT0 : 0,48h EP6_CNT0 : 0,4Ah EP7_CNT0 : 0,4Ch EP8_CNT0 : 0,4Eh Access : POR RW : 0 RC : 0 # : 0...

  • Page 202: Epx_Cnt1

    EPx_CNT1 0,41h 21.3.15 EPx_CNT1 Endpoint Count 1 Registers Individual Register Names and Addresses: 0,41h EP1_CNT1 : 0,41h EP2_CNT1 : 0,43h EP3_CNT1 : 0,45h EP4_CNT1 : 0,47h EP5_CNT1 : 0,49h EP6_CNT1 : 0,4Bh EP7_CNT1 : 0,4Dh EP8_CNT1 : 0,4Fh Access : POR RW : 00 Bit Name Data Count[7:0]...

  • Page 203: Pmax_Dr

    PMAx_DR 0,58h 21.3.16 PMAx_DR PSoC Memory Arbiter Data Registers Individual Register Names and Addresses: 0,58h PMA0_DR : 0,58h PMA1_DR : 0,59h PMA2_DR : 0,5Ah PMA3_DR : 0,5Bh PMA4_DR : 0,5Ch PMA5_DR : 0,5Dh PMA6_DR : 0,5Eh PMA7_DR : 0,5Fh PMA8_DR : 0,64h PMA9_DR : 0,65h PMA10_DR : 0,66h PMA11_DR : 0,67h...

  • Page 204: Amux_Cfg

    AMUX_CFG 0,61h 21.3.17 AMUX_CFG Analog Mux Configuration Register Individual Register Names and Addresses: 0,61h AMUX_CFG : 0,61h Access : POR RW : 0 RW : 0 RW : 0 Bit Name PRX_MODE ICAPEN[1:0] INTCAP[1:0] This register is used to configure the integration capacitor pin connections to the analog global bus. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 205: Cmp_Rdc

    CMP_RDC 0,78h 21.3.18 CMP_RDC Comparator Read/Clear Register Individual Register Names and Addresses: CMP_RDC : 0,78h 0,78h Access : POR R : 0 R : 0 RC : 0 RC : 0 Bit Name CMP1D CMP0D CMP1L CMP0L This register is used to read the state of the comparator data signal and the latched state of the comparator. In the table above, reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 206: Cmp_Mux

    CMP_MUX 0,79h 21.3.19 CMP_MUX Comparator Multiplexer Register Individual Register Names and Addresses: 0,79h CMP_MUX : 0,79h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name INP1[1:0] INN1[1:0] INP0[1:0] INN0[1:0] This register contains control bits for input selection of comparators 0 and 1. For additional information, refer to the Register Definitions on page 103 in the Comparators chapter .

  • Page 207: Cmp_Cr0

    CMP_CR0 0,7Ah 21.3.20 CMP_CR0 Comparator Control Register 0 Individual Register Names and Addresses: 0,7Ah CMP_CR0 : 0,7Ah Access : POR RW : 0 RW : 0 Bit Name CMP1EN CMP0EN This register is used to enable and configure the input range of the comparators. In the table above, reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 208: Cmp_Cr1

    CMP_CR1 0,7Bh 21.3.21 CMP_CR1 Comparator Control Register 1 Individual Register Names and Addresses: 0,7Bh CMP_CR1 : 0,7Bh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name CINT1...
  • Page 209 CMP_CR1 0,7Bh 21.3.21 CMP_CR1 (continued) CDS0 This bit selects the data output for the comparator 0 channel, for routing to the capacitive sense logic and comparator 0 interrupt. Select the comparator 0 LUT output. Select the comparator 0 latch output. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No.

  • Page 210: Cmp_Lut

    CMP_LUT 0,7Ch 21.3.22 CMP_LUT Comparator LUT Register Individual Register Names and Addresses: 0,7Ch CMP_LUT : 0,7Ch Access : POR RW : 0 RW : 0 Bit Name LUT1[3:0] LUT0[3:0] This register is used to select the logic function. For additional information, refer to the Register Definitions on page 103 in the Comparators chapter.

  • Page 211: Cs_Cr0

    CS_CR0 0,A0h 21.3.23 CS_CR0 TrueTouch Control Register 0 Individual Register Names and Addresses: 0,A0h CS_CR0 : 0,A0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 CSD_ CSD_CS_ CSD_ Bit Name CSOUT[1:0]...

  • Page 212: Cs_Cr1

    CS_CR1 0,A1h 21.3.24 CS_CR1 TrueTouch Control Register 1 Individual Register Names and Addresses: 0,A1h CS_CR1 : 0,A1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name CHAIN CLKSEL[1:0] RLOCLK INSEL[2:0] This register contains additional TrueTouch system control options.

  • Page 213: Cs_Cr2

    CS_CR2 0,A2h 21.3.25 CS_CR2 TrueTouch Control Register 2 Individual Register Names and Addresses: 0,A2h CS_CR2 : 0,A2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name IRANGE IDACDIR...

  • Page 214: Cs_Cr3

    CS_CR3 0,A3h 21.3.26 CS_CR3 TrueTouch Control Register 3 Individual Register Names and Addresses: 0,A3h CS_CR3 : 0,A3h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name REFMUX REFMODE REF_EN...

  • Page 215: Cs_Cntl

    CS_CNTL 0,A4h 21.3.27 CS_CNTL TrueTouch Counter Low Byte Register Individual Register Names and Addresses: 0,A4h CS_CNTL : 0,A4h Access : POR RO : 00 Bit Name Data[7:0] This register contains the current count for the low byte counter and is read only. For additional information, refer to the Register Definitions on page 92 in the TrueTouch Module chapter .

  • Page 216: Cs_Cnth

    CS_CNTH 0,A5h 21.3.28 CS_CNTH TrueTouch Counter High Byte Register Individual Register Names and Addresses: 0,A5h CS_CNTH : 0,A5h Access : POR RO : 00 Bit Name Data[7:0] This register contains the current count value for the high byte counter and is read only. For additional information, refer to the Register Definitions on page 92 in the TrueTouch Module chapter .

  • Page 217: Cs_Stat

    CS_STAT 0,A6h 21.3.29 CS_STAT TrueTouch Status Register Individual Register Names and Addresses: 0,A6h CS_STA : 0,A6h Access : POR RC : 0 RC : 0 RC : 0 RC : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name COLS...

  • Page 218: Cs_Timer

    CS_TIMER 0,A7h 21.3.30 CS_TIMER TrueTouch Timer Register Individual Register Names and Addresses: 0,A7h CS_TIMER : 0,A7h Access : POR RW : 00 Bit Name Timer Count Value [6:0] This register sets the timer count value. For additional information, refer to the Register Definitions on page 92 in the TrueTouch Module chapter .

  • Page 219: Cs_Slew

    CS_SLEW 0,A8h 21.3.31 CS_SLEW TrueTouch Slew Control Register Individual Register Names and Addresses: 0,A8h CS_SLEW : 0,A8h Access : POR RW : 00 RW : 0 Bit Name FastSlew[6:0] FS_EN This register enables and controls a fast slewing mode for the relaxation oscillator. For additional information, refer to the Register Definitions on page 92 in the TrueTouch Module chapter .

  • Page 220: Prs_Cr

    PRS_CR 0,A9h 21.3.32 PRS_CR Pseudo Ransom Sequence and Prescaler Control Register Individual Register Names and Addresses: 0,A9h PRS_CR : 0,A9h Access : POR RW : 0 RW : 0‘ RW : 0‘ RW : 0 RW : 0 RW : 0 PRESCALE- Bit Name CS_CLK_OUT...

  • Page 221: Pt0_Cfg

    PT0_CFG 0,B0h 21.3.33 PT0_CFG Programmable Timer 0 Configuration Register Individual Register Names and Addresses: 0,B0h PT0_CFG : 0,B0h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 0. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 222: Ptx_Data1

    PTx_DATA1 0,B1h 21.3.34 PTx_DATA1 Programmable Timers Data Register 1 Individual Register Names and Addresses: 0,B1h PT0_DATA1 : 0,B1h PT1_DATA1 : 0,B4h PT2_DATA : 0,B7h Access : POR RW : 00 Bit Name DATA[7:0] These registers hold the eight bits of the progammable timer’s count value for the device. For additional information, refer to the Register Definitions on page 163 in the Programmable Timer chapter .

  • Page 223: Ptx_Data0

    PTx_DATA0 0,B2h 21.3.35 PTx_DATA0 Programmable Timers Data Register 0 Individual Register Names and Addresses: 0,B2h PT0_DATA : 0,B2h PT1_DATA0 : 0,B5h PT2_DATA0 : 0,B8h Access : POR RW : 00 Bit Name DATA[7:0] These registers provide the programmable timer with its lower eight bits of the count value. For additional information, refer to the Register Definitions on page 163 in the Programmable Timer chapter .

  • Page 224: Pt1_Cfg

    PT1_CFG 0,B3h 21.3.36 PT1_CFG Programmable Timer 1 Configuration Register Individual Register Names and Addresses: 0,B3h PT1_CFG : 0,B3h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 1. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 225: Pt2_Cfg

    PT2_CFG 0,B6h 21.3.37 PT2_CFG Programmable Timer 2 Configuration Register Individual Register Names and Addresses: 0,B6h PT2_CFG : 0,B6h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 2. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 226: I2C_Xcfg

    I2C_XCFG 0,C8h 21.3.38 I2C_XCFG C Extended Configuration Register Individual Register Names and Addresses: 0,C8h I2C_XCFG: 0,C8h Access : POR RW : 0 RW : 0 RW : 0 Bit Name No BC Int Buffer Mode HW Addr En This register configures enhanced features. The Enable bit (bit 0) of the I2C_CFG (0,D6h) register should be set to 1'b1 for the I2C enhanced features to work.

  • Page 227: I2C_Xstat

    I2C_XSTAT 0,C9h 21.3.39 I2C_XSTAT C Extended Status Register Individual Register Names and Addresses: 0,C9h 0,D0h I2C_XSTAT : 0,C9h Access : POR R : 0 R : 0 Bit Name Slave Busy This register reads enhanced feature status. When the bits of the I2C_XCFG register are left in their reset state, the block is in compatibility mode and this register is not in use.

  • Page 228: I2C_Addr

    I2C_ADDR 0,CAh 21.3.40 I2C_ADDR C Slave Address Register Individual Register Names and Addresses: 0,CAh 0,D0h I2C_ADDR : 0,CAh Access : POR RW : 00 Bit Name Slave Address[6:0] This register holds the slave’s 7-bit address. When hardware address compare mode is not enabled in the I2C_XCFG register, this register is not in use.

  • Page 229: I2C_Bp

    I2C_BP 0,CBh 21.3.41 I2C_BP C Base Address Pointer Register Individual Register Names and Addresses: 0,CBh 0,D0h I2C_BP : 0,CBh Access : POR R : 00 Bit Name I2C Base Pointer[4:0] This register contains the base address value of the RAM data buffer and is read only. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 230: I2C_Cp

    I2C_CP 0,CCh 21.3.42 I2C_CP C Current Address Pointer Register Individual Register Names and Addresses: 0,CCh I2C_CP : 0,CCh Access : POR R : 00 Bit Name I2C Current Pointer[4:0] This register contains the current address value of the RAM data buffer and is read only. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 231: Cpu_Bp

    CPU_BP 0,CDh 21.3.43 CPU_BP CPU Base Address Pointer Register Individual Register Names and Addresses: 0,CDh CPU_BP : 0,CDh Access : POR RW : 00 Bit Name CPU Base Pointer[4:0] This register contains the base address value of the RAM data buffer. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 232: Cpu_Cp

    CPU_CP 0,CEh 21.3.44 CPU_CP CPU Current Address Pointer Register Individual Register Names and Addresses: 0,CEh CPU_CP : 0,CEh Access : POR R : 00 Bit Name CPU Current Pointer [4:0] This register is a pointer into the RAM buffer for CPU reads and writes and is read only. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 233: I2C_Buf

    I2C_BUF 0,CFh 21.3.45 I2C_BUF C Data Buffer Register Individual Register Names and Addresses: 0,CFh I2C_BUF : 0,CFh Access : POR RW : 00 Bit Name Data Buffer [7: 0] This register is the CPU read/write interface to the data buffer. For additional information, refer to the Register Definitions on page 122 in the I2C Slave chapter.

  • Page 234: Cur_Pp

    CUR_PP 0,D0h 21.3.46 CUR_PP Current Page Pointer Register Individual Register Names and Addresses: 0,D0h CUR_PP : 0,D0h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page device. It is only used when a device has more than one SRAM page.

  • Page 235: Stk_Pp

    STK_PP 0,D1h 21.3.47 STK_PP Stack Page Pointer Register Individual Register Names and Addresses: 0,D1h STK_PP : 0,D1h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. It is only used when a device has more than one SRAM page.

  • Page 236: Idx_Pp

    IDX_PP 0,D3h 21.3.48 IDX_PP Indexed Memory Access Page Pointer Register Individual Register Names and Addresses: 0,D3h IDX_PP : 0,D3h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device. This register is only used when a device has more than one page of SRAM.

  • Page 237: Mvr_Pp

    MVR_PP 0,D4h 21.3.49 MVR_PP MVI Read Page Pointer Register Individual Register Names and Addresses: 0,D4h MVR_PP : 0,D4h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device. This register is only used when a device has more than one page of SRAM.

  • Page 238: Mvw_Pp

    MVW_PP 0,D5h 21.3.50 MVW_PP MVI Write Page Pointer Register Individual Register Names and Addresses: 0,D5h MVW_PP : 0,D5h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. This register is only used when a device has more than one page of SRAM.

  • Page 239: I2C_Cfg

    I2C_CFG 0,D6h 21.3.51 I2C_CFG C Configuration Register Individual Register Names and Addresses: 0,D6h I2C_CFG : 0,D6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PSelect Stop IE Clock Rate[1:0] Enable This register is used to set the basic operating modes, baud rate, and interrupt selection. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 240: I2C_Scr

    I2C_SCR 0,D7h 21.3.52 I2C_SCR C Status and Control Register Individual Register Names and Addresses: 0,D7h I2C_SCR : 0,D7h Access : POR RC : 0 RC : 0 RW : 0 RC : 0 RW : 0 RC : 0 RC : 0 Bit Name Bus Error Stop Status...

  • Page 241: I2C_Dr

    I2C_DR 0,D8h 21.3.53 I2C_DR C Data Register Individual Register Names and Addresses: 0,D8h I2C_DR : 0,D8h Access : POR RW : 00 Bit Name Data[7:0] This register provides read/write access to the Shift register. This register is read only for received data and write only for transmitted data. For additional information, refer to the Register Definitions on page 122 in the I2C Slave chapter .

  • Page 242: Int_Clr0

    INT_CLR0 0,DAh 21.3.54 INT_CLR0 Interrupt Clear Register 0 Individual Register Names and Addresses: 0,DAh INT_CLR0 : 0,DAh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep...
  • Page 243 INT_CLR0 0,DAh 21.3.54 INT_CLR0 (continued) Timer0 Read 0 No posted interrupt for Timer. Read 1 Posted interrupt present for Timer. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.

  • Page 244: Int_Clr1

    INT_CLR1 0,DBh 21.3.55 INT_CLR1 Interrupt Clear Register 1 Individual Register Names and Addresses: 0,DBh INT_CLR1 : 0,DBh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Endpoint3...
  • Page 245 INT_CLR1 0,DBh 21.3.55 INT_CLR1 (continued) Endpoint0 Read 0 No posted interrupt for USB Endpoint0. Read 1 Posted interrupt present for USB Endpoint0. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.

  • Page 246: Int_Clr2

    INT_CLR2 0,DCh 21.3.56 INT_CLR2 Interrupt Clear Register 2 Individual Register Names and Addresses: 0,DCh INT_CLR2 : 0,DCh Access : RW:00 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name USB_WAKE Endpoint8 Endpoint7...
  • Page 247 INT_CLR2 0,DCh 21.3.56 INT_CLR2 (continued) Endpoint7 Read 0 No posted interrupt for USB Endpoint7. Read 1 Posted interrupt present for USB Endpoint7. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.

  • Page 248: Int_Msk2

    INT_MSK2 0,DEh 21.3.57 INT_MSK2 Interrupt Mask Register 2 Individual Register Names and Addresses: 0,DEh INT_MSK2 : 0,DEh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name USB Wakeup Endpoint8 Endpoint7...

  • Page 249: Int_Msk1

    INT_MSK1 0,DFh 21.3.58 INT_MSK1 Interrupt Mask Register 1 Individual Register Names and Addresses: 0,DFh INT_MSK1 : 0,DFh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 USB Bus Bit Name...

  • Page 250: Int_Msk0

    INT_MSK0 0,E0h 21.3.59 INT_MSK0 Interrupt Mask Register 0 Individual Register Names and Addresses: 0,E0h INT_MSK0 : 0,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep...

  • Page 251: Int_Sw_En

    INT_SW_EN 0,E1h 21.3.60 INT_SW_EN Interrupt Software Enable Register Individual Register Names and Addresses: 0,E1h INT_SW_EN : 0,E1h Access : POR RW : 0 Bit Name ENSWINT This register is used to enable software interrupts. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a value of ‘0’.

  • Page 252: Int_Vc

    INT_VC 0,E2h 21.3.61 INT_VC Interrupt Vector Clear Register Individual Register Names and Addresses: 0,E2h INT_VC : 0,E2h Access : POR RC : 00 Bit Name Pending Interrupt[7:0] This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the Register Definitions on page 48 in the Interrupt Controller chapter.

  • Page 253: Res_Wdt

    RES_WDT 0,E3h 21.3.62 RES_WDT Reset Watchdog Timer Register Individual Register Names and Addresses: 0,E3h RES_WDT : 0,E3h Access : POR W : 00 Bit Name WDSL_Clear[7:0] This register is used to clear the watchdog timer alone, or clear both the watchdog timer and the sleep timer together. For additional information, refer to the Register Definitions on page 77 in the Sleep and Watchdog chapter.

  • Page 254: Cpu_F

    CPU_F x,F7h 21.3.63 CPU_F M8C Flag Register Individual Register Names and Addresses: x,F7h CPU_F : x,F7h Access : POR RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 Bit Name PgMode[1:0] BINC Carry Zero...
  • Page 255 CPU_F x,F7h 21.3.63 CPU_F (continued) Zero Set by the M8C CPU Core to indicate whether there was a zero result in the previous logical/arith- metic operation. Not equal to zero. Equal to zero. M8C does not process any interrupts. Interrupt processing enabled. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No.

  • Page 256: Idac_D

    IDAC_D 0,FDh 21.3.64 IDAC_D Current DAC Data Register Individual Register Names and Addresses: 0,FDh IDAC_D : 0,FDh Access : POR RW : 00 Bit Name IDACDATA[7:0] This register specifies the 8-bit multiplying factor that determines the output IDAC current. For additional information, refer to the Register Definitions on page 92 in the TrueTouch Module chapter.

  • Page 257: Cpu_Scr1

    CPU_SCR1 x,FEh 21.3.65 CPU_SCR1 System Status and Control Register 1 Individual Register Names and Addresses: x,FEh CPU_SCR1: x,FEh Access : POR R : 0 RW : 0 RW : 0 Bit Name IRESS SLIMO[1:0] IRAMDIS This register is used to convey the status and control of events related to internal resets and watchdog reset. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 258: Cpu_Scr0

    CPU_SCR0 x,FFh 21.3.66 CPU_SCR0 System Status and Control Register 0 Individual Register Names and Addresses: x,FFh CPU_SCR0 : x,FFh Access : POR R : 0 RC : 0 RC : 1 RW : 0 RW : 0 Bit Name GIES WDRS PORS Sleep...

  • Page 259: Bank 1 Registers

    PRTxDM0 1,00h 21.4 Bank 1 Registers The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are listed in address order in the section titled Bank 0 Registers on page 188.

  • Page 260: Prtxdm1

    PRTxDM1 1,01h 21.4.2 PRTxDM1 Port Drive Mode Bit Registers 1 Individual Register Names and Addresses: 1,01h PRT0DM1 : 1,01h PRT1DM1 : 1,05h PRT2DM1 : 1,09h PRT3DM1 : 1,0Dh PRT4DM1 : 1,11h Access : POR RW : FF Bit Name Drive Mode 1[7:0] This register is one of three registers where the combined value determines the unique drive mode of each bit in a GPIO port.

  • Page 261: Spi_Cfg

    SPI_CFG 1,29h 21.4.3 SPI_CFG SPI Configuration Register Individual Register Names and Addresses: 1,29h SPI_CFG : 1,29h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Clock Sel [2:0] Bypass SS_EN_ Int Sel...

  • Page 262: Usb_Cr1

    USB_CR1 1,30h 21.4.4 USB_CR1 USB Control Register 1 Individual Register Names and Addresses: 1,30h USB_CR1 : 1,30h Access : POR RC : 0 RW : 0 RW : 0 Bit Name BusActivity EnableLock RegEnable This register is used to configure the internal regulator and the oscillator tuning capability. This register is only used by the CY8CTMG20x, CY8CTST200 PSoC devices.

  • Page 263: Pmax_Wa

    PMAx_WA 1,34h 21.4.5 PMAx_WA PSoC Memory Arbiter Write Address Registers Individual Register Names and Addresses: 1,34h PMA0_WA : 1,34h PMA1_WA : 1,35h PMA2_WA : 1,36h PMA3_WA : 1,37h PMA4_WA : 1,38h PMA5_WA : 1,39h PMA6_WA : 1,3Ah PMA7_WA : 1,3Bh PMA8_WA : 1,44H PMA9_WA : 1,45H PMA10_WA : 1,46H...

  • Page 264: Pmax_Ra

    PMAx_RA 1,3Ch 21.4.6 PMAx_RA PSoC Memory Arbiter Read Address Registers Individual Register Names and Addresses: 1,3Ch PMA0_RA : 1,3Ch PMA1_RA : 1,3Dh PMA2_RA : 1,3Eh PMA3_RA : 1,3Fh PMA4_RA : 1,40h PMA5_RA : 1,41h PMA6_RA : 1,42h PMA7_RA : 1,43h PMA8_RA : 1,4Ch PMA9_RA : 1,4Dh PMA10_RA : 1,4Eh...

  • Page 265: Epx_Cr0

    EPx_CR0 1,54h 21.4.7 EPx_CR0 Endpoint Control Registers 0 Individual Register Names and Addresses: 1,54h EP1_CR0 : 1,54h EP2_CR0 : 1,55h EP3_CR0 : 1,56h EP4_CR0 : 1,57h EP5_CR0 : 1,58h EP6_CR0 : 1,59h EP7_CR0 : 1,5Ah EP7_CR0 : 1,5Bh Access : POR RW : 0 RW : 0 RC : 0...

  • Page 266: Tmp_Drx

    TMP_DRx x,6Ch 21.4.8 TMP_DRx Temporary Data Registers Individual Register Names and Addresses: x,6Ch TMP_DR0 : x,6Ch TMP_DR1 : x,6Dh TMP_DR2 : x,6Eh TMP_DR3 : x,6Fh Access : POR RW : 00 Bit Name Data[7:0] These registers enhance the performance in multiple SRAM page PSoC devices. All bits in this register are reserved for PSoC devices with 256 bytes of SRAM.

  • Page 267: Usb_Misc_Cr

    USB_MISC_CR 1,BDh 21.4.9 USB_MISC_CR USB Miscellaneous Control Register Individual Register Names and Addresses: 1,BDh USB_MISC_CR: 1,BDh Access : POR RW : 0 RW : 0 RW : 0 Bit Name USB_SE_EN USB_ON USB_CLK_ON The USB Miscellaneous Control Register controls the clocks to the USB block to make IMO work with better accuracy for the USB part and to disable the single ended input of USBIO in the case of a non-USB part.

  • Page 268: Out_P0

    OUT_P0 1,D1h 21.4.10 OUT_P0 Output Override to Port 0 Register Individual Register Names and Addresses: 1,D1h OUT_P0: 1,D1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name P0P7D P0P7EN P0P4D P0P4EN This register enables specific internal signals to output to Port 0 pins. The GPIO drive modes must be specified to support the desired output mode (registers PRT1DM1 and PRT1DM0).

  • Page 269: Eco_Enbus

    ECO_ENBUS 1,D2h 21.4.11 ECO_ENBUS External Oscillator ENBUS Register Individual Register Names and Addresses: 1,D2h ECO_ENBUS : 1,D2h Access : POR RW : 7 Bit Name ECO_ENBUS[2:0] The ECO_ENBUS register is used to disable and enable the external crystal oscillator (ECO). In the table above, note that reserved bits are grayed table cells and are not described in the bit description section.

  • Page 270: Eco_Trim

    ECO_TRIM 1,D3h 21.4.12 ECO_TRIM External Oscillator Trim Register Individual Register Names and Addresses: 1,D3h ECO_TRIM : 1,D3h Access : POR RW : 4 RW : 1 Bit Name ECO_XGM[2:0] ECO_LP[1:0] This register trims the external oscillator gain and power settings. These settings in this register should not be changed from their default state.

  • Page 271: Mux_Crx

    MUX_CRx 1,D8h 21.4.13 MUX_CRx Analog Mux Port Bit Enable Registers Individual Register Names and Addresses: 1,D8h MUX_CR0 : 1,D8h MUX_CR1 : 1,D9h MUX_CR2 : 1,DAh MUX_CR3 : 1,DBh MUX_CR4 : 1,DFh Access : POR RW : 00 Bit Name ENABLE[7:0] This register is used to control the connection between the analog mux bus and the corresponding pin.

  • Page 272: Io_Cfg1

    IO_CFG1 1,DCh 21.4.14 IO_CFG1 Input/Output Configuration Register 1 Individual Register Names and Addresses: 1,DCh IO_CFG1 : 1,DCh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name P1_LOW_ SPICLK_ StrongP...

  • Page 273: Out_P1

    OUT_P1 1,DDh 21.4.15 OUT_P1 Output Override to Port 1 Register Individual Register Names and Addresses: 1,DDh OUT_P1: 1,DDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name P16D...
  • Page 274 OUT_P1 1,DDh 21.4.15 OUT_P1 (continued) P10D Bit selects the data output to P1[0] when P10EN is high. Select Sleep Interrupt (SLPINT) Select Comparator 0 Output (CMP0) P10EN Bit enables pin P1[0] for output of the signal selected by the P10D bit. No internal signal output to P1[0] Output the signal selected by P10D to P1[0] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No.

  • Page 275: Io_Cfg2

    IO_CFG2 1,DEh 21.4.16 IO_CFG2 Input/Output Configuration Register 2 Individual Register Names and Addresses: 1,DEh IO_CFG2 : 1,DEh Access : POR RW : 0 RW : 0 Bit Name REG_LEVEL[2:0] REG_CLOCK[1:0] The Input/Output Configuration 2 Register (IO_CFG2) selects output regulated supply and clock rates. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section.

  • Page 276: Osc_Cr0

    OSC_CR0 1,E0h 21.4.17 OSC_CR0 Oscillator Control Register 0 Individual Register Names and Addresses: 1,E0h OSC_CR0: 1,E0h Access : POR RW: 0 RW : 0 RW : 0 RW : 0 RW : 010b Bit Name X32ON Disable Buzz No Buzz Sleep[1:0] CPU Speed[2:0] This register is used to configure various features of internal clock sources and clock nets.

  • Page 277: Eco_Cfg

    ECO_CFG 1,E1h 21.4.18 ECO_CFG External Oscillator Trim Configuration Register Individual Register Names and Addresses: 1,E1h ECO_CFG : 1,E1h Access : POR RW : 0 RW : 0 RW : 0 Bit Name ECO_LPM ECO_EXW ECO_EX This register provides ECO status and control information. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 278: Osc_Cr2

    OSC_CR2 1,E2h 21.4.19 OSC_CR2 Oscillator Control Register 2 Individual Register Names and Addresses: 1,E2h OSC_CR2 : 1,E2h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLK48MEN EXTCLKEN IMODIS This register is used to configure various features of internal clock sources and clock nets. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 279: Vlt_Cr

    VLT_CR 1,E3h 21.4.20 VLT_CR Voltage Monitor Control Register Individual Register Names and Addresses: 1,E3h VLT_CR: 1,E3h Access : POR RW : 0 RW : 0 RW : 0 Bit Name PORLEV[1:0] LVDTBEN VM[2:0] This register is used to set the trip points for POR and LVD. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 280: Vlt_Cmp

    VLT_CMP 1,E4h 21.4.21 VLT_CMP Voltage Monitor Comparators Register Individual Register Names and Addresses: 1,E4h VLT_CMP : 1,E4h Access : POR R : 0 Bit Name This register reads the state of the internal supply voltage monitors. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a value of ‘0’.

  • Page 281: Imo_Tr

    IMO_TR 1,E8h 21.4.22 IMO_TR Internal Main Oscillator Trim Register Individual Register Names and Addresses: 1,E8h IMO_TR : 1,E8h Access : POR RW : 00 Bit Name Trim[7:0] This register is used to manually center the Internal Main Oscillator’s (IMO) output to a target frequency. It is strongly recommended that you do not alter this register’s values except to load factory trim settings when changing IMO range.

  • Page 282: Ilo_Tr

    ILO_TR 1,E9h 21.4.23 ILO_TR Internal Low Speed Oscillator Trim Register Individual Register Names and Addresses: 1,E9h ILO_TR : 1,E9h Access : POR RW : 0 RW : 0 RW : 08 Bit Name PD_MODE ILOFREQ Freq Trim[3:0] This register sets the adjustment for the Internal Low Speed Oscillator (ILO). It is strongly recommended that you do not alter this register’s Freq Trim[3:0] values.

  • Page 283: Slp_Cfg

    SLP_CFG 1,EBh 21.4.24 SLP_CFG Sleep Configuration Register Individual Register Names and Addresses: 1,EBh SLP_CFG : 1,EBh Access : POR RW : 0 Bit Name PSSDC[1:0] This register sets up the sleep duty cycle. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a value of ‘0’.

  • Page 284: Slp_Cfg2

    SLP_CFG2 1,ECh 21.4.25 SLP_CFG2 Sleep Configuration Register 2 Individual Register Names and Addresses: 1,ECh SLP_CFG2 : 1,ECh Access : POR RW : 0 RW : 0 RW : 0 Bit Name ALT_Buzz[1:0] I2C_ON LSO_OFF This register holds the configuration for I2C sleep, deep sleep, and buzz. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.

  • Page 285: Slp_Cfg3

    SLP_CFG3 1,EDh 21.4.26 SLP_CFG3 Sleep Configuration Register 3 Individual Register Names and Addresses: 1,EDh SLP_CFG3 : 1,EDh Access : POR RW : 1 RW : 11 RW : 11 RW : 11 Bit Name DBL_TAPS T2TAP[1:0] T1TAP[1:0] T0TAP[1:0] This register holds the configuration of the wakeup sequence taps. It is strongly recommended to not alter this register setting .

  • Page 286: Imo_Tr1

    IMO_TR1 1,FAh 21.4.27 IMO_TR1 Internal Main Oscillator Trim Register 1 Individual Register Names and Addresses: 1,FAh IMO_TR1 : 1,FAh Access : POR W : 0 Bit Name FineTrim[2:0] This register is used to fine tune the IMO frequency. It is strongly recommended that the user not alter this register’s values. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section.

  • Page 287: Section F: Glossary

    Section F: Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. accumulator In a CPU, a register in which intermediate results are stored. Without an accumulator, it would be necessary to write the result of each calculation (addition, subtraction, shift, and so on) to main memory and read them back.
  • Page 288 Glossary A series of software routines that comprise an interface between a computer application and API (Application Pro- gramming Interface) lower-level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. array An array, also known as a vector or list, is one of the simplest data structures in computer pro- gramming.
  • Page 289 Glossary The number of bits occurring per unit of time in a bit stream, usually expressed in bits per second bit rate (BR) (bps). block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital block or an analog block.
  • Page 290 Glossary Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another. checksum The checksum of a set of data is generated by adding the value of each data word to a sum. The actual checksum can simply be the result sum or a value that must be added to the sum to gen- erate a pre-determined value.
  • Page 291 Glossary A hardware and software system that allows the user to analyze the operation of the system debugger under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition.
  • Page 292 Glossary The software that is embedded in a hardware device and executed by the CPU. The software firmware may be executed by the end user but it may not be modified. flag Any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission).
  • Page 293 Glossary A base 16 numeral system (often abbreviated and called hex), usually written using the symbols hexadecimal 0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits. Compare the binary, hex, and decimal representations: 0000b = 0001b =...
  • Page 294 Glossary A suspension of a process, such as the execution of a computer program, caused by an event interrupt external to that process and performed in such a way that the process can be resumed. interrupt service rou- A block of code that normal code execution is diverted to when the M8C receives a hardware tine (ISR) interrupt.
  • Page 295 Glossary An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside the PSoC device by interfacing to the Flash, SRAM, and register space. macro A programming language macro is an abstraction whereby a certain textual pattern is replaced according to a defined set of rules. The interpreter or compiler automatically replaces the macro instance with the macro contents when an instance of the macro is encountered.
  • Page 296 Glossary 1. A logic function that uses a binary value, or address, to select between a number of inputs multiplexer (mux) and conveys the data from the selected input to the output. 2. A technique which allows different input (or output) signals to use the same lines at different times, controlled by an external signal.
  • Page 297 A set of rules. Particularly the rules that govern networked communications. PSoC® Cypress Semiconductor’s Programmable System-on-Chip (PSoC) mixed-signal array. PSoC® is a trademark of Cypress. PSoC blocks See analog blocks and digital blocks .
  • Page 298 Glossary A unique identifier of the PSoC device. revision ID ripple divider An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2 - 1.
  • Page 299 Glossary The difference in arrival time of bits transmitted at the same time, in parallel transmission. skew slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface.
  • Page 300 Glossary The connection between two blocks of a device created by connecting several blocks/compo- nents in a series, such as a shift register or resistive voltage divider. terminal count The state at which a counter is counted down to zero. threshold The minimum value of a signal that can be detected by the system or sensor under consider- ation.
  • Page 301 Glossary watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. waveform The representation of a signal as a plot of amplitude versus time. See Boolean Algebra . PSoC CY8CTMG20x and CY8CTST200 TRM, Document No.
  • Page 302 Glossary PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback...

  • Page 303: Section F: Index

    Index Numerics CINTx bits 208 CIP_EN bit 213 16-Pin Part Pinout 19 CLKSEL bits 212 24-Pin Part Pinout 20 Clock Phase bit in SPI_CR 192 32 kHz clock selection 67 Clock Polarity bit 192 32-Pin Part Pinout 21 Clock Rate bits 239 48-Pin Part Pinout 22 Clock Sel bit 261 clock, external digital 110...
  • Page 304 Index CS_CNTL register 94, 215 EXTCLKEN bit 278 CS_CR0 register 92, 211 external digital clock 110 CS_CR1 register 93, 212 external reset 139 CS_CR2 register 93, 213 CS_CR3 register 94, 214 CS_SLEW register 219, 220 CS_STAT register 95, 217 FastSlew bits 219 CS_TIMER register 95, 218 Flash CSD_CS_CLK bit in CS_CR0 register 211...
  • Page 305 Index stall timing 132 IRESS bit 257 status timing 131 I2C_CFG register 126, 239 I2C_DR register 129, 241 I2C_SCR register 128, 240 low voltage detect (LVD) ICAPEN bit 204 See POR and LVD IDAC_D register 97, 256 LRB bit 240 IDACDATA bits 256 LSb First bit 192 IDACEN bit 213...
  • Page 306 Index in MVR_PP register 237 reference of all registers 187 in MVW_PP register 238 register conventions 17, 187 in STK_PP register 235 register definitions Pending Interrupt bits 252 comparators 103 PgMode bits 254 CPU core 32 digital clocks 112 pin behavior during reset 135 general purpose IO 59 pin information, See pinouts I2C slave 122...
  • Page 307 Index Sleep bits 276 functional details 141 pin behavior 135 sleep timer 76 power modes 141 SLIMO bit 257 power on reset 139 SLP_CFG register 77, 283, 284, 285 register definitions 137 SPI 145 timing diagrams 139 architecture 145 watchdog timer reset 139 configuration register 150 system resources control register 149...
  • Page 308 Index VM bits 279 watchdog timer reset 139 WDRS bit 258 WDSL_Clear bits 253 WriteAndVerify function in SROM 37 WriteBlock function in SROM 35 XIO bit 254 XRES reset 139 Zero bit 255 [+] Feedback...

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