Related Manuals for Cypress CapSense CY8CMBR2010
Summary of Contents for Cypress CapSense CY8CMBR2010
- Page 1 AN75999 ® CY8CMBR2010 CapSense Design Guide Doc. No. 001-75999 Rev. *E Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 http://www.cypress.com...
- Page 2 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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Page 3: Table Of Contents
Contents Introduction ..................................5 Abstract ................................. 5 Cypress’s CapSense Documentation Ecosystem ....................5 ® CY8CMBR2010 CapSense Express Device Features ..................7 Document Conventions ............................8 CapSense Technology ..............................9 CapSense Fundamentals ............................9 Capacitive Sensing Method ..........................11 2.2.1 CapSense Sigma-Delta (CSD) ....................... 11 SmartSense Auto-Tuning ............................ - Page 4 Contents Electrical and Mechanical Design Considerations ....................33 Overlay Selection..............................33 4.1.1 Bonding Overlay to PCB ......................... 34 ESD Protection ..............................34 4.2.1 Prevent ..............................34 4.2.2 Redirect ..............................34 4.2.3 Clamp ..............................34 Electromagnetic Compatibility (EMC) Considerations ..................35 4.3.1 Radiated Interference ..........................
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Page 5: Introduction
1. Introduction 1.1 Abstract ® This document describes how to implement capacitive sensing functionality using Cypress’s CapSense Express™ CY8CMBR2010 device. The following topics are covered in this guide: Features of the CY8CMBR2010 CapSense principles of operation Configuration options of the CY8CMBR2010 device ... - Page 6 Introduction Figure 1-1. Typical CapSense Product Design Flow ® CY8CMBR2010 CapSense Design Guide Doc. No. 001-75999 Rev. *E...
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Page 7: Cy8Cmbr2010 Capsense ® Express Device Features
This document This document ® 1.3 CY8CMBR2010 CapSense Express Device Features Cypress’s low-power CapSense controller can easily add capacitive touch sensing to your user interface. The device’s features include: Hardware Configurable CapSense Controller Does not require software tools or programming ... -
Page 8: Document Conventions
Introduction Noise Immunity Specifically designed for superior noise immunity to external radiated and conducted noise Low radiated noise emission System Diagnostics Button shorts Improper value of modulating capacitor (C Parasitic capacitance (C ) value out of range ... -
Page 9: Capsense Technology
2. CapSense Technology 2.1 CapSense Fundamentals CapSense is a touch sensing technology that works by measuring the capacitance of each sensor input pin on the CapSense controller. The total capacitance on each of the sensor pins can be modeled as equivalent lumped capacitors with values of through C as shown in Figure... - Page 10 CapSense Technology Figure 2-2. Section of Typical CapSense PCB with the Sensor Being Activated by a Finger In addition to the parallel plate capacitance, a finger in contact with the overlay causes electric field fringing between itself and other conductors in the immediate vicinity. Typically, the effect of these fringing fields is minor, and it can usually be ignored. Even without a finger touching the overlay, the sensor input pin has some parasitic capacitance (C ).
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Page 11: Capacitive Sensing Method
CapSense Technology 2.2 Capacitive Sensing Method CY8CMBR2010 device supports the CapSense Sigma Delta (CSD) with SmartSense Auto-Tuning for converting sensor capacitance (C ) into digital counts. The CSD method is described in the following sections. 2.2.1 CapSense Sigma-Delta (CSD) The CSD method in the CY8CMBR2010 device incorporates C into a switched capacitor circuit, as shown in Figure 2-3. -
Page 12: Smartsense Auto-Tuning
CapSense Technology 2.3 SmartSense Auto-Tuning Tuning the touch-sensing user interface is critical for proper system operation and a pleasant user experience. Unfortunately, tuning is time-consuming because it is an iterative process. In a typical development cycle, the interface is tuned in the initial design phase, during system integration, and before production ramp. -
Page 13: Capsense Schematic Design
3. CapSense Schematic Design Cypress’s CY8CMBR2010 is hardware-configurable. This section gives an overview of the CapSense controller pins and how to configure them. 3.1 CY8CMBR2010 CapSense Controller Pins Figure 3-1. CY8CMBR2010 Pin Diagram CS 1 CS 7 CS 0 CS 8... -
Page 14: Button Auto Reset (Arst/Emc Pin)
CapSense Schematic Design 3.1.4 Button Auto Reset (ARST/EMC Pin) Button Auto Reset determines the maximum time a button is considered to be ON when CSx is continuously touched. The button is turned OFF after the ARST period. This feature prevents a button from getting stuck if a metal object is placed too close to it. -
Page 15: Flanking Sensor Suppression (Toggle/Fss Pin)
CapSense Schematic Design Figure 3-3. Example of Toggle ON/OFF Feature GPO0 3.1.7 Flanking Sensor Suppression (Toggle/FSS Pin) FSS allows only one CSx to be in the TOUCH state at a time. This means you can distinguish TOUCH states for closely spaced buttons. -
Page 16: Power-On Led Effects (Ledfading Pin)
CapSense Schematic Design Table 3-3 provides some example values for R . Resistor tolerance R should be less than 1 percent. DELAY DELAY Table 3-3. Delay Pin Configuration Approx. LED ON Time Delay Pin Connection Serial Debug Data (ms) Disabled Ground / 300 Ω... - Page 17 CapSense Schematic Design High-brightness time: The time period the LED remains in a high-brightness state Ramp-down time: The time period the LED transitions from high-brightness to low-brightness Repeat rate: The number of times the effects are repeated Power-On LED Effect 1: All LEDs go to high brightness and return to low brightness simultaneously one time as shown in Figure 3-8.
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Page 18: Analog Voltage Support (Ledfading Pin)
CapSense Schematic Design Power-On LED Effect 3: All LEDs go to high brightness and return to low brightness sequentially one time as shown in Figure 3-10. Figure 3-10. Power-on LED Effect 3 with Two Button Design Effects Power on completed 100% Normal Operation... -
Page 19: Backlighting (Backlighting Pin)
CapSense Schematic Design Figure 3-11. A General External Resistive Network Key 1 Host Processor Key 2 The analog voltage support feature of CY8CMBR2010 gives you the option to control these switches using CapSense buttons. Each switch can be replaced with one GPOx. When a CSx button is touched, the corresponding GPOx goes low; therefore, the switch is closed (shorted to ground). -
Page 20: Cs0 Debounce (Cs0Sensitivity Pin)
CapSense Schematic Design The configuration for CS0Sensitivity is shown in Table 3-5. Table 3-5. CS0Sensitivity Pin Configuration CS0Sensitivity Pin Connection CS0Sensitivity CS0 Debounce Ground / Floating High 1.5 kΩ (±5%) resistor to ground High 5.1 kΩ (±5%) resistor to ground High 3.1.13 CS0 Debounce (CS0Sensitivity Pin) Debounce avoids false button triggering from noise spikes or system glitches, by specifying the minimum time a CS0 has to be... - Page 21 CapSense Schematic Design 3.1.14.1 Button Shorted to Ground If any button is found to be shorted to ground, it is disabled. Figure 3-14. Button Shorted to Ground Button CY8CMBR2010 shorting 3.1.14.2 Button Shorted to V If any button is found to be shorted to V , it is disabled.
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Page 22: Button Scan Rate (Scanrate/Sleep Pin)
CapSense Schematic Design 3.1.15 Button Scan Rate (ScanRate/Sleep Pin) The button scan rate specifies the time between successive button scans by the device. Button Scan Rate = Button Scan Rate constant + Button Scan Rate offset Equation 5 An external resistor on the ScanRate/Sleep pin determines the Button Scan Rate offset for the device. You can use Table 3-6 to determine the resistor value. -
Page 23: Sleep Modes (Scanrate/Sleep Pin)
CapSense Schematic Design Button Scan Rate ScanRate/Sleep Pin Connection Offset Response Time Optimized Power Consumption Optimized (ms) 1300 Ω (±1%) resistor to ground 8100 Ω (±1%) resistor to ground 1400 Ω (±1%) resistor to ground 8200 Ω (±1%) resistor to ground 1500 Ω... - Page 24 GPOs. This feature is enabled using a resistor connected between the Delay pin and ground as described in Equation 4 Table 3-3. The Cypress MultiChart Tool can be used to view the data. The serial debug data is sent by the device in the order according Table 3-8.
- Page 25 CapSense Schematic Design Byte Data Notes CS4 and CS5 SNR CS4_CS5_SNR – 0x00 CS6 and CS7 SNR CS6_CS7_SNR System Diagnostics data for CS pins shorted to GND GND_Short_Mask_MSB GND_Short_Mask_LSB – 0x00 0x02 Compensated IDAC IDAC_Comp Gives GPO status for GPO8—GPO9 GPO_Status_Mask_MSB –...
- Page 26 CapSense Schematic Design Table 3-9. Serial Debug Data Arranged in MultiChart Raw Count Array Baseline Array Signal array 0x80 FW Revision 0x00 CS_status_MSB IDAC_Comp GPO_Status_MSB CS0_Cp CS1_Cp 0x00 CS_status_LSB 0x00 GPO_Status_LSB CS0_RawCount CS0_Baseline CS0_DiffCount CS1_RawCount CS1_Baseline CS1_DiffCount CS2_RawCount CS2_Baseline CS2_DiffCount CS3_RawCount CS3_Baseline CS3_DiffCount...
- Page 27 CapSense Schematic Design CMOD_Mask: This contains the information about the C value within range. This byte is written as: If the C value is within range (1—4 nF) If the C value > 4 nF If the C value < 1 nF ...
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Page 28: Design Toolbox
CapSense Schematic Design 3.2 Design Toolbox Design Toolbox helps you to design a CY8CMBR2010 CapSense solution. It offers basic information about the board layout and feature settings and recommends whether the design is fit for mass production. 3.2.1 General Layout Guidelines Table 3-10 summarizes the layout guidelines for the CY8CMBR2010. -
Page 29: Layout Estimator
CapSense Schematic Design 3.2.2 Layout Estimator The Layout Estimator provides minimum button size and maximum trace length recommendations based on the intended end- system requirements and industrial design. The inputs include the overlay material, overlay thickness, trace capacitance of circuit board material, whether CS0 is used in the design, and if so, its sensitivity. Figure 3-17, Table B, lists the dielectric constants for different overlay materials as well as the trace capacitance per unit length for different PCBs. -
Page 30: Power Consumption, And Response Time Calculator
CapSense Schematic Design 3.2.3 C , Power Consumption, and Response Time Calculator After board layout is complete, use the Power Consumption and Response Time Calculator to check your design before building a prototype, as shown in Figure 3-18. To verify the C value of each button, insert the button diameters and trace lengths into Table A. -
Page 31: Design Validation
Select PORT = <Specify Port number> Port Speed = 115200 Visible points = 1000 Log file name = "C:\Program Files\Cypress\CY8CMBR2010.csv" Click on Enable/disable log-file. This will automatically store the data to the log file. Log this data for at least 300 samples. - Page 32 CapSense Schematic Design Inputs Raw Counts Noise Counts Button C If the design fails, note the following: New overlay thickness, overlay material permittivity, and button diameter for each individual button, and trace capacitance Scan rate resistor value used in the design ...
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Page 33: Electrical And Mechanical Design Considerations
4. Electrical and Mechanical Design Considerations When designing a capacitive touch sense technology into your application, it is crucial to remember that the CapSense device exists within a larger framework. Careful attention to every detail, including PCB layout, user interface, and end-user operating environment, leads to robust and reliable system performance. -
Page 34: Bonding Overlay To Pcb
Electrical and Mechanical Design Considerations 4.1.1 Bonding Overlay to PCB Because the dielectric constant of air is very low, an air gap between the overlay and the button degrades the performance of the button. To eliminate the air gap, use a nonconductive adhesive to bond the overlay to the CapSense PCB. A transparent acrylic adhesive film from 3M™... -
Page 35: Electromagnetic Compatibility (Emc) Considerations
Electrical and Mechanical Design Considerations 4.3 Electromagnetic Compatibility (EMC) Considerations 4.3.1 Radiated Interference Radiated electrical energy can influence system measurements and the operation of the processor core. The interference enters the CY8CMBR2010 chip at the PCB level, through CapSense button traces and any other digital or analog inputs. The layout guidelines for minimizing the effects of RF interference include: ... -
Page 36: Low-Power Design Considerations
5. Low-Power Design Considerations 5.1 System Design Recommendations Cypress’s CY8CMBR2010 is designed to meet the low-power requirements for battery-powered applications. To minimize power consumption: Ground all unused CapSense inputs Minimize C using the design guidelines in Getting Started with CapSense ... -
Page 37: Scan Time
Low-Power Design Considerations 5.2.1.1 Response Time Response time is the minimum time the button CSx should be touched for the device to detect a valid button touch and produce a signal on GPOx. Response times are calculated using the following equations: Equation 7 ����... -
Page 38: Average Current In No Touch State (I )
Low-Power Design Considerations Table 5-2. Average Current Parameters Parameter 6.00 ms 6.50 ms From Equation 7 +5% from TYP value From Equation 5 ±10 from Value 1.07 µA 1.50 µA SLEEP 3.4 mA 4.00 mA ACTIVE 5.2.3 Average Current in NO TOUCH State (I AVE_NT ��... -
Page 39: Average Power (Pave )
Low-Power Design Considerations 5.2.7 Average Power (P �� = �� × �� Equation 14 ������ ���� ������ Where: = average current = supply voltage 5.2.8 Example Calculation As an example of how to calculate average power, consider a CapSense user interface with eight well-designed buttons and the following parameters: ... -
Page 40: Sleep Modes
Low-Power Design Considerations 5.3 Sleep Modes Cypress’s CY8CMBR2010 can be configured to operate in either low-power or deep sleep mode. These modes reduce the power consumption of the device. 5.3.1 Low-Power Sleep Mode The behavior of CY8CMBR2010 controller in low-power sleep mode is described in Figure 5-1. -
Page 41: Resources
Toolbox, to help you rapidly design a robust and reliable CY8CMBR2010 CapSense solution. 6.4 Design Support Cypress has a variety of design support channels to ensure the success of your CapSense solutions. –Browse technical articles by product family or perform a search on various CapSense topics. ... -
Page 42: Appendix
A. Appendix Schematic Example A . 1 . 1 S c h e m a t i c 1 : T e n B u t t o n s a n d T e n G P O s Figure 6-1. - Page 43 Appendix pin: 2.2 nF to Ground Modulating capacitor XRES pin: Floating For external reset Toggle/FSS pin: 5.1 kΩ to Ground Toggle ON/OFF disabled FSS enabled ARST/EMC pin: 1.5 kΩ to Ground Button Auto Reset enabled Noise Immunity level ―Normal‖...
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Page 44: Schematic 2: Eight Buttons And Eight Gpos
Appendix A . 1 . 2 S c h e m a t i c 2 : E i g h t B u t t o n s a n d E i g h t G P O s Figure 6-2. -
Page 45: Acronyms
Appendix Toggle/FSS pin: V Toggle ON/OFF enabled FSS enabled ARST/EMC pin: V Button Auto Reset enabled Noise Immunity level ―High‖ LEDFading pin: Ground Analog Voltage Support enabled Power-on LED effects disabled ... -
Page 46: Glossary
® CapSense Cypress’s touch-sensing user interface solution. The industry’s No. 1 solution in sales by 4x over No. 2. CapSense Mechanical Button Replacement (MBR) Cypress’s configurable solution to upgrade mechanical buttons to capacitive buttons, requires minimal engineering effort to configure the sensor parameters and does not require firmware development. - Page 47 Glossary CapSense Sigma Delta (CSD) is a Cypress-patented method of performing self-capacitance (also called self-cap) measurements for capacitive sensing applications. In CSD mode, the sensing system measures the self-capacitance of an electrode, and a change in the self- capacitance is detected to identify the presence or absence of a finger.
- Page 48 Glossary Hysteresis A parameter used to prevent the sensor status output from random toggling due to system noise, used in conjunction with the Finger Threshold to determine the sensor state. See Finger Threshold. IDAC (Current-Output Digital-to-Analog Converter) Programmable constant current source available inside PSoC, used for CapSense and ADC operations. Liquid Tolerance The ability of a capacitive sensing system to work reliably in the presence of liquid droplets, streaming liquids or mist.
- Page 49 Glossary Baseline is updated to track the change in the Raw Count as long as the Raw Count stays within Negative Noise Threshold, that is, the difference between Baseline and Raw count (Baseline – Raw count) is less than Negative Noise Threshold.
- Page 50 Glossary Sensor Capacitive Sensor. Sensor Auto Reset A setting to prevent a sensor from reporting false touch status indefinitely due to system failure, or when a metal object is continuously present near the sensor. When Sensor Auto Reset is enabled, the Baseline is always updated even if the Difference Count is greater than the Noise Threshold.
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Page 51: Revision History
Revision History ® Document Title: AN75999 - CY8CMBR2010 CapSense Design Guide Document Number: 001-75999 Revision Issue Date Origin of Change Description of Change 04/04/2012 UDYG New Design Guide 04/27/2012 GNKK Corrected phone number in the title page 09/26/2012 UDYG Overall content update for reader clarity. Updated Table 3-8, Figure 3-17, Section 4.4, and Schematic 2.
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