Cypress PSoC CY8CTMG200-24LQXI Manuals

Manuals and User Guides for Cypress PSoC CY8CTMG200-24LQXI. We have 1 Cypress PSoC CY8CTMG200-24LQXI manual available for free PDF download: Technical Reference Manual

Cypress PSoC CY8CTMG200-24LQXI Technical Reference Manual (308 pages)

Brand: Cypress | Category: Microcontrollers | Size: 2 MB

Table of Contents
3
Section A: Overview
13
Pin Information
19
Pinouts
19
Section B: Psoc Core
23
CPU Core (M8C)
27
Overview
27
Internal Registers
27
Address Spaces
27
Instruction Set Summary
28
Instruction Formats
30
One-Byte Instructions
30
Two-Byte Instructions
30
Three-Byte Instructions
31
Register Definitions
32
CPU_F Register
32
Related Registers
32
Supervisory ROM (SROM)
33
Architectural Description
33
Additional SROM Feature
34
SROM Function Descriptions
34
Swbootreset Function
34
Readblock Function
35
Writeblock Function
35
Eraseblock Function
36
Protectblock Function
36
Tableread Function
36
Eraseall Function
36
Checksum Function
37
Calibrate0 Function
37
Calibrate1 Function
37
Writeandverify Function
37
Hwbootreset Function
38
Register Definitions
38
RAM Paging
39
Architectural Description
39
Basic Paging
39
Stack Operations
40
Interrupts
40
MVI Instructions
40
Current
40
Index Memory
41
Register Definitions
42
Tmp_Drx Registers
42
CUR_PP Register
42
STK_PP Register
43
IDX_PP Register
43
MVR_PP Register
43
MVW_PP Register
44
Related Registers
44
Interrupt Controller
45
Architectural Description
45
Posted Versus Pending Interrupts
46
Application Overview
46
Register Definitions
48
INT_CLR0 Register
48
INT_CLR1 Register
49
INT_CLR2 Register
50
INT_MSK0 Register
51
INT_MSK1 Register
51
INT_MSK2 Register
52
INT_SW_EN Register
52
INT_VC Register
52
Related Registers
53
General Purpose I/O (GPIO)
55
Architectural Description
55
General Description
56
Digital I/O
56
Analog and Digital Inputs
56
Port 1 Distinctions
56
Port 0 Distinctions
57
GPIO Block Interrupts
57
Interrupt Modes
57
Data Bypass
58
Register Definitions
59
Prtxdr Registers
59
Prtxie Registers
59
Prtxdmx Registers
60
IO_CFG1 Register
61
IO_CFG2 Register
61
Internal Main Oscillator (IMO)
63
Architectural Description
63
Application Overview
63
Trimming the IMO
63
Engaging Slow IMO
63
Register Definitions
64
IMO_TR Register
64
IMO_TR1 Register
64
CPU_SCR1 Register
65
OSC_CR2 Register
65
Related Registers
66
Internal Low Speed Oscillator (ILO)
67
Architectural Description
67
Register Definitions
68
ILO_TR Register
68
External Crystal Oscillator (ECO)
69
Architectural Description
69
Application Overview
70
Register Definitions
71
ECO_ENBUS Register
71
ECO_TRIM Register
71
ECO_CFG Register
71
Related Registers
72
Sleep and Watchdog
73
Architectural Description
73
Sleep Control Implementation Logic
74
Wakeup Logic
74
Sleep Timer
76
Application Overview
76
Register Definitions
77
RES_WDT Register
77
SLP_CFG Register
77
SLP_CFG2 Register
78
SLP_CFG3 Register
78
Related Registers
78
Timing Diagrams
79
Sleep Sequence
79
Wakeup Sequence
80
Bandgap Refresh
80
Watchdog Timer
81
Section C: Truetouch System
83
Truetouch Module
85
Architectural Description
85
Types of Truetouch Approaches
85
Positive Charge Integration
85
Relaxation Oscillator
86
Successive Approximation
87
Negative Charge Integration
88
Sigma Delta
89
Idac
90
Truetouch Counter
90
Operation
91
Register Definitions
92
CS_CR0 Register
92
CS_CR1 Register
93
CS_CR2 Register
93
CS_CR3 Register
94
CS_CNTL Register
94
CS_CNTH Register
94
CS_STAT Register
95
CS_TIMER Register
95
CS_SLEW Register
96
PRS_CR Register
96
IDAC_D Register
97
Timing Diagrams
97
I/O Analog Multiplexer
99
Architectural Description
99
Register Definitions
100
Mux_Crx Registers
100
Comparators
101
Architectural Description
101
Register Definitions
103
CMP_RDC Register
103
CMP_MUX Register
103
CMP_CR0 Register
104
CMP_CR1 Register
104
CMP_LUT Register
104
Section D: System Resources
105
Digital Clocks
109
Architectural Description
109
Internal Main Oscillator
109
Internal Low Speed Oscillator
110
External Clock
110
Switch Operation
110
Register Definitions
112
USB_MISC_CR Register
112
OUT_P0 Register
113
OUT_P1 Register
113
OSC_CR0 Register
113
OSC_CR2 Register
115
I2C Slave
117
Architectural Description
117
Basic I2C Data Transfer
118
Application Overview
118
Slave Operation
118
EZI2C Mode
119
Register Definitions
122
I2C_XCFG Register
122
I2C_XSTAT Register
123
I2C_ADDR Register
123
I2C_BP Register
123
I2C_CP Register
124
CPU_BP Register
124
CPU_CP Register
124
I2C_BUF Register
125
I2C_CFG Register
126
I2C_SCR Register
128
I2C_DR Register
129
Timing Diagrams
130
Clock Generation
130
Basic I/O Timing
130
Status Timing
131
Slave Stall Timing
132
Implementation
132
Compatibility Mode Configuration
133
System Resets
135
Architectural Description
135
Pin Behavior During Reset
135
GPIO Behavior on Power up
135
Powerup External Reset Behavior
136
GPIO Behavior on External Reset
136
Register Definitions
137
CPU_SCR1 Register
137
CPU_SCR0 Register
138
Timing Diagrams
139
Power on Reset
139
External Reset
139
Watchdog Timer Reset
139
Reset Details
141
Power Modes
141
POR and LVD
143
Architectural Description
143
Register Definitions
144
VLT_CR Register
144
VLT_CMP Register
144
Spi
145
Architectural Description
145
SPI Protocol Function
145
SPI Protocol Signal Definitions
146
SPI Master Function
146
Usability Exceptions
146
Block Interrupt
146
SPI Slave Function
146
Block Interrupt
147
Input Synchronization
147
Register Definitions
147
SPI_TXR Register
147
SPI_RXR Register
148
SPI Master Data Register Definitions
148
SPI Slave Data Register Definitions
148
SPI_CR Register
149
SPI Control Register Definitions
149
SPI_CFG Register
150
SPI Configuration Register Definitions
150
Related Registers
150
Timing Diagrams
151
SPI Mode Timing
151
SPIM Timing
152
SPIS Timing
157
Programmable Timer
161
Architectural Description
161
Operation
161
Register Definitions
163
PT0_CFG Register
163
PT1_CFG Register
163
PT2_CFG Register
164
Ptx_Data0 Register
164
Ptx_Data1 Register
164
Full-Speed USB
165
Architectural Description
165
Application Description
165
Usb Sie
165
Usb Sram
166
Psoc Memory Arbiter
166
Oscillator Lock
168
Transceiver
168
USB Suspend
168
Using Standby I2C-USB Sleep Mode for USB Suspend
169
Using Standby or Deep Sleep Modes for USB Suspend
169
Wakeup from Suspend
169
Regulator
169
Register Definitions
171
USB_SOF0 Register
171
USB_CR0 Register
171
USBIO_CR0 Register
172
USBIO_CR1 Register
172
EP0_CR Register
173
EP0_CNT Register
174
Ep0_Drx Register
174
Epx_Cnt1 Register
175
Epx_Cnt0 Register
176
Epx_Cr0 Register
177
Pmax_Wa Register
178
Pmax_Dr Register
179
Pmax_Ra Register
180
USB_CR1 Register
180
IMO_TR1 Register
181
Related Registers
181
Section E: Registers
183
Register Reference
187
Maneuvering Around the Registers
187
Register Conventions
187
Bank 0 Registers
188
Prtxdr
188
Prtxie
189
Spi_Txr
190
Spi_Rxr
191
Spi_Cr
192
Usb_Sof0
193
Usb_Sof1
194
Usb_Cr0
195
Usbio_Cr0
196
Usbio_Cr1
197
Ep0_Cr
198
Ep0_Cnt
199
Ep0_Drx
200
Epx_Cnt0
201
Epx_Cnt1
202
Pmax_Dr
203
Amux_Cfg
204
Cmp_Rdc
205
Cmp_Mux
206
Cmp_Cr0
207
Cmp_Cr1
208
Cmp_Lut
210
Cs_Cr0
211
Cs_Cr1
212
Cs_Cr2
213
Cs_Cr3
214
Cs_Cntl
215
Cs_Cnth
216
Cs_Stat
217
Cs_Timer
218
Cs_Slew
219
Prs_Cr
220
Pt0_Cfg
221
Ptx_Data1
222
Ptx_Data0
223
Pt1_Cfg
224
Pt2_Cfg
225
I2C_Xcfg
226
I2C_Xstat
227
I2C_Addr
228
I2C_Bp
229
I2C_Cp
230
Cpu_Bp
231
Cpu_Cp
232
I2C_Buf
233
Cur_Pp
234
Stk_Pp
235
Idx_Pp
236
Mvr_Pp
237
Mvw_Pp
238
I2C_Cfg
239
I2C_Scr
240
I2C_Dr
241
Int_Clr0
242
Int_Clr1
244
Int_Clr2
246
Int_Msk2
248
Int_Msk1
249
Int_Msk0
250
Int_Sw_En
251
Int_Vc
252
Res_Wdt
253
Cpu_F
254
Idac_D
256
Cpu_Scr1
257
Cpu_Scr0
258
Bank 1 Registers
259
Prtxdm0
259
Prtxdm1
260
Spi_Cfg
261
Usb_Cr1
262
Pmax_Wa
263
Pmax_Ra
264
Epx_Cr0
265
Tmp_Drx
266
Usb_Misc_Cr
267
Out_P0
268
Eco_Enbus
269
Eco_Trim
270
Mux_Crx
271
Io_Cfg1
272
Out_P1
273
Io_Cfg2
275
Osc_Cr0
276
Eco_Cfg
277
Osc_Cr2
278
Vlt_Cr
279
Vlt_Cmp
280
Imo_Tr
281
Ilo_Tr
282
Slp_Cfg
283
Slp_Cfg2
284
Slp_Cfg3
285
Imo_Tr1
286
Section F: Glossary
287
Section F: Index
303

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Cypress PSoC CY8CTMG200-24LQXI Manuals

Cypress PSoC CY8CTMG200-24LQXI Technical Reference Manual (308 pages)

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